[llvm] [AMDGPU][SIInsertWaitcnts] Track SCC. Insert KM_CNT waits for SCC writes. (PR #157843)

[Matt Arsenault via llvm-commits]

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@@ -121,6 +121,7 @@ struct HardwareLimits {
   DECL(LDS_ACCESS)               /* lds read & write */                        \
   DECL(GDS_ACCESS)               /* gds read & write */                        \
   DECL(SQ_MESSAGE)               /* send message */                            \
+  DECL(SCC_WRITE)                /* write to SCC from barrier */               \
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arsenm wrote:

...Is this the same SCC as the condition register? 

https://github.com/llvm/llvm-project/pull/157843