[llvm] c6947da - [RISCV] Add helper method for detecting BEXTI or TH_TST is supported. NFC (#157915)

[via llvm-commits]

Author: Craig Topper
Date: 2025-09-10T12:16:46-07:00
New Revision: c6947dad53dacc19d47b4da6b1984ca39ec111f6

URL: https://github.com/llvm/llvm-project/commit/c6947dad53dacc19d47b4da6b1984ca39ec111f6
DIFF: https://github.com/llvm/llvm-project/commit/c6947dad53dacc19d47b4da6b1984ca39ec111f6.diff

LOG: [RISCV] Add helper method for detecting BEXTI or TH_TST is supported. NFC (#157915)

These instructions both extract single bit to bit 0 and fill the upper
bits with 0.

There's at least one place where we check for BEXTI but not TH_TST. I
wanted to keep this patch NFC so that will be a follow up fix.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVSubtarget.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 756422dfa29e5..c7f15415ebb91 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1052,7 +1052,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
   SDLoc DL(Node);
   MVT VT = Node->getSimpleValueType(0);
 
-  bool HasBitTest = Subtarget->hasStdExtZbs() || Subtarget->hasVendorXTHeadBs();
+  bool HasBitTest = Subtarget->hasBEXTILike();
 
   switch (Opcode) {
   case ISD::Constant: {

diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 409f98b348903..a68a3c14dc41d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2173,7 +2173,7 @@ bool RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial(
   // on the basis that it's possible the sinking+duplication of the AND in
   // CodeGenPrepare triggered by this hook wouldn't decrease the instruction
   // count and would increase code size (e.g. ANDI+BNEZ => BEXTI+BNEZ).
-  if (!Subtarget.hasStdExtZbs() && !Subtarget.hasVendorXTHeadBs())
+  if (!Subtarget.hasBEXTILike())
     return false;
   ConstantInt *Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
   if (!Mask)

diff  --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 4429d760a6cb0..50e76df56e575 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -186,6 +186,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
     return HasStdExtZfhmin || HasStdExtZfbfmin;
   }
 
+  bool hasBEXTILike() const { return HasStdExtZbs || HasVendorXTHeadBs; }
+
   bool hasCZEROLike() const {
     return HasStdExtZicond || HasVendorXVentanaCondOps;
   }