[llvm] AMDGPU/GlobalISel: Add regbanklegalize rules for load and store (PR #153176)

[Petar Avramovic via llvm-commits]

================
@@ -654,54 +657,153 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
     return (*MI.memoperands_begin())->getFlags() & MONoClobber;
   });
 
-  Predicate isNaturalAlignedSmall([](const MachineInstr &MI) -> bool {
+  Predicate isNaturalAligned([](const MachineInstr &MI) -> bool {
+    const MachineMemOperand *MMO = *MI.memoperands_begin();
+    return MMO->getAlign() >= Align(MMO->getSize().getValue());
+  });
+
+  Predicate is8Or16BitMMO([](const MachineInstr &MI) -> bool {
     const MachineMemOperand *MMO = *MI.memoperands_begin();
     const unsigned MemSize = 8 * MMO->getSize().getValue();
-    return (MemSize == 16 && MMO->getAlign() >= Align(2)) ||
-           (MemSize == 8 && MMO->getAlign() >= Align(1));
+    return MemSize == 16 || MemSize == 8;
+  });
+
+  Predicate is32BitMMO([](const MachineInstr &MI) -> bool {
+    const MachineMemOperand *MMO = *MI.memoperands_begin();
+    return 8 * MMO->getSize().getValue() == 32;
   });
 
   auto isUL = !isAtomicMMO && isUniMMO && (isConst || !isVolatileMMO) &&
               (isConst || isInvMMO || isNoClobberMMO);
 
   // clang-format off
+  // TODO: S32Dst, 16-bit any-extending load should not appear on True16 targets
   addRulesForGOpcs({G_LOAD})
-      .Any({{DivB32, DivP0}, {{VgprB32}, {VgprP0}}})
-      .Any({{DivB32, UniP0}, {{VgprB32}, {VgprP0}}})
-
-      .Any({{DivB32, DivP1}, {{VgprB32}, {VgprP1}}})
-      .Any({{{UniB256, UniP1}, isAlign4 && isUL}, {{SgprB256}, {SgprP1}}})
-      .Any({{{UniB512, UniP1}, isAlign4 && isUL}, {{SgprB512}, {SgprP1}}})
-      .Any({{{UniB32, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB32}, {SgprP1}}})
-      .Any({{{UniB64, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB64}, {SgprP1}}})
-      .Any({{{UniB96, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB96}, {SgprP1}}})
-      .Any({{{UniB128, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB128}, {SgprP1}}})
-      .Any({{{UniB256, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB256}, {VgprP1}, SplitLoad}})
-      .Any({{{UniB512, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB512}, {VgprP1}, SplitLoad}})
-
-      .Any({{DivB32, UniP3}, {{VgprB32}, {VgprP3}}})
-      .Any({{{UniB32, UniP3}, isAlign4 && isUL}, {{SgprB32}, {SgprP3}}})
-      .Any({{{UniB32, UniP3}, !isAlign4 || !isUL}, {{UniInVgprB32}, {VgprP3}}})
-
-      .Any({{{DivB256, DivP4}}, {{VgprB256}, {VgprP4}, SplitLoad}})
-      .Any({{{UniB32, UniP4}, isNaturalAlignedSmall && isUL}, {{SgprB32}, {SgprP4}}}, hasSMRDSmall) // i8 and i16 load
-      .Any({{{UniB32, UniP4}, isAlign4 && isUL}, {{SgprB32}, {SgprP4}}})
-      .Any({{{UniB96, UniP4}, isAlign16 && isUL}, {{SgprB96}, {SgprP4}, WidenLoad}}, !hasUnalignedLoads)
-      .Any({{{UniB96, UniP4}, isAlign4 && !isAlign16 && isUL}, {{SgprB96}, {SgprP4}, SplitLoad}}, !hasUnalignedLoads)
-      .Any({{{UniB96, UniP4}, isAlign4 && isUL}, {{SgprB96}, {SgprP4}}}, hasUnalignedLoads)
-      .Any({{{UniB128, UniP4}, isAlign4 && isUL}, {{SgprB128}, {SgprP4}}})
-      .Any({{{UniB256, UniP4}, isAlign4 && isUL}, {{SgprB256}, {SgprP4}}})
-      .Any({{{UniB512, UniP4}, isAlign4 && isUL}, {{SgprB512}, {SgprP4}}})
-      .Any({{{UniB32, UniP4}, !isNaturalAlignedSmall || !isUL}, {{UniInVgprB32}, {VgprP4}}}, hasSMRDSmall) // i8 and i16 load
-      .Any({{{UniB32, UniP4}, !isAlign4 || !isUL}, {{UniInVgprB32}, {VgprP4}}})
-      .Any({{{UniB256, UniP4}, !isAlign4 || !isUL}, {{UniInVgprB256}, {VgprP4}, SplitLoad}})
-      .Any({{{UniB512, UniP4}, !isAlign4 || !isUL}, {{UniInVgprB512}, {VgprP4}, SplitLoad}})
-
-      .Any({{DivB32, P5}, {{VgprB32}, {VgprP5}}});
-
-  addRulesForGOpcs({G_ZEXTLOAD}) // i8 and i16 zero-extending loads
-      .Any({{{UniB32, UniP3}, !isAlign4 || !isUL}, {{UniInVgprB32}, {VgprP3}}})
-      .Any({{{UniB32, UniP4}, !isAlign4 || !isUL}, {{UniInVgprB32}, {VgprP4}}});
+      // flat, addrspace(0), never uniform - flat_load
----------------
petar-avramovic wrote:

https://github.com/llvm/llvm-project/pull/157845

https://github.com/llvm/llvm-project/pull/153176