[clang] [llvm] [RISCV] Enabled debug entry support by default (PR #157703)

[Georgiy Samoylov via llvm-commits]

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@@ -0,0 +1,74 @@
+;; Test RISC-V 64 bit:
+; RUN: llc -emit-call-site-info -stop-after=livedebugvalues -mtriple=riscv64-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK64
+; RUN: llc -force-instr-ref-livedebugvalues=1 -emit-call-site-info -stop-after=livedebugvalues -mtriple=riscv64-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK64
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sga-sc wrote:

Tbh, I just copied these commands from tests for other architectures: 
https://github.com/llvm/llvm-project/blob/main/llvm/test/DebugInfo/Mips/dw_op_entry_value_64bit.ll
https://github.com/llvm/llvm-project/blob/main/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
https://github.com/llvm/llvm-project/blob/main/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir

As I explored, when this option is set, LLVM switches to a model that tracks the values defined by specific instructions ("Instruction References") instead of just physical locations. This allows more precise and robust debug information, especially after complex optimizations that move or transform values between registers, memory, or the stack.

https://github.com/llvm/llvm-project/pull/157703