[llvm] [AArch64][GlobalISel] Add codegen for simd fpcvt intrinsics (PR #157680)

[via llvm-commits]

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@@ -5232,19 +5232,54 @@ defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
 
+defm FCVTAS : SIMDFPTwoScalarFCVT<   0, 0, 0b11100, "fcvtas", int_aarch64_neon_fcvtas>;
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Lukacma wrote:

I can do that, but that will require moving all patterns down, which seems more intrusive than moving couple of instructions up. Why is it so important to keep the instructions in their original location? The description of the section they are moved to matches their behaviour as well.

https://github.com/llvm/llvm-project/pull/157680