[llvm] [AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (PR #157640)
Pierre van Houtryve via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 10 01:23:30 PDT 2025
https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/157640
>From 2a7f810648f3e138ac0da3d515a160da6599078d Mon Sep 17 00:00:00 2001
From: pvanhout <pierre.vanhoutryve at amd.com>
Date: Tue, 9 Sep 2025 12:36:58 +0200
Subject: [PATCH] [AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores
---
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 5 -
.../AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll | 24 +-
.../CodeGen/AMDGPU/atomics-system-scope.ll | 28 +-
llvm/test/CodeGen/AMDGPU/bf16-conversions.ll | 12 +-
.../test/CodeGen/AMDGPU/flat-saddr-atomics.ll | 232 +-
llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll | 194 +-
.../CodeGen/AMDGPU/fp64-atomics-gfx90a.ll | 24 +-
.../AMDGPU/gfx1250-scratch-scope-se.ll | 8 +-
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll | 48 +-
.../CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll | 8 +-
.../test/CodeGen/AMDGPU/loop-prefetch-data.ll | 4 +-
llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll | 2 +-
.../AMDGPU/memory-legalizer-flat-agent.ll | 92 +-
.../AMDGPU/memory-legalizer-flat-lastuse.ll | 8 +-
.../memory-legalizer-flat-nontemporal.ll | 10 +-
.../memory-legalizer-flat-singlethread.ll | 104 +-
.../AMDGPU/memory-legalizer-flat-system.ll | 92 +-
.../AMDGPU/memory-legalizer-flat-volatile.ll | 8 +-
.../AMDGPU/memory-legalizer-flat-wavefront.ll | 102 +-
.../AMDGPU/memory-legalizer-flat-workgroup.ll | 104 +-
.../AMDGPU/memory-legalizer-private-agent.ll | 90 +-
.../memory-legalizer-private-singlethread.ll | 104 +-
.../AMDGPU/memory-legalizer-private-system.ll | 90 +-
.../memory-legalizer-private-wavefront.ll | 104 +-
.../memory-legalizer-private-workgroup.ll | 104 +-
llvm/test/CodeGen/AMDGPU/packed-fp32.ll | 4 +-
llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll | 10 +-
.../CodeGen/AMDGPU/scale-offset-scratch.ll | 6 +-
.../CodeGen/AMDGPU/whole-wave-functions.ll | 3714 ++++++++---------
29 files changed, 2665 insertions(+), 2670 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index f61c0d8f84b29..0be6a9d09379f 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -2655,11 +2655,6 @@ bool SIGfx12CacheControl::finalizeStore(MachineInstr &MI, bool Atomic) const {
return Changed;
}
- // GFX12.5 only: Require SCOPE_SE on stores that may hit the scratch address
- // space.
- if (TII->mayAccessScratchThroughFlat(MI) && Scope == CPol::SCOPE_CU)
- return setScope(MI, CPol::SCOPE_SE);
-
return Changed;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
index e886ea4fc6ac6..7e297f46a780e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
@@ -73,7 +73,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -192,7 +192,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inreg
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
@@ -311,7 +311,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -429,7 +429,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inr
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -547,7 +547,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -666,7 +666,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
@@ -785,7 +785,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -903,7 +903,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inr
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -1021,7 +1021,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -1140,7 +1140,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inreg
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
@@ -1259,7 +1259,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -1377,7 +1377,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inr
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll b/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
index 4bb2a13d02cc7..ef52694910da3 100644
--- a/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
@@ -572,7 +572,7 @@ define double @flat_system_atomic_fadd_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB34_5: ; %Flow1
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s1
@@ -634,7 +634,7 @@ define double @flat_one_as_atomic_fadd_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB35_5: ; %Flow1
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s1
@@ -714,7 +714,7 @@ define double @flat_system_atomic_fmin_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB38_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -758,7 +758,7 @@ define double @flat_one_as_atomic_fmin_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB39_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -826,7 +826,7 @@ define double @flat_system_atomic_fmax_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB42_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -870,7 +870,7 @@ define double @flat_one_as_atomic_fmax_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB43_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1009,7 +1009,7 @@ define i64 @flat_one_as_atomic_min_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_min_i64 v[0:1], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB52_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1052,7 +1052,7 @@ define i64 @flat_system_atomic_min_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_min_i64 v[0:1], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB53_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1095,7 +1095,7 @@ define i64 @flat_one_as_atomic_max_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_i64 v[0:1], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB54_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1138,7 +1138,7 @@ define i64 @flat_system_atomic_max_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_i64 v[0:1], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB55_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1181,7 +1181,7 @@ define i64 @flat_one_as_atomic_umin_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_min_u64 v[0:1], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB56_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1224,7 +1224,7 @@ define i64 @flat_system_atomic_umin_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_min_u64 v[0:1], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB57_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1267,7 +1267,7 @@ define i64 @flat_one_as_atomic_umax_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_u64 v[0:1], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB58_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1310,7 +1310,7 @@ define i64 @flat_system_atomic_umax_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_u64 v[0:1], v[4:5], v[2:3]
-; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB59_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
index 02ead572145f9..752a87ac3cb73 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
@@ -344,7 +344,7 @@ define amdgpu_ps void @fptrunc_f32_to_bf16(float %a, ptr %out) {
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.cvt = fptrunc float %a to bfloat
@@ -380,7 +380,7 @@ define amdgpu_ps void @fptrunc_f32_to_bf16_abs(float %a, ptr %out) {
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, |v0|, s0
-; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.abs = call float @llvm.fabs.f32(float %a)
@@ -417,7 +417,7 @@ define amdgpu_ps void @fptrunc_f32_to_bf16_neg(float %a, ptr %out) {
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, -v0, s0
-; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.neg = fneg float %a
@@ -480,7 +480,7 @@ define amdgpu_ps void @fptrunc_f64_to_bf16(double %a, ptr %out) {
; GFX1250-NEXT: s_or_b32 vcc_lo, vcc_lo, s0
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.cvt = fptrunc double %a to bfloat
@@ -543,7 +543,7 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_neg(double %a, ptr %out) {
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.neg = fneg double %a
@@ -607,7 +607,7 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
-; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.abs = call double @llvm.fabs.f64(double %a)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
index 1bf37d512f845..f8c2ddf0d7d3c 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
@@ -577,7 +577,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn(ptr inreg %sbase, i32 %vof
; GFX1250-SDAG-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
; GFX1250-SDAG-NEXT: s_clause 0x1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
@@ -625,7 +625,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn(ptr inreg %sbase, i32 %vof
; GFX1250-GISEL-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[4:5], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[4:5], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -761,7 +761,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn_neg128(ptr inreg %sbase, i
; GFX1250-SDAG-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
; GFX1250-SDAG-NEXT: s_clause 0x1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
@@ -812,7 +812,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn_neg128(ptr inreg %sbase, i
; GFX1250-GISEL-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[4:5], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[4:5], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -948,7 +948,7 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: v_subrev_nc_u32_e32 v4, s0, v0
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v4, vcc_lo
-; GFX1250-SDAG-NEXT: scratch_store_b64 v0, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v0, v[2:3], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_xchg_saddr_i64_nortn:
@@ -987,7 +987,7 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: v_subrev_nc_u32_e32 v0, s0, v2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc_lo
-; GFX1250-GISEL-NEXT: scratch_store_b64 v0, v[4:5], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v0, v[4:5], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_xchg_saddr_i64_nortn:
@@ -1100,7 +1100,7 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v
; GFX1250-SDAG-NEXT: v_subrev_nc_u32_e32 v4, s0, v0
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v4, vcc_lo
-; GFX1250-SDAG-NEXT: scratch_store_b64 v0, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v0, v[2:3], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_xchg_saddr_i64_nortn_neg128:
@@ -1142,7 +1142,7 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v
; GFX1250-GISEL-NEXT: v_subrev_nc_u32_e32 v0, s0, v2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc_lo
-; GFX1250-GISEL-NEXT: scratch_store_b64 v0, v[4:5], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v0, v[4:5], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_xchg_saddr_i64_nortn_neg128:
@@ -1438,7 +1438,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB18_5
@@ -1486,7 +1486,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_add_nc_u64_e32 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB18_5
@@ -1626,7 +1626,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB19_5
@@ -1677,7 +1677,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_add_nc_u64_e32 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB19_5
@@ -1819,7 +1819,7 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_add_saddr_i64_nortn:
@@ -1861,7 +1861,7 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_add_saddr_i64_nortn:
@@ -1985,7 +1985,7 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_add_saddr_i64_nortn_neg128:
@@ -2030,7 +2030,7 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_add_saddr_i64_nortn_neg128:
@@ -2334,7 +2334,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_sub_nc_u64_e32 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB26_5
@@ -2382,7 +2382,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_sub_nc_u64_e32 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB26_5
@@ -2524,7 +2524,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_sub_nc_u64_e32 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB27_5
@@ -2575,7 +2575,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_sub_nc_u64_e32 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB27_5
@@ -2719,7 +2719,7 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_sub_nc_u64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_sub_saddr_i64_nortn:
@@ -2761,7 +2761,7 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_sub_nc_u64_e32 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_sub_saddr_i64_nortn:
@@ -2887,7 +2887,7 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_sub_nc_u64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_sub_saddr_i64_nortn_neg128:
@@ -2932,7 +2932,7 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_sub_nc_u64_e32 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_sub_saddr_i64_nortn_neg128:
@@ -3239,7 +3239,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_and_b32_e32 v3, v1, v3
; GFX1250-SDAG-NEXT: v_and_b32_e32 v2, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB34_5
@@ -3288,7 +3288,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_and_b32_e32 v2, v0, v4
; GFX1250-GISEL-NEXT: v_and_b32_e32 v3, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB34_5
@@ -3429,7 +3429,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_and_b32_e32 v3, v1, v3
; GFX1250-SDAG-NEXT: v_and_b32_e32 v2, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB35_5
@@ -3481,7 +3481,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_and_b32_e32 v2, v0, v4
; GFX1250-GISEL-NEXT: v_and_b32_e32 v3, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB35_5
@@ -3624,7 +3624,7 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_and_b32_e32 v1, v1, v3
; GFX1250-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_and_saddr_i64_nortn:
@@ -3667,7 +3667,7 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v4
; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_and_saddr_i64_nortn:
@@ -3792,7 +3792,7 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_and_b32_e32 v1, v1, v3
; GFX1250-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_and_saddr_i64_nortn_neg128:
@@ -3838,7 +3838,7 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_and_b32_e32 v0, v0, v4
; GFX1250-GISEL-NEXT: v_and_b32_e32 v1, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_and_saddr_i64_nortn_neg128:
@@ -4143,7 +4143,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn(ptr inreg %sbase, i32 %voffs
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_or_b32_e32 v3, v1, v3
; GFX1250-SDAG-NEXT: v_or_b32_e32 v2, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB42_5
@@ -4192,7 +4192,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_or_b32_e32 v2, v0, v4
; GFX1250-GISEL-NEXT: v_or_b32_e32 v3, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB42_5
@@ -4333,7 +4333,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn_neg128(ptr inreg %sbase, i32
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_or_b32_e32 v3, v1, v3
; GFX1250-SDAG-NEXT: v_or_b32_e32 v2, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB43_5
@@ -4385,7 +4385,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn_neg128(ptr inreg %sbase, i32
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_or_b32_e32 v2, v0, v4
; GFX1250-GISEL-NEXT: v_or_b32_e32 v3, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB43_5
@@ -4528,7 +4528,7 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, i
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_or_b32_e32 v1, v1, v3
; GFX1250-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_or_saddr_i64_nortn:
@@ -4571,7 +4571,7 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, i
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_or_b32_e32 v0, v0, v4
; GFX1250-GISEL-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_or_saddr_i64_nortn:
@@ -4696,7 +4696,7 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vof
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_or_b32_e32 v1, v1, v3
; GFX1250-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_or_saddr_i64_nortn_neg128:
@@ -4742,7 +4742,7 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vof
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_or_b32_e32 v0, v0, v4
; GFX1250-GISEL-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_or_saddr_i64_nortn_neg128:
@@ -5047,7 +5047,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v3, v1, v3
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v2, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB50_5
@@ -5096,7 +5096,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_xor_b32_e32 v2, v0, v4
; GFX1250-GISEL-NEXT: v_xor_b32_e32 v3, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB50_5
@@ -5237,7 +5237,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v3, v1, v3
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v2, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB51_5
@@ -5289,7 +5289,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_xor_b32_e32 v2, v0, v4
; GFX1250-GISEL-NEXT: v_xor_b32_e32 v3, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB51_5
@@ -5432,7 +5432,7 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v1, v1, v3
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_xor_saddr_i64_nortn:
@@ -5475,7 +5475,7 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GFX1250-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_xor_saddr_i64_nortn:
@@ -5600,7 +5600,7 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v1, v1, v3
; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_xor_saddr_i64_nortn_neg128:
@@ -5646,7 +5646,7 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GFX1250-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_xor_saddr_i64_nortn_neg128:
@@ -5916,7 +5916,7 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_max_i64 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB58_5
@@ -5960,7 +5960,7 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_max_i64 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB58_5
@@ -6098,7 +6098,7 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_max_i64 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB59_5
@@ -6145,7 +6145,7 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_max_i64 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB59_5
@@ -6286,7 +6286,7 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_max_i64 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_max_saddr_i64_nortn:
@@ -6325,7 +6325,7 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_max_i64 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_max_saddr_i64_nortn:
@@ -6446,7 +6446,7 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_max_i64 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_max_saddr_i64_nortn_neg128:
@@ -6488,7 +6488,7 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_max_i64 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_max_saddr_i64_nortn_neg128:
@@ -6758,7 +6758,7 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_min_i64 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB66_5
@@ -6802,7 +6802,7 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_min_i64 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB66_5
@@ -6940,7 +6940,7 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_min_i64 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB67_5
@@ -6987,7 +6987,7 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_min_i64 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB67_5
@@ -7128,7 +7128,7 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_min_i64 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_min_saddr_i64_nortn:
@@ -7167,7 +7167,7 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_min_i64 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_min_saddr_i64_nortn:
@@ -7288,7 +7288,7 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_min_i64 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_min_saddr_i64_nortn_neg128:
@@ -7330,7 +7330,7 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_min_i64 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_min_saddr_i64_nortn_neg128:
@@ -7600,7 +7600,7 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn(ptr inreg %sbase, i32 %vof
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_max_u64 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB74_5
@@ -7644,7 +7644,7 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn(ptr inreg %sbase, i32 %vof
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_max_u64 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB74_5
@@ -7782,7 +7782,7 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn_neg128(ptr inreg %sbase, i
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_max_u64 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB75_5
@@ -7829,7 +7829,7 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn_neg128(ptr inreg %sbase, i
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_max_u64 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB75_5
@@ -7970,7 +7970,7 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_max_u64 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_umax_saddr_i64_nortn:
@@ -8009,7 +8009,7 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_max_u64 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_umax_saddr_i64_nortn:
@@ -8130,7 +8130,7 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_max_u64 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_umax_saddr_i64_nortn_neg128:
@@ -8172,7 +8172,7 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_max_u64 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_umax_saddr_i64_nortn_neg128:
@@ -8442,7 +8442,7 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn(ptr inreg %sbase, i32 %vof
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_min_u64 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB82_5
@@ -8486,7 +8486,7 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn(ptr inreg %sbase, i32 %vof
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_min_u64 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB82_5
@@ -8624,7 +8624,7 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn_neg128(ptr inreg %sbase, i
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_min_u64 v[2:3], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB83_5
@@ -8671,7 +8671,7 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn_neg128(ptr inreg %sbase, i
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_min_u64 v[2:3], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB83_5
@@ -8812,7 +8812,7 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_min_u64 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_umin_saddr_i64_nortn:
@@ -8851,7 +8851,7 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_min_u64 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_umin_saddr_i64_nortn:
@@ -8972,7 +8972,7 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v
; GFX1250-SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_min_u64 v[0:1], v[0:1], v[2:3]
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_umin_saddr_i64_nortn_neg128:
@@ -9014,7 +9014,7 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v
; GFX1250-GISEL-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_min_u64 v[0:1], v[0:1], v[4:5]
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_umin_saddr_i64_nortn_neg128:
@@ -9330,7 +9330,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn(ptr inreg %sbase, i32 %
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[6:7]
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v3, v1, v5 :: v_dual_cndmask_b32 v2, v0, v4
-; GFX1250-SDAG-NEXT: scratch_store_b64 v8, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v8, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB90_5
@@ -9380,7 +9380,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn(ptr inreg %sbase, i32 %
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX1250-GISEL-NEXT: v_dual_cndmask_b32 v2, v0, v6 :: v_dual_cndmask_b32 v3, v1, v7
-; GFX1250-GISEL-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB90_5
@@ -9531,7 +9531,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn_neg128(ptr inreg %sbase
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[6:7]
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v3, v1, v5 :: v_dual_cndmask_b32 v2, v0, v4
-; GFX1250-SDAG-NEXT: scratch_store_b64 v8, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v8, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB91_5
@@ -9584,7 +9584,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn_neg128(ptr inreg %sbase
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX1250-GISEL-NEXT: v_dual_cndmask_b32 v2, v0, v6 :: v_dual_cndmask_b32 v3, v1, v7
-; GFX1250-GISEL-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v4, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB91_5
@@ -9737,7 +9737,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffs
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[6:7]
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
-; GFX1250-SDAG-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_cmpxchg_saddr_i64_nortn:
@@ -9781,7 +9781,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffs
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX1250-GISEL-NEXT: v_dual_cndmask_b32 v0, v0, v6 :: v_dual_cndmask_b32 v1, v1, v7
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_cmpxchg_saddr_i64_nortn:
@@ -9915,7 +9915,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[6:7]
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
-; GFX1250-SDAG-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_cmpxchg_saddr_i64_nortn_neg128:
@@ -9962,7 +9962,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX1250-GISEL-NEXT: v_dual_cndmask_b32 v0, v0, v6 :: v_dual_cndmask_b32 v1, v1, v7
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_cmpxchg_saddr_i64_nortn_neg128:
@@ -10238,7 +10238,7 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 1, v[0:1]
; GFX1250-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
-; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB98_5
@@ -10288,7 +10288,7 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB98_5
@@ -10434,7 +10434,7 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 1, v[0:1]
; GFX1250-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
-; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-SDAG-NEXT: s_branch .LBB99_5
@@ -10487,7 +10487,7 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1250-GISEL-NEXT: s_branch .LBB99_5
@@ -10633,7 +10633,7 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 1, v[0:1]
; GFX1250-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v1, 0, v5 :: v_dual_cndmask_b32 v0, 0, v4
-; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_inc_saddr_i64_nortn:
@@ -10675,7 +10675,7 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_inc_saddr_i64_nortn:
@@ -10799,7 +10799,7 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], 1, v[0:1]
; GFX1250-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v1, 0, v5 :: v_dual_cndmask_b32 v0, 0, v4
-; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_inc_saddr_i64_nortn_neg128:
@@ -10844,7 +10844,7 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1250-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc_lo
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_inc_saddr_i64_nortn_neg128:
@@ -11118,7 +11118,7 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-SDAG-NEXT: s_or_b32 vcc_lo, vcc_lo, s0
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1250-SDAG-NEXT: s_branch .LBB106_5
@@ -11169,7 +11169,7 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX1250-GISEL-NEXT: s_or_b32 vcc_lo, vcc_lo, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1250-GISEL-NEXT: s_branch .LBB106_5
@@ -11320,7 +11320,7 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-SDAG-NEXT: s_or_b32 vcc_lo, vcc_lo, s0
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1250-SDAG-NEXT: s_branch .LBB107_5
@@ -11374,7 +11374,7 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX1250-GISEL-NEXT: s_or_b32 vcc_lo, vcc_lo, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v6, v[2:3], off
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1250-GISEL-NEXT: s_branch .LBB107_5
@@ -11525,7 +11525,7 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-SDAG-NEXT: s_or_b32 vcc_lo, vcc_lo, s0
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v0, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_dec_saddr_i64_nortn:
@@ -11568,7 +11568,7 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX1250-GISEL-NEXT: s_or_b32 vcc_lo, vcc_lo, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_dec_saddr_i64_nortn:
@@ -11697,7 +11697,7 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG-NEXT: s_or_b32 vcc_lo, vcc_lo, s0
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v0, v0, v2
-; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 v4, v[0:1], off
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_dec_saddr_i64_nortn_neg128:
@@ -11743,7 +11743,7 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX1250-GISEL-NEXT: s_or_b32 vcc_lo, vcc_lo, s0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5
-; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 v2, v[0:1], off
; GFX1250-GISEL-NEXT: s_endpgm
;
; GFX950-SDAG-LABEL: flat_dec_saddr_i64_nortn_neg128:
@@ -11878,7 +11878,7 @@ define double @flat_atomic_fadd_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s2
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_add_f64_e32 v[4:5], v[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[4:5], s2 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[4:5], s2
; GFX1250-SDAG-NEXT: .LBB110_6: ; %Flow1
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_cbranch_execnz .LBB110_8
@@ -11933,7 +11933,7 @@ define double @flat_atomic_fadd_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-GISEL-NEXT: scratch_load_b64 v[2:3], off, s2
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_add_f64_e32 v[4:5], v[2:3], v[0:1]
-; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[4:5], s2 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[4:5], s2
; GFX1250-GISEL-NEXT: .LBB110_5: ; %Flow1
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_mov_b32 s2, 0
@@ -12102,7 +12102,7 @@ define void @flat_atomic_fadd_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s2
; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX1250-SDAG-NEXT: v_add_f64_e32 v[2:3], v[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[2:3], s2 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[2:3], s2
; GFX1250-SDAG-NEXT: .LBB111_7: ; %Flow1
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: s_cbranch_execnz .LBB111_2
@@ -12153,7 +12153,7 @@ define void @flat_atomic_fadd_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-GISEL-NEXT: scratch_load_b64 v[2:3], off, s2
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: v_add_f64_e32 v[2:3], v[2:3], v[0:1]
-; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[2:3], s2 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[2:3], s2
; GFX1250-GISEL-NEXT: .LBB111_5: ; %Flow1
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: s_mov_b32 s2, 0
@@ -12304,7 +12304,7 @@ define double @flat_atomic_fmax_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[0:1]
-; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: .LBB112_4: ; %atomicrmw.end
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
@@ -12345,7 +12345,7 @@ define double @flat_atomic_fmax_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[0:1]
-; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-GISEL-NEXT: .LBB112_4: ; %atomicrmw.end
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
@@ -12460,7 +12460,7 @@ define void @flat_atomic_fmax_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-LABEL: flat_atomic_fmax_f64_saddr_nortn:
@@ -12498,7 +12498,7 @@ define void @flat_atomic_fmax_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[0:1], v[2:3], v[0:1]
-; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-GISEL-NEXT: .LBB113_4: ; %atomicrmw.phi
; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
;
@@ -12605,7 +12605,7 @@ define double @flat_atomic_fmin_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[0:1]
-; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: .LBB114_4: ; %atomicrmw.end
; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
@@ -12646,7 +12646,7 @@ define double @flat_atomic_fmin_f64_saddr_rtn(ptr inreg %ptr, double %data) {
; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[4:5], v[0:1]
-; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-GISEL-NEXT: .LBB114_4: ; %atomicrmw.end
; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
@@ -12761,7 +12761,7 @@ define void @flat_atomic_fmin_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
-; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-LABEL: flat_atomic_fmin_f64_saddr_nortn:
@@ -12799,7 +12799,7 @@ define void @flat_atomic_fmin_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-GISEL-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
-; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1250-GISEL-NEXT: .LBB115_4: ; %atomicrmw.phi
; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
index 4e9a74a912ce1..32888d2acf1cd 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
@@ -9,7 +9,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr(ptr inreg %sbase, ptr %voff
; GFX1250: ; %bb.0:
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b8 v0, v2, s[2:3] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b8 v0, v2, s[2:3]
; GFX1250-NEXT: s_endpgm
%voffset = load i32, ptr %voffset.ptr
%zext.offset = zext i32 %voffset to i64
@@ -24,7 +24,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_2047(ptr inreg %sbas
; GFX1250: ; %bb.0:
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b8 v0, v2, s[2:3] offset:2047 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b8 v0, v2, s[2:3] offset:2047
; GFX1250-NEXT: s_endpgm
%voffset = load i32, ptr %voffset.ptr
%zext.offset = zext i32 %voffset to i64
@@ -40,7 +40,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_neg2048(ptr inreg %s
; GFX1250: ; %bb.0:
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b8 v0, v2, s[2:3] offset:-2048 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b8 v0, v2, s[2:3] offset:-2048
; GFX1250-NEXT: s_endpgm
%voffset = load i32, ptr %voffset.ptr
%zext.offset = zext i32 %voffset to i64
@@ -65,7 +65,7 @@ define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 %d
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v2
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-SDAG-NEXT: flat_store_b8 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b8 v0, v1, s[0:1]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_uniform_ptr_in_vgprs:
@@ -76,7 +76,7 @@ define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 %d
; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
-; GFX1250-GISEL-NEXT: flat_store_b8 v[2:3], v1 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b8 v[2:3], v1
; GFX1250-GISEL-NEXT: s_endpgm
%sbase = load ptr, ptr addrspace(3) @ptr.in.lds
%zext.offset = zext i32 %voffset to i64
@@ -94,7 +94,7 @@ define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voff
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v2
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1250-SDAG-NEXT: flat_store_b8 v0, v1, s[0:1] offset:-120 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b8 v0, v1, s[0:1] offset:-120
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_uniform_ptr_in_vgprs_immoffset:
@@ -105,7 +105,7 @@ define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voff
; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
-; GFX1250-GISEL-NEXT: flat_store_b8 v[2:3], v1 offset:-120 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b8 v[2:3], v1 offset:-120
; GFX1250-GISEL-NEXT: s_endpgm
%sbase = load ptr, ptr addrspace(3) @ptr.in.lds
%zext.offset = zext i32 %voffset to i64
@@ -122,7 +122,7 @@ define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voff
define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr(ptr inreg %sbase, i32 %voffset, i16 %data) {
; GFX1250-LABEL: flat_store_saddr_i16_zext_vgpr:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -133,7 +133,7 @@ define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr(ptr inreg %sbase, i32 %vof
define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, i16 %data) {
; GFX1250-LABEL: flat_store_saddr_i16_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -145,7 +145,7 @@ define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr_offset_neg128(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr(ptr inreg %sbase, i32 %voffset, half %data) {
; GFX1250-LABEL: flat_store_saddr_f16_zext_vgpr:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -156,7 +156,7 @@ define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr(ptr inreg %sbase, i32 %vof
define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, half %data) {
; GFX1250-LABEL: flat_store_saddr_f16_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b16 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -168,7 +168,7 @@ define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr_offset_neg128(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr(ptr inreg %sbase, i32 %voffset, i32 %data) {
; GFX1250-LABEL: flat_store_saddr_i32_zext_vgpr:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -179,7 +179,7 @@ define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr(ptr inreg %sbase, i32 %vof
define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, i32 %data) {
; GFX1250-LABEL: flat_store_saddr_i32_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -191,7 +191,7 @@ define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr_offset_neg128(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr(ptr inreg %sbase, i32 %voffset, float %data) {
; GFX1250-LABEL: flat_store_saddr_f32_zext_vgpr:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -202,7 +202,7 @@ define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr(ptr inreg %sbase, i32 %vof
define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, float %data) {
; GFX1250-LABEL: flat_store_saddr_f32_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -214,7 +214,7 @@ define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr_offset_neg128(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr(ptr inreg %sbase, i32 %voffset, ptr addrspace(3) %data) {
; GFX1250-LABEL: flat_store_saddr_p3_zext_vgpr:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -225,7 +225,7 @@ define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr(ptr inreg %sbase, i32 %voff
define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, ptr addrspace(3) %data) {
; GFX1250-LABEL: flat_store_saddr_p3_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -238,13 +238,13 @@ define amdgpu_ps void @flat_store_saddr_i64_zext_vgpr(ptr inreg %sbase, i32 %vof
; GFX1250-SDAG-LABEL: flat_store_saddr_i64_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_i64_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -256,13 +256,13 @@ define amdgpu_ps void @flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr inreg %s
; GFX1250-SDAG-LABEL: flat_store_saddr_i64_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_i64_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -275,13 +275,13 @@ define amdgpu_ps void @flat_store_saddr_f64_zext_vgpr(ptr inreg %sbase, i32 %vof
; GFX1250-SDAG-LABEL: flat_store_saddr_f64_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_f64_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -293,13 +293,13 @@ define amdgpu_ps void @flat_store_saddr_f64_zext_vgpr_offset_neg128(ptr inreg %s
; GFX1250-SDAG-LABEL: flat_store_saddr_f64_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_f64_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -312,13 +312,13 @@ define amdgpu_ps void @flat_store_saddr_v2i32_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG-LABEL: flat_store_saddr_v2i32_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2i32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -330,13 +330,13 @@ define amdgpu_ps void @flat_store_saddr_v2i32_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG-LABEL: flat_store_saddr_v2i32_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2i32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -349,13 +349,13 @@ define amdgpu_ps void @flat_store_saddr_v2f32_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG-LABEL: flat_store_saddr_v2f32_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2f32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -367,13 +367,13 @@ define amdgpu_ps void @flat_store_saddr_v2f32_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG-LABEL: flat_store_saddr_v2f32_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2f32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -386,13 +386,13 @@ define amdgpu_ps void @flat_store_saddr_v4i16_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG-LABEL: flat_store_saddr_v4i16_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4i16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -404,13 +404,13 @@ define amdgpu_ps void @flat_store_saddr_v4i16_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG-LABEL: flat_store_saddr_v4i16_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4i16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -423,13 +423,13 @@ define amdgpu_ps void @flat_store_saddr_v4f16_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG-LABEL: flat_store_saddr_v4f16_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4f16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -441,13 +441,13 @@ define amdgpu_ps void @flat_store_saddr_v4f16_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG-LABEL: flat_store_saddr_v4f16_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4f16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -460,13 +460,13 @@ define amdgpu_ps void @flat_store_saddr_p1_zext_vgpr(ptr inreg %sbase, i32 %voff
; GFX1250-SDAG-LABEL: flat_store_saddr_p1_zext_vgpr:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_p1_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -478,13 +478,13 @@ define amdgpu_ps void @flat_store_saddr_p1_zext_vgpr_offset_neg128(ptr inreg %sb
; GFX1250-SDAG-LABEL: flat_store_saddr_p1_zext_vgpr_offset_neg128:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v0, v[2:3], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_p1_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
-; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v0, v[4:5], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -498,14 +498,14 @@ define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v3i32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
-; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -518,14 +518,14 @@ define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v3i32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
-; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -539,14 +539,14 @@ define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v3f32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
-; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -559,14 +559,14 @@ define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v3f32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
-; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -580,14 +580,14 @@ define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v6i16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
-; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -600,14 +600,14 @@ define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v6i16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
-; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -621,14 +621,14 @@ define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v6f16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
-; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -641,14 +641,14 @@ define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b96 v0, v[2:4], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v6f16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3
-; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b96 v0, v[4:6], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -662,14 +662,14 @@ define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4i32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -682,14 +682,14 @@ define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4i32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -703,14 +703,14 @@ define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4f32_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -723,14 +723,14 @@ define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4f32_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -744,14 +744,14 @@ define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2i64_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -764,14 +764,14 @@ define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2i64_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -785,14 +785,14 @@ define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2f64_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -805,14 +805,14 @@ define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2f64_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -826,14 +826,14 @@ define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v8i16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -846,14 +846,14 @@ define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v8i16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -867,14 +867,14 @@ define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr(ptr inreg %sbase, i32 %v
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v8f16_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -887,14 +887,14 @@ define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr_offset_neg128(ptr inreg
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v8f16_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -908,14 +908,14 @@ define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2p1_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -928,14 +928,14 @@ define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr_offset_neg128(ptr inreg %
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v2p1_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -949,14 +949,14 @@ define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr(ptr inreg %sbase, i32 %vo
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4p3_zext_vgpr:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -969,14 +969,14 @@ define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr_offset_neg128(ptr inreg %
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
-; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b128 v0, v[2:5], s[2:3] offset:-128
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: flat_store_saddr_v4p3_zext_vgpr_offset_neg128:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4
-; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b128 v0, v[6:9], s[2:3] offset:-128
; GFX1250-GISEL-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -1068,7 +1068,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr i
define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr(ptr inreg %sbase, i32 %voffset, <2 x i16> %data) {
; GFX1250-LABEL: flat_store_saddr_i16_d16hi_zext_vgpr:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_d16_hi_b16 v0, v1, s[2:3] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_d16_hi_b16 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -1080,7 +1080,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr(ptr inreg %sbase, i3
define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <2 x i16> %data) {
; GFX1250-LABEL: flat_store_saddr_i16_d16hi_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_d16_hi_b16 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_d16_hi_b16 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -1093,7 +1093,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(ptr in
define amdgpu_ps void @flat_store_saddr_i16_d16hi_trunci8_zext_vgpr(ptr inreg %sbase, i32 %voffset, <2 x i16> %data) {
; GFX1250-LABEL: flat_store_saddr_i16_d16hi_trunci8_zext_vgpr:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_d16_hi_b8 v0, v1, s[2:3] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_d16_hi_b8 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
@@ -1106,7 +1106,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_trunci8_zext_vgpr(ptr inreg %s
define amdgpu_ps void @flat_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128(ptr inreg %sbase, i32 %voffset, <2 x i16> %data) {
; GFX1250-LABEL: flat_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: flat_store_d16_hi_b8 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_d16_hi_b8 v0, v1, s[2:3] offset:-128
; GFX1250-NEXT: s_endpgm
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr %sbase, i64 %zext.offset
diff --git a/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
index 160b35352d8a4..6484c2f82ff94 100644
--- a/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
@@ -74,7 +74,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -193,7 +193,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inreg
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
@@ -312,7 +312,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -430,7 +430,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inr
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -548,7 +548,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -667,7 +667,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
@@ -786,7 +786,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -904,7 +904,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inr
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -1022,7 +1022,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -1141,7 +1141,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inreg
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
@@ -1260,7 +1260,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -1378,7 +1378,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inr
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/gfx1250-scratch-scope-se.ll b/llvm/test/CodeGen/AMDGPU/gfx1250-scratch-scope-se.ll
index 99025f0a983c0..f0c9258358316 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx1250-scratch-scope-se.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx1250-scratch-scope-se.ll
@@ -9,7 +9,7 @@ define void @test_scratch_store(ptr addrspace(5) %ptr, i32 %val) {
; GCN: ; %bb.0:
; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: scratch_store_b32 v0, v1, off scope:SCOPE_SE
+; GCN-NEXT: scratch_store_b32 v0, v1, off
; GCN-NEXT: s_set_pc_i64 s[30:31]
store i32 %val, ptr addrspace(5) %ptr
ret void
@@ -20,7 +20,7 @@ define void @test_unknown_flat_store(ptr %ptr, i32 %val) {
; GCN: ; %bb.0:
; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GCN-NEXT: flat_store_b32 v[0:1], v2
; GCN-NEXT: s_wait_dscnt 0x0
; GCN-NEXT: s_set_pc_i64 s[30:31]
store i32 %val, ptr %ptr
@@ -65,7 +65,7 @@ define void @test_flat_store_select(ptr addrspace(1) %a, ptr addrspace(3) %b, i1
; GCN-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GCN-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GCN-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v2, v0
-; GCN-SDAG-NEXT: flat_store_b32 v[0:1], v4 scope:SCOPE_SE
+; GCN-SDAG-NEXT: flat_store_b32 v[0:1], v4
; GCN-SDAG-NEXT: s_wait_dscnt 0x0
; GCN-SDAG-NEXT: s_set_pc_i64 s[30:31]
;
@@ -81,7 +81,7 @@ define void @test_flat_store_select(ptr addrspace(1) %a, ptr addrspace(3) %b, i1
; GCN-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GCN-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GCN-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GCN-GISEL-NEXT: flat_store_b32 v[0:1], v4 scope:SCOPE_SE
+; GCN-GISEL-NEXT: flat_store_b32 v[0:1], v4
; GCN-GISEL-NEXT: s_wait_dscnt 0x0
; GCN-GISEL-NEXT: s_set_pc_i64 s[30:31]
%a.ascast = addrspacecast ptr addrspace(1) %a to ptr
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
index 57967bc1650fe..559b1b171031d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
@@ -16,7 +16,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_v:
@@ -27,7 +27,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, s2
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_v:
@@ -38,7 +38,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_v:
@@ -49,7 +49,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, s2
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 %src) #0
store i16 %cvt, ptr %out, align 2
@@ -63,7 +63,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s8
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
@@ -72,7 +72,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, s8
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_s:
@@ -83,7 +83,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
@@ -94,7 +94,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, s2
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 %src) #0
store i16 %cvt, ptr %out, align 2
@@ -108,7 +108,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, 0x64
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_i:
@@ -117,7 +117,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, 0x64
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_i:
@@ -126,7 +126,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, 0x64
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_i:
@@ -135,7 +135,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, 0x64
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 100) #0
store i16 %cvt, ptr %out, align 2
@@ -151,7 +151,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_v:
@@ -162,7 +162,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, s2
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_v:
@@ -173,7 +173,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_v:
@@ -184,7 +184,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, s2
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 %src) #0
store i16 %cvt, ptr %out, align 2
@@ -198,7 +198,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s8
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
@@ -207,7 +207,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, s8
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_s:
@@ -218,7 +218,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
@@ -229,7 +229,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, s2
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 %src) #0
store i16 %cvt, ptr %out, align 2
@@ -243,7 +243,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, 0x64
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_i:
@@ -252,7 +252,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, 0x64
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_i:
@@ -261,7 +261,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, 0x64
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_i:
@@ -270,7 +270,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, 0x64
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 100) #0
store i16 %cvt, ptr %out, align 2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
index d2f96c402d50e..9705843087100 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
@@ -12,7 +12,7 @@ define void @test_perm_pk16_b4_u4(i32 %a, i32 %b, <2 x i32> %c, ptr %out) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_perm_pk16_b4_u4 v[0:1], v0, v1, v[2:3]
-; GFX1250-NEXT: flat_store_b64 v[4:5], v[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b64 v[4:5], v[0:1]
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%ret = tail call <2 x i32> @llvm.amdgcn.perm.pk16.b4.u4(i32 %a, i32 %b, <2 x i32> %c)
@@ -30,7 +30,7 @@ define void @test_perm_pk16_b6_u4(i32 %a, i64 %b, <2 x i32> %c, ptr %out) {
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v6, v5
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT: v_perm_pk16_b6_u4 v[0:2], v0, v[2:3], v[8:9]
-; GFX1250-SDAG-NEXT: flat_store_b96 v[6:7], v[0:2] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b96 v[6:7], v[0:2]
; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
;
@@ -43,7 +43,7 @@ define void @test_perm_pk16_b6_u4(i32 %a, i64 %b, <2 x i32> %c, ptr %out) {
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-GISEL-NEXT: v_perm_pk16_b6_u4 v[0:2], v0, v[8:9], v[2:3]
-; GFX1250-GISEL-NEXT: flat_store_b96 v[4:5], v[0:2] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b96 v[4:5], v[0:2]
; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0
; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
%ret = tail call <3 x i32> @llvm.amdgcn.perm.pk16.b6.u4(i32 %a, i64 %b, <2 x i32> %c)
@@ -57,7 +57,7 @@ define void @test_perm_pk16_b8_u4(i64 %a, i64 %b, <2 x i32> %c, ptr %out) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_perm_pk16_b8_u4 v[0:3], v[0:1], v[2:3], v[4:5]
-; GFX1250-NEXT: flat_store_b128 v[6:7], v[0:3] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b128 v[6:7], v[0:3]
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%ret = tail call <4 x i32> @llvm.amdgcn.perm.pk16.b8.u4(i64 %a, i64 %b, <2 x i32> %c)
diff --git a/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll b/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
index 702a69f776de3..ea9d5e8a0bc1f 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
@@ -77,7 +77,7 @@ define amdgpu_kernel void @copy_flat(ptr nocapture %d, ptr nocapture readonly %s
; GFX1250-NEXT: s_add_nc_u64 s[2:3], s[2:3], 16
; GFX1250-NEXT: s_cmp_lg_u32 s6, 0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b128 v0, v[2:5], s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b128 v0, v[2:5], s[0:1]
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], 16
; GFX1250-NEXT: s_cbranch_scc1 .LBB0_2
@@ -490,7 +490,7 @@ define amdgpu_kernel void @copy_flat_divergent(ptr nocapture %d, ptr nocapture r
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_cmp_lg_u32 s0, 0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b128 v[0:1], v[4:7] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b128 v[0:1], v[4:7]
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], 16, v[0:1]
; GFX1250-NEXT: s_cbranch_scc1 .LBB4_2
diff --git a/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll b/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
index 836e88c2d3636..1112be3aeac07 100644
--- a/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
@@ -409,7 +409,7 @@ define amdgpu_ps float @mad_i32_vvv_multiuse(i32 %a, i32 %b, i32 %c) {
; GFX1250: ; %bb.0:
; GFX1250-NEXT: v_mul_lo_u32 v1, v0, v1
; GFX1250-NEXT: v_add_nc_u32_e32 v0, v1, v2
-; GFX1250-NEXT: flat_store_b32 v[0:1], v1 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v1
; GFX1250-NEXT: s_wait_dscnt 0x0
; GFX1250-NEXT: ; return to shader part epilog
%mul = mul i32 %a, %b
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
index 55ec0c2255f9b..4caaad646378d 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
@@ -197,7 +197,7 @@ define amdgpu_kernel void @flat_agent_unordered_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -390,7 +390,7 @@ define amdgpu_kernel void @flat_agent_monotonic_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -599,7 +599,7 @@ define amdgpu_kernel void @flat_agent_acquire_load(
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -836,7 +836,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_load(
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -997,7 +997,7 @@ define amdgpu_kernel void @flat_agent_unordered_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -2733,7 +2733,7 @@ define amdgpu_kernel void @flat_agent_acquire_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -2987,7 +2987,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -3241,7 +3241,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -8061,7 +8061,7 @@ define amdgpu_kernel void @flat_agent_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8378,7 +8378,7 @@ define amdgpu_kernel void @flat_agent_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8706,7 +8706,7 @@ define amdgpu_kernel void @flat_agent_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9054,7 +9054,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9402,7 +9402,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9723,7 +9723,7 @@ define amdgpu_kernel void @flat_agent_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10040,7 +10040,7 @@ define amdgpu_kernel void @flat_agent_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10388,7 +10388,7 @@ define amdgpu_kernel void @flat_agent_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10736,7 +10736,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11084,7 +11084,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11432,7 +11432,7 @@ define amdgpu_kernel void @flat_agent_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11776,7 +11776,7 @@ define amdgpu_kernel void @flat_agent_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -12124,7 +12124,7 @@ define amdgpu_kernel void @flat_agent_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -12472,7 +12472,7 @@ define amdgpu_kernel void @flat_agent_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -12820,7 +12820,7 @@ define amdgpu_kernel void @flat_agent_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -13015,7 +13015,7 @@ define amdgpu_kernel void @flat_agent_one_as_unordered_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -13208,7 +13208,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -13428,7 +13428,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_load(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -13676,7 +13676,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_load(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -13837,7 +13837,7 @@ define amdgpu_kernel void @flat_agent_one_as_unordered_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -15572,7 +15572,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -15837,7 +15837,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -16102,7 +16102,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -20870,7 +20870,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21198,7 +21198,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21526,7 +21526,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21885,7 +21885,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -22244,7 +22244,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -22576,7 +22576,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -22904,7 +22904,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -23263,7 +23263,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -23622,7 +23622,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -23981,7 +23981,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -24340,7 +24340,7 @@ define amdgpu_kernel void @flat_agent_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -24695,7 +24695,7 @@ define amdgpu_kernel void @flat_agent_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -25054,7 +25054,7 @@ define amdgpu_kernel void @flat_agent_one_as_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -25413,7 +25413,7 @@ define amdgpu_kernel void @flat_agent_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -25772,7 +25772,7 @@ define amdgpu_kernel void @flat_agent_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
index faa970e049bd2..c9e61c6ab5d42 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
@@ -26,7 +26,7 @@ define amdgpu_kernel void @flat_last_use_load_0(ptr %in, ptr %out) {
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] th:TH_LOAD_LU
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
entry:
%val = load i32, ptr %in, align 4, !amdgpu.last.use !{}
@@ -79,7 +79,7 @@ define amdgpu_kernel void @flat_last_use_load_1(ptr %in, ptr %out) {
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v1, s[2:3] scale_offset th:TH_LOAD_LU
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -115,7 +115,7 @@ define amdgpu_kernel void @flat_last_use_and_volatile_load(ptr %in, ptr %out) {
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
entry:
%val = load volatile i32, ptr %in, align 4, !amdgpu.last.use !{}
@@ -146,7 +146,7 @@ define amdgpu_kernel void @flat_last_use_and_nontemporal_load(ptr %in, ptr %out)
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] th:TH_LOAD_LU
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
entry:
%val = load i32, ptr %in, align 4, !amdgpu.last.use !{}, !nontemporal !0
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
index 721ecd8da5387..ec6ec4328db87 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
@@ -197,7 +197,7 @@ define amdgpu_kernel void @flat_nontemporal_load_0(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] th:TH_LOAD_NT
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -568,7 +568,7 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v1, s[2:3] scale_offset th:TH_LOAD_NT
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -763,7 +763,7 @@ define amdgpu_kernel void @flat_nontemporal_store_0(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] th:TH_STORE_NT scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] th:TH_STORE_NT
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -1121,7 +1121,7 @@ define amdgpu_kernel void @flat_nontemporal_store_1(
; GFX1250-NEXT: s_mov_b32 s2, 0x3ff
; GFX1250-NEXT: v_and_b32_e64 v0, v0, s2
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scale_offset th:TH_STORE_NT scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scale_offset th:TH_STORE_NT
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -1330,7 +1330,7 @@ define amdgpu_kernel void @flat_nontemporal_volatile_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] th:TH_LOAD_NT scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
index 635895259ee32..a05f4c718c351 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
@@ -197,7 +197,7 @@ define amdgpu_kernel void @flat_singlethread_unordered_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -390,7 +390,7 @@ define amdgpu_kernel void @flat_singlethread_monotonic_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -583,7 +583,7 @@ define amdgpu_kernel void @flat_singlethread_acquire_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -776,7 +776,7 @@ define amdgpu_kernel void @flat_singlethread_seq_cst_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -937,7 +937,7 @@ define amdgpu_kernel void @flat_singlethread_unordered_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -1097,7 +1097,7 @@ define amdgpu_kernel void @flat_singlethread_monotonic_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -1257,7 +1257,7 @@ define amdgpu_kernel void @flat_singlethread_release_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -1417,7 +1417,7 @@ define amdgpu_kernel void @flat_singlethread_seq_cst_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -2423,7 +2423,7 @@ define amdgpu_kernel void @flat_singlethread_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -2630,7 +2630,7 @@ define amdgpu_kernel void @flat_singlethread_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -2837,7 +2837,7 @@ define amdgpu_kernel void @flat_singlethread_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -6931,7 +6931,7 @@ define amdgpu_kernel void @flat_singlethread_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -7232,7 +7232,7 @@ define amdgpu_kernel void @flat_singlethread_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -7533,7 +7533,7 @@ define amdgpu_kernel void @flat_singlethread_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -7834,7 +7834,7 @@ define amdgpu_kernel void @flat_singlethread_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8135,7 +8135,7 @@ define amdgpu_kernel void @flat_singlethread_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8436,7 +8436,7 @@ define amdgpu_kernel void @flat_singlethread_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8737,7 +8737,7 @@ define amdgpu_kernel void @flat_singlethread_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9038,7 +9038,7 @@ define amdgpu_kernel void @flat_singlethread_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9339,7 +9339,7 @@ define amdgpu_kernel void @flat_singlethread_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9640,7 +9640,7 @@ define amdgpu_kernel void @flat_singlethread_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9941,7 +9941,7 @@ define amdgpu_kernel void @flat_singlethread_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10242,7 +10242,7 @@ define amdgpu_kernel void @flat_singlethread_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10543,7 +10543,7 @@ define amdgpu_kernel void @flat_singlethread_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10844,7 +10844,7 @@ define amdgpu_kernel void @flat_singlethread_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11145,7 +11145,7 @@ define amdgpu_kernel void @flat_singlethread_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11340,7 +11340,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_unordered_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -11533,7 +11533,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_monotonic_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -11726,7 +11726,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_acquire_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -11919,7 +11919,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_seq_cst_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -12080,7 +12080,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_unordered_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -12240,7 +12240,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_monotonic_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -12400,7 +12400,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_release_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -12560,7 +12560,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_seq_cst_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -13566,7 +13566,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -13773,7 +13773,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -13980,7 +13980,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -18074,7 +18074,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_monotonic_monotonic_ret_cmpx
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -18375,7 +18375,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_acquire_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -18676,7 +18676,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_release_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -18977,7 +18977,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_acq_rel_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -19278,7 +19278,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_seq_cst_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -19579,7 +19579,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_monotonic_acquire_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -19880,7 +19880,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -20181,7 +20181,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -20482,7 +20482,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -20783,7 +20783,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21084,7 +21084,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_monotonic_seq_cst_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21385,7 +21385,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21686,7 +21686,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21987,7 +21987,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -22288,7 +22288,7 @@ define amdgpu_kernel void @flat_singlethread_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
index e45a8e51c836c..265c8c409f2d6 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
@@ -197,7 +197,7 @@ define amdgpu_kernel void @flat_system_unordered_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -390,7 +390,7 @@ define amdgpu_kernel void @flat_system_monotonic_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -601,7 +601,7 @@ define amdgpu_kernel void @flat_system_acquire_load(
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -840,7 +840,7 @@ define amdgpu_kernel void @flat_system_seq_cst_load(
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -1001,7 +1001,7 @@ define amdgpu_kernel void @flat_system_unordered_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -2765,7 +2765,7 @@ define amdgpu_kernel void @flat_system_acquire_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -3025,7 +3025,7 @@ define amdgpu_kernel void @flat_system_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -3285,7 +3285,7 @@ define amdgpu_kernel void @flat_system_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -8175,7 +8175,7 @@ define amdgpu_kernel void @flat_system_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8494,7 +8494,7 @@ define amdgpu_kernel void @flat_system_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8826,7 +8826,7 @@ define amdgpu_kernel void @flat_system_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9180,7 +9180,7 @@ define amdgpu_kernel void @flat_system_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9534,7 +9534,7 @@ define amdgpu_kernel void @flat_system_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9857,7 +9857,7 @@ define amdgpu_kernel void @flat_system_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10176,7 +10176,7 @@ define amdgpu_kernel void @flat_system_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10530,7 +10530,7 @@ define amdgpu_kernel void @flat_system_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10884,7 +10884,7 @@ define amdgpu_kernel void @flat_system_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11238,7 +11238,7 @@ define amdgpu_kernel void @flat_system_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11592,7 +11592,7 @@ define amdgpu_kernel void @flat_system_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11942,7 +11942,7 @@ define amdgpu_kernel void @flat_system_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -12296,7 +12296,7 @@ define amdgpu_kernel void @flat_system_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -12650,7 +12650,7 @@ define amdgpu_kernel void @flat_system_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -13004,7 +13004,7 @@ define amdgpu_kernel void @flat_system_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -13199,7 +13199,7 @@ define amdgpu_kernel void @flat_system_one_as_unordered_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -13392,7 +13392,7 @@ define amdgpu_kernel void @flat_system_one_as_monotonic_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -13614,7 +13614,7 @@ define amdgpu_kernel void @flat_system_one_as_acquire_load(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -13864,7 +13864,7 @@ define amdgpu_kernel void @flat_system_one_as_seq_cst_load(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -14025,7 +14025,7 @@ define amdgpu_kernel void @flat_system_one_as_unordered_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -15788,7 +15788,7 @@ define amdgpu_kernel void @flat_system_one_as_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -16059,7 +16059,7 @@ define amdgpu_kernel void @flat_system_one_as_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -16330,7 +16330,7 @@ define amdgpu_kernel void @flat_system_one_as_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -21168,7 +21168,7 @@ define amdgpu_kernel void @flat_system_one_as_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21498,7 +21498,7 @@ define amdgpu_kernel void @flat_system_one_as_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21830,7 +21830,7 @@ define amdgpu_kernel void @flat_system_one_as_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -22195,7 +22195,7 @@ define amdgpu_kernel void @flat_system_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -22560,7 +22560,7 @@ define amdgpu_kernel void @flat_system_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -22894,7 +22894,7 @@ define amdgpu_kernel void @flat_system_one_as_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -23224,7 +23224,7 @@ define amdgpu_kernel void @flat_system_one_as_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -23589,7 +23589,7 @@ define amdgpu_kernel void @flat_system_one_as_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -23954,7 +23954,7 @@ define amdgpu_kernel void @flat_system_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -24319,7 +24319,7 @@ define amdgpu_kernel void @flat_system_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -24684,7 +24684,7 @@ define amdgpu_kernel void @flat_system_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -25045,7 +25045,7 @@ define amdgpu_kernel void @flat_system_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -25410,7 +25410,7 @@ define amdgpu_kernel void @flat_system_one_as_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -25775,7 +25775,7 @@ define amdgpu_kernel void @flat_system_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -26140,7 +26140,7 @@ define amdgpu_kernel void @flat_system_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
index 41c5927cad4de..d277441d422d9 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
@@ -153,7 +153,7 @@ define amdgpu_kernel void @flat_nontemporal_load_0(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -432,7 +432,7 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v1, s[2:3] scale_offset scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -1018,7 +1018,7 @@ define amdgpu_kernel void @flat_volatile_workgroup_acquire_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -1150,7 +1150,7 @@ define amdgpu_kernel void @flat_volatile_workgroup_release_store(
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
index 041b3f51abc2f..8734e7152e281 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
@@ -197,7 +197,7 @@ define amdgpu_kernel void @flat_wavefront_unordered_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -390,7 +390,7 @@ define amdgpu_kernel void @flat_wavefront_monotonic_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -583,7 +583,7 @@ define amdgpu_kernel void @flat_wavefront_acquire_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -776,7 +776,7 @@ define amdgpu_kernel void @flat_wavefront_seq_cst_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -937,7 +937,7 @@ define amdgpu_kernel void @flat_wavefront_unordered_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -1097,7 +1097,7 @@ define amdgpu_kernel void @flat_wavefront_monotonic_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -1257,7 +1257,7 @@ define amdgpu_kernel void @flat_wavefront_release_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -1417,7 +1417,7 @@ define amdgpu_kernel void @flat_wavefront_seq_cst_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -2423,7 +2423,7 @@ define amdgpu_kernel void @flat_wavefront_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -2630,7 +2630,7 @@ define amdgpu_kernel void @flat_wavefront_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -2837,7 +2837,7 @@ define amdgpu_kernel void @flat_wavefront_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -6931,7 +6931,7 @@ define amdgpu_kernel void @flat_wavefront_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -7232,7 +7232,7 @@ define amdgpu_kernel void @flat_wavefront_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -7533,7 +7533,7 @@ define amdgpu_kernel void @flat_wavefront_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -7834,7 +7834,7 @@ define amdgpu_kernel void @flat_wavefront_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8135,7 +8135,7 @@ define amdgpu_kernel void @flat_wavefront_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8436,7 +8436,7 @@ define amdgpu_kernel void @flat_wavefront_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8737,7 +8737,7 @@ define amdgpu_kernel void @flat_wavefront_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9038,7 +9038,7 @@ define amdgpu_kernel void @flat_wavefront_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9339,7 +9339,7 @@ define amdgpu_kernel void @flat_wavefront_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9640,7 +9640,7 @@ define amdgpu_kernel void @flat_wavefront_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9941,7 +9941,7 @@ define amdgpu_kernel void @flat_wavefront_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10242,7 +10242,7 @@ define amdgpu_kernel void @flat_wavefront_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10543,7 +10543,7 @@ define amdgpu_kernel void @flat_wavefront_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10844,7 +10844,7 @@ define amdgpu_kernel void @flat_wavefront_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11145,7 +11145,7 @@ define amdgpu_kernel void @flat_wavefront_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11340,7 +11340,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_unordered_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -11533,7 +11533,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_monotonic_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -11726,7 +11726,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_acquire_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -11919,7 +11919,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_seq_cst_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -12080,7 +12080,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_unordered_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -12240,7 +12240,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_monotonic_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -12400,7 +12400,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_release_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -12560,7 +12560,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_seq_cst_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -13566,7 +13566,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -13773,7 +13773,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -13980,7 +13980,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -18074,7 +18074,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_monotonic_monotonic_ret_cmpxchg
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -18375,7 +18375,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -18676,7 +18676,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -18977,7 +18977,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -19278,7 +19278,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -19579,7 +19579,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -19880,7 +19880,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -20181,7 +20181,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -20482,7 +20482,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -20783,7 +20783,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21084,7 +21084,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21385,7 +21385,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21686,7 +21686,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_acq_relc_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21987,7 +21987,7 @@ define amdgpu_kernel void @flat_wavefront_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
index 85ecab8128d2f..e7f348e9f7d2f 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
@@ -197,7 +197,7 @@ define amdgpu_kernel void @flat_workgroup_unordered_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -390,7 +390,7 @@ define amdgpu_kernel void @flat_workgroup_monotonic_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -595,7 +595,7 @@ define amdgpu_kernel void @flat_workgroup_acquire_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -821,7 +821,7 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -982,7 +982,7 @@ define amdgpu_kernel void @flat_workgroup_unordered_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -1142,7 +1142,7 @@ define amdgpu_kernel void @flat_workgroup_monotonic_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -1321,7 +1321,7 @@ define amdgpu_kernel void @flat_workgroup_release_store(
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -1500,7 +1500,7 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_store(
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -2635,7 +2635,7 @@ define amdgpu_kernel void @flat_workgroup_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -2875,7 +2875,7 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -3115,7 +3115,7 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -6510,7 +6510,7 @@ define amdgpu_kernel void @flat_workgroup_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -6823,7 +6823,7 @@ define amdgpu_kernel void @flat_workgroup_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -7143,7 +7143,7 @@ define amdgpu_kernel void @flat_workgroup_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -7477,7 +7477,7 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -7811,7 +7811,7 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8126,7 +8126,7 @@ define amdgpu_kernel void @flat_workgroup_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8439,7 +8439,7 @@ define amdgpu_kernel void @flat_workgroup_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -8773,7 +8773,7 @@ define amdgpu_kernel void @flat_workgroup_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9107,7 +9107,7 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9441,7 +9441,7 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -9775,7 +9775,7 @@ define amdgpu_kernel void @flat_workgroup_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10107,7 +10107,7 @@ define amdgpu_kernel void @flat_workgroup_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10441,7 +10441,7 @@ define amdgpu_kernel void @flat_workgroup_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -10775,7 +10775,7 @@ define amdgpu_kernel void @flat_workgroup_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11109,7 +11109,7 @@ define amdgpu_kernel void @flat_workgroup_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -11304,7 +11304,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_unordered_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -11497,7 +11497,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonic_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -11698,7 +11698,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -11913,7 +11913,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_load(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %in, ptr %out) {
entry:
@@ -12074,7 +12074,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_unordered_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -12234,7 +12234,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonic_store(
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -12406,7 +12406,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_store(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -12578,7 +12578,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_store(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
i32 %in, ptr %out) {
entry:
@@ -13661,7 +13661,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -13890,7 +13890,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -14119,7 +14119,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v1, v0, v1, s[0:1] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in) {
entry:
@@ -18488,7 +18488,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonicmonotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -18797,7 +18797,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -19110,7 +19110,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -19433,7 +19433,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -19756,7 +19756,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -20067,7 +20067,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -20376,7 +20376,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -20699,7 +20699,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21022,7 +21022,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21345,7 +21345,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21668,7 +21668,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -21989,7 +21989,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -22312,7 +22312,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -22635,7 +22635,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
@@ -22958,7 +22958,7 @@ define amdgpu_kernel void @flat_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v1, v0, v[2:3], s[0:1] offset:16 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
ptr %out, i32 %in, i32 %old) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
index 8ac3414da7354..c41c8a0b4ce2e 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
@@ -205,7 +205,7 @@ define amdgpu_kernel void @private_agent_unordered_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -405,7 +405,7 @@ define amdgpu_kernel void @private_agent_monotonic_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -606,7 +606,7 @@ define amdgpu_kernel void @private_agent_acquire_load(
; GFX1250-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -809,7 +809,7 @@ define amdgpu_kernel void @private_agent_seq_cst_load(
; GFX1250-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -989,7 +989,7 @@ define amdgpu_kernel void @private_agent_unordered_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -2678,7 +2678,7 @@ define amdgpu_kernel void @private_agent_acquire_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -2918,7 +2918,7 @@ define amdgpu_kernel void @private_agent_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -3158,7 +3158,7 @@ define amdgpu_kernel void @private_agent_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -7567,7 +7567,7 @@ define amdgpu_kernel void @private_agent_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -7870,7 +7870,7 @@ define amdgpu_kernel void @private_agent_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8175,7 +8175,7 @@ define amdgpu_kernel void @private_agent_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8481,7 +8481,7 @@ define amdgpu_kernel void @private_agent_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8787,7 +8787,7 @@ define amdgpu_kernel void @private_agent_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9090,7 +9090,7 @@ define amdgpu_kernel void @private_agent_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9393,7 +9393,7 @@ define amdgpu_kernel void @private_agent_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9699,7 +9699,7 @@ define amdgpu_kernel void @private_agent_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10005,7 +10005,7 @@ define amdgpu_kernel void @private_agent_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10311,7 +10311,7 @@ define amdgpu_kernel void @private_agent_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10617,7 +10617,7 @@ define amdgpu_kernel void @private_agent_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10923,7 +10923,7 @@ define amdgpu_kernel void @private_agent_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11229,7 +11229,7 @@ define amdgpu_kernel void @private_agent_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11535,7 +11535,7 @@ define amdgpu_kernel void @private_agent_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11841,7 +11841,7 @@ define amdgpu_kernel void @private_agent_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -12043,7 +12043,7 @@ define amdgpu_kernel void @private_agent_one_as_unordered_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12243,7 +12243,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12445,7 +12445,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_load(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12649,7 +12649,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_load(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12829,7 +12829,7 @@ define amdgpu_kernel void @private_agent_one_as_unordered_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -14519,7 +14519,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -14760,7 +14760,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -15001,7 +15001,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -19410,7 +19410,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -19714,7 +19714,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20021,7 +20021,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20328,7 +20328,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20632,7 +20632,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20936,7 +20936,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21243,7 +21243,7 @@ define amdgpu_kernel void @private_agent_one_as_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21550,7 +21550,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21857,7 +21857,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22164,7 +22164,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22471,7 +22471,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22778,7 +22778,7 @@ define amdgpu_kernel void @private_agent_one_as_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -23085,7 +23085,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -23392,7 +23392,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_DEV
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
index f5ba70e454823..17ed7b7776aa9 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
@@ -205,7 +205,7 @@ define amdgpu_kernel void @private_singlethread_unordered_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -405,7 +405,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -605,7 +605,7 @@ define amdgpu_kernel void @private_singlethread_acquire_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -805,7 +805,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -985,7 +985,7 @@ define amdgpu_kernel void @private_singlethread_unordered_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -1164,7 +1164,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -1343,7 +1343,7 @@ define amdgpu_kernel void @private_singlethread_release_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -1522,7 +1522,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -2652,7 +2652,7 @@ define amdgpu_kernel void @private_singlethread_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -2888,7 +2888,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -3124,7 +3124,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -7474,7 +7474,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -7776,7 +7776,7 @@ define amdgpu_kernel void @private_singlethread_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8078,7 +8078,7 @@ define amdgpu_kernel void @private_singlethread_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8380,7 +8380,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8682,7 +8682,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8984,7 +8984,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9286,7 +9286,7 @@ define amdgpu_kernel void @private_singlethread_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9588,7 +9588,7 @@ define amdgpu_kernel void @private_singlethread_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9890,7 +9890,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10192,7 +10192,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10494,7 +10494,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10796,7 +10796,7 @@ define amdgpu_kernel void @private_singlethread_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11098,7 +11098,7 @@ define amdgpu_kernel void @private_singlethread_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11400,7 +11400,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11702,7 +11702,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11904,7 +11904,7 @@ define amdgpu_kernel void @private_singlethread_one_as_unordered_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12104,7 +12104,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12304,7 +12304,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12504,7 +12504,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12684,7 +12684,7 @@ define amdgpu_kernel void @private_singlethread_one_as_unordered_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -12863,7 +12863,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -13042,7 +13042,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -13221,7 +13221,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -14351,7 +14351,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -14587,7 +14587,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -14823,7 +14823,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -19173,7 +19173,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_monotonic_ret_c
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -19475,7 +19475,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_monotonic_ret_cmp
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -19777,7 +19777,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_monotonic_ret_cmp
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20079,7 +20079,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_monotonic_ret_cmp
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20381,7 +20381,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_monotonic_ret_cmp
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20683,7 +20683,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_acquire_ret_cmp
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20985,7 +20985,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_acquire_ret_cmpxc
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21287,7 +21287,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_acquire_ret_cmpxc
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21589,7 +21589,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_acquire_ret_cmpxc
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21891,7 +21891,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_acquire_ret_cmpxc
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22193,7 +22193,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_seq_cst_ret_cmp
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22495,7 +22495,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_seq_cst_ret_cmpxc
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22797,7 +22797,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_seq_cst_ret_cmpxc
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -23099,7 +23099,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_seq_cst_ret_cmpxc
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -23401,7 +23401,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_seq_cst_ret_cmpxc
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
index 1e2153f76bc03..3702f983dbbb4 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
@@ -205,7 +205,7 @@ define amdgpu_kernel void @private_system_unordered_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -405,7 +405,7 @@ define amdgpu_kernel void @private_system_monotonic_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -606,7 +606,7 @@ define amdgpu_kernel void @private_system_acquire_load(
; GFX1250-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -809,7 +809,7 @@ define amdgpu_kernel void @private_system_seq_cst_load(
; GFX1250-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -989,7 +989,7 @@ define amdgpu_kernel void @private_system_unordered_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -2678,7 +2678,7 @@ define amdgpu_kernel void @private_system_acquire_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -2918,7 +2918,7 @@ define amdgpu_kernel void @private_system_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -3158,7 +3158,7 @@ define amdgpu_kernel void @private_system_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -6467,7 +6467,7 @@ define amdgpu_kernel void @private_system_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -6770,7 +6770,7 @@ define amdgpu_kernel void @private_system_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -7076,7 +7076,7 @@ define amdgpu_kernel void @private_system_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -7382,7 +7382,7 @@ define amdgpu_kernel void @private_system_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -7685,7 +7685,7 @@ define amdgpu_kernel void @private_system_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -7988,7 +7988,7 @@ define amdgpu_kernel void @private_system_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8294,7 +8294,7 @@ define amdgpu_kernel void @private_system_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8600,7 +8600,7 @@ define amdgpu_kernel void @private_system_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8906,7 +8906,7 @@ define amdgpu_kernel void @private_system_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9212,7 +9212,7 @@ define amdgpu_kernel void @private_system_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9518,7 +9518,7 @@ define amdgpu_kernel void @private_system_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9824,7 +9824,7 @@ define amdgpu_kernel void @private_system_relese_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10130,7 +10130,7 @@ define amdgpu_kernel void @private_system_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10436,7 +10436,7 @@ define amdgpu_kernel void @private_system_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10638,7 +10638,7 @@ define amdgpu_kernel void @private_system_one_as_unordered_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -10838,7 +10838,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -11040,7 +11040,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_load(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -11244,7 +11244,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_load(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -11424,7 +11424,7 @@ define amdgpu_kernel void @private_system_one_as_unordered_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -13114,7 +13114,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -13355,7 +13355,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -13596,7 +13596,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -18005,7 +18005,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_monotonic_ret_cmpxchg
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -18309,7 +18309,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -18614,7 +18614,7 @@ define amdgpu_kernel void @private_system_one_as_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -18921,7 +18921,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -19228,7 +19228,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -19532,7 +19532,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -19836,7 +19836,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20143,7 +20143,7 @@ define amdgpu_kernel void @private_system_one_as_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20450,7 +20450,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20757,7 +20757,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21064,7 +21064,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21371,7 +21371,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21678,7 +21678,7 @@ define amdgpu_kernel void @private_system_one_as_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21985,7 +21985,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22292,7 +22292,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: global_inv scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
index 28d9d5dacd9e3..b868d8a86de4b 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
@@ -205,7 +205,7 @@ define amdgpu_kernel void @private_wavefront_unordered_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -405,7 +405,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -605,7 +605,7 @@ define amdgpu_kernel void @private_wavefront_acquire_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -805,7 +805,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -985,7 +985,7 @@ define amdgpu_kernel void @private_wavefront_unordered_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -1164,7 +1164,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -1343,7 +1343,7 @@ define amdgpu_kernel void @private_wavefront_release_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -1522,7 +1522,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -2652,7 +2652,7 @@ define amdgpu_kernel void @private_wavefront_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -2888,7 +2888,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -3124,7 +3124,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -7474,7 +7474,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -7776,7 +7776,7 @@ define amdgpu_kernel void @private_wavefront_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8078,7 +8078,7 @@ define amdgpu_kernel void @private_wavefront_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8380,7 +8380,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8682,7 +8682,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8984,7 +8984,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9286,7 +9286,7 @@ define amdgpu_kernel void @private_wavefront_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9588,7 +9588,7 @@ define amdgpu_kernel void @private_wavefront_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9890,7 +9890,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10192,7 +10192,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10494,7 +10494,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10796,7 +10796,7 @@ define amdgpu_kernel void @private_wavefront_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11098,7 +11098,7 @@ define amdgpu_kernel void @private_wavefront_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11400,7 +11400,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11702,7 +11702,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11904,7 +11904,7 @@ define amdgpu_kernel void @private_wavefront_one_as_unordered_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12104,7 +12104,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12304,7 +12304,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12504,7 +12504,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12684,7 +12684,7 @@ define amdgpu_kernel void @private_wavefront_one_as_unordered_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -12863,7 +12863,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -13042,7 +13042,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -13221,7 +13221,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -14351,7 +14351,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -14587,7 +14587,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -14823,7 +14823,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -19173,7 +19173,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_monotonic_ret_cmpx
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -19475,7 +19475,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -19777,7 +19777,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20079,7 +20079,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20381,7 +20381,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20683,7 +20683,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_acquire_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20985,7 +20985,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21287,7 +21287,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21589,7 +21589,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21891,7 +21891,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22193,7 +22193,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_seq_cst_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22495,7 +22495,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22797,7 +22797,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -23099,7 +23099,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -23401,7 +23401,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
index 01b2f6835cf7b..08388d1b95aef 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
@@ -205,7 +205,7 @@ define amdgpu_kernel void @private_workgroup_unordered_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -405,7 +405,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -605,7 +605,7 @@ define amdgpu_kernel void @private_workgroup_acquire_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -807,7 +807,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_load(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -987,7 +987,7 @@ define amdgpu_kernel void @private_workgroup_unordered_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -1166,7 +1166,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -1347,7 +1347,7 @@ define amdgpu_kernel void @private_workgroup_release_store(
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -1528,7 +1528,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_store(
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -2667,7 +2667,7 @@ define amdgpu_kernel void @private_workgroup_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -2905,7 +2905,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -3143,7 +3143,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -7528,7 +7528,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -7830,7 +7830,7 @@ define amdgpu_kernel void @private_workgroup_acquire_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8134,7 +8134,7 @@ define amdgpu_kernel void @private_workgroup_release_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8438,7 +8438,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -8742,7 +8742,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_monotonic_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9044,7 +9044,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9346,7 +9346,7 @@ define amdgpu_kernel void @private_workgroup_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9650,7 +9650,7 @@ define amdgpu_kernel void @private_workgroup_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -9954,7 +9954,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10258,7 +10258,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10562,7 +10562,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -10866,7 +10866,7 @@ define amdgpu_kernel void @private_workgroup_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11170,7 +11170,7 @@ define amdgpu_kernel void @private_workgroup_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11474,7 +11474,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11778,7 +11778,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -11980,7 +11980,7 @@ define amdgpu_kernel void @private_workgroup_one_as_unordered_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12180,7 +12180,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12380,7 +12380,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_load(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12582,7 +12582,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_load(
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: flat_load_b32 v0, v[0:1]
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %in, ptr addrspace(5) %out) {
entry:
@@ -12762,7 +12762,7 @@ define amdgpu_kernel void @private_workgroup_one_as_unordered_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -12941,7 +12941,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_store(
; GFX1250-NEXT: v_mov_b32_e32 v1, v2
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -13122,7 +13122,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_store(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -13303,7 +13303,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_store(
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SE
+; GFX1250-NEXT: flat_store_b32 v[0:1], v2
; GFX1250-NEXT: s_endpgm
i32 %in, ptr addrspace(5) %out) {
entry:
@@ -14442,7 +14442,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -14680,7 +14680,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -14918,7 +14918,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_ret_atomicrmw(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in) {
entry:
@@ -19303,7 +19303,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_monotonic_ret_cmpx
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -19605,7 +19605,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -19909,7 +19909,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20213,7 +20213,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20517,7 +20517,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_monotonic_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -20819,7 +20819,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_acquire_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21121,7 +21121,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21425,7 +21425,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -21729,7 +21729,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22033,7 +22033,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22337,7 +22337,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_seq_cst_ret_cmpxch
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22641,7 +22641,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -22945,7 +22945,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -23249,7 +23249,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
@@ -23553,7 +23553,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SE
+; GFX1250-NEXT: scratch_store_b32 off, v0, s0
; GFX1250-NEXT: s_endpgm
ptr addrspace(5) %out, i32 %in, i32 %old) {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
index f78168ba29ef1..9f27e1ffd9130 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
@@ -3435,7 +3435,7 @@ define amdgpu_kernel void @fadd_fadd_fsub_0(<2 x float> %arg) {
; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-SDAG-NEXT: s_add_f32 s1, s1, 0
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_endpgm
;
; GFX1250-GISEL-LABEL: fadd_fadd_fsub_0:
@@ -3450,7 +3450,7 @@ define amdgpu_kernel void @fadd_fadd_fsub_0(<2 x float> %arg) {
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], 0
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v3, v0
-; GFX1250-GISEL-NEXT: flat_store_b64 v[0:1], v[2:3] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: flat_store_b64 v[0:1], v[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
bb:
%i12 = fadd <2 x float> zeroinitializer, %arg
diff --git a/llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll b/llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
index 725d57d852966..e0bdd77bd18e2 100644
--- a/llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
+++ b/llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
@@ -285,7 +285,7 @@ define amdgpu_ps void @flat_store_b32_idxprom(ptr align 4 inreg %p, i32 %idx) {
; GCN-LABEL: flat_store_b32_idxprom:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: v_mov_b32_e32 v1, 1.0
-; GCN-NEXT: flat_store_b32 v0, v1, s[0:1] scale_offset scope:SCOPE_SE
+; GCN-NEXT: flat_store_b32 v0, v1, s[0:1] scale_offset
; GCN-NEXT: s_endpgm
entry:
%idxprom = sext i32 %idx to i64
@@ -298,7 +298,7 @@ define amdgpu_ps void @flat_store_b16_idxprom(ptr align 2 inreg %p, i32 %idx) {
; GCN-LABEL: flat_store_b16_idxprom:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: v_mov_b32_e32 v1, 1
-; GCN-NEXT: flat_store_b16 v0, v1, s[0:1] scale_offset scope:SCOPE_SE
+; GCN-NEXT: flat_store_b16 v0, v1, s[0:1] scale_offset
; GCN-NEXT: s_endpgm
entry:
%idxprom = sext i32 %idx to i64
@@ -311,7 +311,7 @@ define amdgpu_ps void @flat_store_b64_idxprom(ptr align 4 inreg %p, i32 %idx) {
; GCN-LABEL: flat_store_b64_idxprom:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: v_mov_b64_e32 v[2:3], 1.0
-; GCN-NEXT: flat_store_b64 v0, v[2:3], s[0:1] scale_offset scope:SCOPE_SE
+; GCN-NEXT: flat_store_b64 v0, v[2:3], s[0:1] scale_offset
; GCN-NEXT: s_endpgm
entry:
%idxprom = sext i32 %idx to i64
@@ -372,7 +372,7 @@ define amdgpu_ps <2 x float> @flat_atomicrmw_b64_rtn_idxprom(ptr align 8 inreg %
; SDAG-NEXT: scratch_load_b64 v[0:1], v4, off
; SDAG-NEXT: s_wait_loadcnt 0x0
; SDAG-NEXT: v_add_nc_u64_e32 v[2:3], 1, v[0:1]
-; SDAG-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; SDAG-NEXT: scratch_store_b64 v4, v[2:3], off
; SDAG-NEXT: s_wait_xcnt 0x0
; SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; SDAG-NEXT: s_branch .LBB21_5
@@ -421,7 +421,7 @@ define amdgpu_ps <2 x float> @flat_atomicrmw_b64_rtn_idxprom(ptr align 8 inreg %
; GISEL-NEXT: scratch_load_b64 v[0:1], v4, off
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: v_add_nc_u64_e32 v[2:3], 1, v[0:1]
-; GISEL-NEXT: scratch_store_b64 v4, v[2:3], off scope:SCOPE_SE
+; GISEL-NEXT: scratch_store_b64 v4, v[2:3], off
; GISEL-NEXT: s_wait_xcnt 0x0
; GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GISEL-NEXT: s_branch .LBB21_5
diff --git a/llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll b/llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
index e5db4c6a934c2..ba4fedf5bb009 100644
--- a/llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
@@ -284,7 +284,7 @@ define amdgpu_ps void @scratch_store_b32_idxprom(ptr addrspace(5) align 4 inreg
; GCN-LABEL: scratch_store_b32_idxprom:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: v_mov_b32_e32 v1, 1.0
-; GCN-NEXT: scratch_store_b32 v0, v1, s0 scale_offset scope:SCOPE_SE
+; GCN-NEXT: scratch_store_b32 v0, v1, s0 scale_offset
; GCN-NEXT: s_endpgm
entry:
%idxprom = zext i32 %idx to i64
@@ -297,7 +297,7 @@ define amdgpu_ps void @scratch_store_b16_idxprom(ptr addrspace(5) align 2 inreg
; GCN-LABEL: scratch_store_b16_idxprom:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: v_mov_b32_e32 v1, 1
-; GCN-NEXT: scratch_store_b16 v0, v1, s0 scale_offset scope:SCOPE_SE
+; GCN-NEXT: scratch_store_b16 v0, v1, s0 scale_offset
; GCN-NEXT: s_endpgm
entry:
%idxprom = zext i32 %idx to i64
@@ -310,7 +310,7 @@ define amdgpu_ps void @scratch_store_b64_idxprom(ptr addrspace(5) align 4 inreg
; GCN-LABEL: scratch_store_b64_idxprom:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: v_mov_b64_e32 v[2:3], 1.0
-; GCN-NEXT: scratch_store_b64 v0, v[2:3], s0 scale_offset scope:SCOPE_SE
+; GCN-NEXT: scratch_store_b64 v0, v[2:3], s0 scale_offset
; GCN-NEXT: s_endpgm
entry:
%idxprom = zext i32 %idx to i64
diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
index 7a985456379b8..b17050178c306 100644
--- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
@@ -114,8 +114,8 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) {
; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1
; GFX1250-DAGISEL-NEXT: s_clause 0x1
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; GFX1250-DAGISEL-NEXT: v_dual_cndmask_b32 v0, 5, v0 :: v_dual_cndmask_b32 v1, 3, v1
@@ -239,8 +239,8 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 %
; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1
; GFX1250-DAGISEL-NEXT: s_clause 0x1
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; GFX1250-DAGISEL-NEXT: v_cndmask_b32_e32 v1, 17, v1, vcc_lo
@@ -338,7 +338,7 @@ define amdgpu_gfx_whole_wave i32 @unused_active(i1 %active, i32 %a, i32 %b) {
; GFX1250-DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 scope:SCOPE_SE ; 4-byte Folded Spill
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 ; 4-byte Folded Spill
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; GFX1250-DAGISEL-NEXT: v_mov_b32_e32 v0, 14
@@ -518,13 +518,13 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) {
; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1
; GFX1250-DAGISEL-NEXT: s_clause 0x3
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 offset:4 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:8 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:16 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 offset:4
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:8
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:16
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s32 offset:12 scope:SCOPE_SE ; 4-byte Folded Spill
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: ;;#ASMSTART
; GFX1250-DAGISEL-NEXT: ; clobber CSR
@@ -636,7 +636,7 @@ define amdgpu_gfx_whole_wave void @csr_vgpr_only(i1 %active, i32 %a, i32 %b) {
; GFX1250-DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-DAGISEL-NEXT: s_or_saveexec_b32 s0, -1
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s32 scope:SCOPE_SE ; 4-byte Folded Spill
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: ;;#ASMSTART
; GFX1250-DAGISEL-NEXT: ; clobber CSR VGPR
@@ -748,7 +748,7 @@ define amdgpu_gfx_whole_wave void @sgpr_spill_only(i1 %active, i32 %a, i32 %b) {
; GFX1250-DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 scope:SCOPE_SE ; 4-byte Folded Spill
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 ; 4-byte Folded Spill
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v0, s68, 0
@@ -894,8 +894,8 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) {
; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1
; GFX1250-DAGISEL-NEXT: s_clause 0x1
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; GFX1250-DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -1059,10 +1059,10 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) {
; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1
; GFX1250-DAGISEL-NEXT: s_clause 0x3
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; GFX1250-DAGISEL-NEXT: v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 5, v0
@@ -1252,21 +1252,21 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i
; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1
; GFX1250-DAGISEL-NEXT: s_clause 0x5
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; GFX1250-DAGISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s9
; GFX1250-DAGISEL-NEXT: v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, s6
; GFX1250-DAGISEL-NEXT: v_dual_mov_b32 v2, s7 :: v_dual_mov_b32 v3, s8
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s10 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s10
; GFX1250-DAGISEL-NEXT: s_clause 0x1
-; GFX1250-DAGISEL-NEXT: scratch_store_b128 off, v[0:3], s11 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s11 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b128 off, v[0:3], s11
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s11
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, s0, -1
; GFX1250-DAGISEL-NEXT: s_clause 0x5
@@ -2645,939 +2645,939 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GFX1250-DAGISEL-NEXT: s_mov_b32 s33, s32
; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s4, -1
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:164 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:168 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:172 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:176 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:180 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:184 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:188 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:192 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:196 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:200 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:204 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:208 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:212 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:216 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:220 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:224 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:228 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:232 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:236 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:240 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:244 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:248 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:252 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:164
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:168
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:172
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:176
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:180
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:184
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:188
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:192
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:196
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:200
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:204
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:208
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:212
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:216
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:220
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:224
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:228
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:232
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:236
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:240
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:244
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:248
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:252
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:256 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:260 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:264 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:268 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:272 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:276 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:280 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:284 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:288 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:292 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:296 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:300 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:304 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:308 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:312 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:316 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:320 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:324 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:328 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:332 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:336 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:340 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:344 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:348 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:352 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:356 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:360 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:364 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:368 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:372 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:376 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:380 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:384 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:388 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:392 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:396 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:400 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:404 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:408 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:412 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:416 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:420 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:424 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:428 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:432 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:436 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:440 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:444 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:448 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:452 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:456 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:460 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:464 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:468 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:472 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:476 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:480 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:484 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:488 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:492 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:496 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:500 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:504 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:256
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:260
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:264
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:268
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:272
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:276
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:280
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:284
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:288
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:292
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:296
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:300
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:304
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:308
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:312
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:316
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:320
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:324
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:328
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:332
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:336
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:340
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:344
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:348
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:352
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:356
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:360
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:364
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:368
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:372
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:376
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:380
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:384
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:388
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:392
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:396
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:400
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:404
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:408
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:412
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:416
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:420
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:424
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:428
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:432
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:436
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:440
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:444
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:448
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:452
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:456
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:460
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:464
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:468
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:472
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:476
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:480
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:484
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:488
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:492
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:496
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:500
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:504
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:508 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:512 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:516 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:520 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:524 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:528 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:532 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:536 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:540 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:544 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:548 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:552 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:556 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:560 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:564 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:568 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:572 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:576 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:508
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:512
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:516
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:520
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:524
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:528
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:532
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:536
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:540
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:544
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:548
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:552
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:556
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:560
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:564
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:568
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:572
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:576
; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 4 ; msbs: dst=0 src0=0 src1=1 src2=0
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s33 offset:580 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s33 offset:584 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s33 offset:588 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s33 offset:592 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s33 offset:596 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s33 offset:600 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s33 offset:604 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s33 offset:608 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s33 offset:612 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s33 offset:616 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s33 offset:620 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s33 offset:624 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s33 offset:628 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s33 offset:632 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s33 offset:636 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s33 offset:640 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s33 offset:644 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s33 offset:648 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s33 offset:652 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s33 offset:656 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s33 offset:660 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s33 offset:664 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s33 offset:668 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s33 offset:672 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s33 offset:676 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s33 offset:680 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s33 offset:684 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s33 offset:688 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s33 offset:692 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s33 offset:696 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s33 offset:700 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s33 offset:704 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s33 offset:708 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s33 offset:712 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s33 offset:716 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s33 offset:720 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s33 offset:724 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s33 offset:728 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s33 offset:732 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s33 offset:736 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s33 offset:740 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s33 offset:744 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s33 offset:748 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s33 offset:752 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s33 offset:756 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s33 offset:580
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s33 offset:584
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s33 offset:588
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s33 offset:592
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s33 offset:596
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s33 offset:600
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s33 offset:604
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s33 offset:608
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s33 offset:612
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s33 offset:616
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s33 offset:620
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s33 offset:624
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s33 offset:628
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s33 offset:632
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s33 offset:636
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s33 offset:640
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s33 offset:644
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s33 offset:648
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s33 offset:652
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s33 offset:656
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s33 offset:660
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s33 offset:664
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s33 offset:668
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s33 offset:672
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s33 offset:676
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s33 offset:680
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s33 offset:684
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s33 offset:688
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s33 offset:692
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s33 offset:696
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s33 offset:700
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s33 offset:704
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s33 offset:708
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s33 offset:712
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s33 offset:716
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s33 offset:720
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s33 offset:724
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s33 offset:728
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s33 offset:732
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s33 offset:736
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s33 offset:740
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s33 offset:744
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s33 offset:748
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s33 offset:752
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s33 offset:756
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s33 offset:760 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s33 offset:764 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s33 offset:768 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s33 offset:772 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s33 offset:776 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s33 offset:780 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s33 offset:784 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s33 offset:788 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s33 offset:792 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s33 offset:796 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s33 offset:800 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s33 offset:804 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s33 offset:808 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s33 offset:812 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s33 offset:816 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s33 offset:820 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s33 offset:824 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s33 offset:828 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s33 offset:832 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s33 offset:836 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s33 offset:840 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s33 offset:844 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s33 offset:848 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s33 offset:852 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s33 offset:856 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s33 offset:860 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s33 offset:864 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s33 offset:868 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s33 offset:872 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s33 offset:876 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s33 offset:880 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s33 offset:884 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s33 offset:888 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s33 offset:892 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s33 offset:896 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s33 offset:900 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s33 offset:904 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s33 offset:908 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s33 offset:912 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s33 offset:916 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s33 offset:920 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s33 offset:924 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s33 offset:928 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s33 offset:932 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s33 offset:936 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s33 offset:940 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s33 offset:944 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s33 offset:948 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s33 offset:952 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s33 offset:956 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s33 offset:960 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s33 offset:964 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s33 offset:968 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s33 offset:972 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s33 offset:976 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s33 offset:980 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s33 offset:984 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s33 offset:988 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s33 offset:992 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s33 offset:996 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s33 offset:1000 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s33 offset:1004 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s33 offset:1008 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s33 offset:760
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s33 offset:764
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s33 offset:768
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s33 offset:772
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s33 offset:776
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s33 offset:780
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s33 offset:784
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s33 offset:788
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s33 offset:792
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s33 offset:796
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s33 offset:800
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s33 offset:804
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s33 offset:808
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s33 offset:812
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s33 offset:816
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s33 offset:820
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s33 offset:824
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s33 offset:828
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s33 offset:832
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s33 offset:836
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s33 offset:840
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s33 offset:844
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s33 offset:848
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s33 offset:852
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s33 offset:856
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s33 offset:860
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s33 offset:864
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s33 offset:868
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s33 offset:872
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s33 offset:876
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s33 offset:880
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s33 offset:884
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s33 offset:888
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s33 offset:892
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s33 offset:896
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s33 offset:900
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s33 offset:904
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s33 offset:908
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s33 offset:912
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s33 offset:916
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s33 offset:920
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s33 offset:924
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s33 offset:928
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s33 offset:932
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s33 offset:936
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s33 offset:940
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s33 offset:944
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s33 offset:948
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s33 offset:952
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s33 offset:956
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s33 offset:960
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s33 offset:964
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s33 offset:968
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s33 offset:972
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s33 offset:976
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s33 offset:980
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s33 offset:984
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s33 offset:988
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s33 offset:992
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s33 offset:996
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s33 offset:1000
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s33 offset:1004
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s33 offset:1008
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s33 offset:1012 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s33 offset:1016 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s33 offset:1020 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s33 offset:1024 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s33 offset:1028 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s33 offset:1032 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s33 offset:1036 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s33 offset:1040 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s33 offset:1044 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s33 offset:1048 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s33 offset:1052 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s33 offset:1056 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s33 offset:1060 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s33 offset:1064 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s33 offset:1068 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s33 offset:1072 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s33 offset:1076 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s33 offset:1080 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s33 offset:1084 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s33 offset:1088 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s33 offset:1092 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s33 offset:1096 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s33 offset:1100 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s33 offset:1104 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s33 offset:1108 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s33 offset:1112 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s33 offset:1116 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s33 offset:1120 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s33 offset:1124 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s33 offset:1128 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s33 offset:1132 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s33 offset:1136 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s33 offset:1140 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s33 offset:1144 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s33 offset:1148 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s33 offset:1152 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s33 offset:1156 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s33 offset:1160 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s33 offset:1164 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s33 offset:1168 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s33 offset:1172 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s33 offset:1176 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s33 offset:1180 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s33 offset:1184 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s33 offset:1188 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s33 offset:1192 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s33 offset:1196 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s33 offset:1200 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s33 offset:1204 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s33 offset:1208 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s33 offset:1212 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s33 offset:1216 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s33 offset:1220 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s33 offset:1224 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s33 offset:1228 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s33 offset:1232 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s33 offset:1236 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s33 offset:1240 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s33 offset:1244 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s33 offset:1248 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s33 offset:1252 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s33 offset:1256 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s33 offset:1260 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s33 offset:1012
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s33 offset:1016
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s33 offset:1020
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s33 offset:1024
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s33 offset:1028
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s33 offset:1032
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s33 offset:1036
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s33 offset:1040
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s33 offset:1044
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s33 offset:1048
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s33 offset:1052
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s33 offset:1056
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s33 offset:1060
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s33 offset:1064
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s33 offset:1068
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s33 offset:1072
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s33 offset:1076
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s33 offset:1080
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s33 offset:1084
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s33 offset:1088
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s33 offset:1092
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s33 offset:1096
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s33 offset:1100
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s33 offset:1104
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s33 offset:1108
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s33 offset:1112
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s33 offset:1116
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s33 offset:1120
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s33 offset:1124
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s33 offset:1128
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s33 offset:1132
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s33 offset:1136
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s33 offset:1140
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s33 offset:1144
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s33 offset:1148
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s33 offset:1152
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s33 offset:1156
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s33 offset:1160
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s33 offset:1164
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s33 offset:1168
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s33 offset:1172
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s33 offset:1176
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s33 offset:1180
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s33 offset:1184
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s33 offset:1188
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s33 offset:1192
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s33 offset:1196
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s33 offset:1200
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s33 offset:1204
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s33 offset:1208
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s33 offset:1212
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s33 offset:1216
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s33 offset:1220
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s33 offset:1224
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s33 offset:1228
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s33 offset:1232
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s33 offset:1236
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s33 offset:1240
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s33 offset:1244
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s33 offset:1248
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s33 offset:1252
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s33 offset:1256
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s33 offset:1260
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s33 offset:1264 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s33 offset:1268 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s33 offset:1272 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s33 offset:1276 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s33 offset:1280 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s33 offset:1284 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s33 offset:1288 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s33 offset:1292 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s33 offset:1296 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s33 offset:1300 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s33 offset:1304 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s33 offset:1308 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s33 offset:1312 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s33 offset:1316 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s33 offset:1320 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s33 offset:1324 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s33 offset:1328 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s33 offset:1332 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s33 offset:1336 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s33 offset:1340 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s33 offset:1344 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s33 offset:1348 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s33 offset:1352 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s33 offset:1356 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s33 offset:1360 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s33 offset:1364 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s33 offset:1368 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s33 offset:1372 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s33 offset:1376 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s33 offset:1380 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s33 offset:1384 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s33 offset:1388 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s33 offset:1392 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s33 offset:1396 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s33 offset:1400 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s33 offset:1404 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s33 offset:1408 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s33 offset:1412 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s33 offset:1416 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s33 offset:1420 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s33 offset:1424 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s33 offset:1428 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s33 offset:1432 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s33 offset:1436 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s33 offset:1440 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s33 offset:1444 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s33 offset:1448 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s33 offset:1452 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s33 offset:1456 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s33 offset:1460 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s33 offset:1464 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s33 offset:1468 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s33 offset:1472 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s33 offset:1476 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s33 offset:1480 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s33 offset:1484 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s33 offset:1488 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s33 offset:1492 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s33 offset:1496 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s33 offset:1500 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s33 offset:1504 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s33 offset:1508 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s33 offset:1512 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s33 offset:1264
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s33 offset:1268
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s33 offset:1272
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s33 offset:1276
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s33 offset:1280
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s33 offset:1284
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s33 offset:1288
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s33 offset:1292
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s33 offset:1296
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s33 offset:1300
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s33 offset:1304
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s33 offset:1308
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s33 offset:1312
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s33 offset:1316
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s33 offset:1320
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s33 offset:1324
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s33 offset:1328
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s33 offset:1332
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s33 offset:1336
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s33 offset:1340
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s33 offset:1344
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s33 offset:1348
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s33 offset:1352
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s33 offset:1356
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s33 offset:1360
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s33 offset:1364
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s33 offset:1368
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s33 offset:1372
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s33 offset:1376
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s33 offset:1380
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s33 offset:1384
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s33 offset:1388
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s33 offset:1392
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s33 offset:1396
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s33 offset:1400
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s33 offset:1404
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s33 offset:1408
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s33 offset:1412
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s33 offset:1416
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s33 offset:1420
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s33 offset:1424
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s33 offset:1428
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s33 offset:1432
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s33 offset:1436
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s33 offset:1440
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s33 offset:1444
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s33 offset:1448
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s33 offset:1452
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s33 offset:1456
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s33 offset:1460
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s33 offset:1464
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s33 offset:1468
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s33 offset:1472
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s33 offset:1476
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s33 offset:1480
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s33 offset:1484
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s33 offset:1488
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s33 offset:1492
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s33 offset:1496
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s33 offset:1500
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s33 offset:1504
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s33 offset:1508
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s33 offset:1512
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s33 offset:1516 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s33 offset:1520 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s33 offset:1524 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s33 offset:1528 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s33 offset:1532 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s33 offset:1536 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s33 offset:1540 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s33 offset:1544 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s33 offset:1548 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s33 offset:1552 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s33 offset:1556 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s33 offset:1560 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s33 offset:1564 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s33 offset:1568 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s33 offset:1572 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s33 offset:1576 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s33 offset:1580 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s33 offset:1584 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s33 offset:1588 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s33 offset:1592 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s33 offset:1596 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s33 offset:1600 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s33 offset:1516
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s33 offset:1520
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s33 offset:1524
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s33 offset:1528
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s33 offset:1532
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s33 offset:1536
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s33 offset:1540
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s33 offset:1544
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s33 offset:1548
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s33 offset:1552
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s33 offset:1556
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s33 offset:1560
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s33 offset:1564
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s33 offset:1568
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s33 offset:1572
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s33 offset:1576
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s33 offset:1580
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s33 offset:1584
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s33 offset:1588
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s33 offset:1592
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s33 offset:1596
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s33 offset:1600
; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 8 ; msbs: dst=0 src0=0 src1=2 src2=0
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s33 offset:1604 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s33 offset:1608 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s33 offset:1612 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s33 offset:1616 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s33 offset:1620 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s33 offset:1624 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s33 offset:1628 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s33 offset:1632 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s33 offset:1636 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s33 offset:1640 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s33 offset:1644 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s33 offset:1648 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s33 offset:1652 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s33 offset:1656 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s33 offset:1660 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s33 offset:1664 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s33 offset:1668 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s33 offset:1672 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s33 offset:1676 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s33 offset:1680 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s33 offset:1684 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s33 offset:1688 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s33 offset:1692 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s33 offset:1696 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s33 offset:1700 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s33 offset:1704 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s33 offset:1708 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s33 offset:1712 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s33 offset:1716 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s33 offset:1720 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s33 offset:1724 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s33 offset:1728 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s33 offset:1732 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s33 offset:1736 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s33 offset:1740 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s33 offset:1744 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s33 offset:1748 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s33 offset:1752 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s33 offset:1756 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s33 offset:1760 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s33 offset:1764 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s33 offset:1604
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s33 offset:1608
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s33 offset:1612
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s33 offset:1616
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s33 offset:1620
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s33 offset:1624
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s33 offset:1628
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s33 offset:1632
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s33 offset:1636
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s33 offset:1640
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s33 offset:1644
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s33 offset:1648
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s33 offset:1652
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s33 offset:1656
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s33 offset:1660
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s33 offset:1664
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s33 offset:1668
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s33 offset:1672
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s33 offset:1676
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s33 offset:1680
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s33 offset:1684
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s33 offset:1688
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s33 offset:1692
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s33 offset:1696
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s33 offset:1700
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s33 offset:1704
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s33 offset:1708
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s33 offset:1712
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s33 offset:1716
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s33 offset:1720
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s33 offset:1724
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s33 offset:1728
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s33 offset:1732
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s33 offset:1736
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s33 offset:1740
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s33 offset:1744
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s33 offset:1748
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s33 offset:1752
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s33 offset:1756
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s33 offset:1760
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s33 offset:1764
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s33 offset:1768 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s33 offset:1772 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s33 offset:1776 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s33 offset:1780 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s33 offset:1784 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s33 offset:1788 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s33 offset:1792 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s33 offset:1796 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s33 offset:1800 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s33 offset:1804 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s33 offset:1808 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s33 offset:1812 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s33 offset:1816 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s33 offset:1820 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s33 offset:1824 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s33 offset:1828 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s33 offset:1832 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s33 offset:1836 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s33 offset:1840 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s33 offset:1844 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s33 offset:1848 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s33 offset:1852 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s33 offset:1856 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s33 offset:1860 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s33 offset:1864 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s33 offset:1868 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s33 offset:1872 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s33 offset:1876 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s33 offset:1880 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s33 offset:1884 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s33 offset:1888 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s33 offset:1892 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s33 offset:1896 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s33 offset:1900 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s33 offset:1904 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s33 offset:1908 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s33 offset:1912 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s33 offset:1916 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s33 offset:1920 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s33 offset:1924 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s33 offset:1928 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s33 offset:1932 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s33 offset:1936 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s33 offset:1940 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s33 offset:1944 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s33 offset:1948 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s33 offset:1952 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s33 offset:1956 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s33 offset:1960 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s33 offset:1964 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s33 offset:1968 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s33 offset:1972 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s33 offset:1976 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s33 offset:1980 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s33 offset:1984 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s33 offset:1988 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s33 offset:1992 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s33 offset:1996 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s33 offset:2000 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s33 offset:2004 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s33 offset:2008 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s33 offset:2012 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s33 offset:2016 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s33 offset:1768
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s33 offset:1772
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s33 offset:1776
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s33 offset:1780
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s33 offset:1784
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s33 offset:1788
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s33 offset:1792
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s33 offset:1796
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s33 offset:1800
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s33 offset:1804
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s33 offset:1808
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s33 offset:1812
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s33 offset:1816
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s33 offset:1820
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s33 offset:1824
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s33 offset:1828
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s33 offset:1832
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s33 offset:1836
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s33 offset:1840
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s33 offset:1844
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s33 offset:1848
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s33 offset:1852
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s33 offset:1856
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s33 offset:1860
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s33 offset:1864
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s33 offset:1868
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s33 offset:1872
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s33 offset:1876
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s33 offset:1880
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s33 offset:1884
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s33 offset:1888
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s33 offset:1892
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s33 offset:1896
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s33 offset:1900
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s33 offset:1904
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s33 offset:1908
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s33 offset:1912
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s33 offset:1916
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s33 offset:1920
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s33 offset:1924
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s33 offset:1928
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s33 offset:1932
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s33 offset:1936
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s33 offset:1940
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s33 offset:1944
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s33 offset:1948
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s33 offset:1952
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s33 offset:1956
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s33 offset:1960
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s33 offset:1964
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s33 offset:1968
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s33 offset:1972
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s33 offset:1976
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s33 offset:1980
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s33 offset:1984
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s33 offset:1988
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s33 offset:1992
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s33 offset:1996
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s33 offset:2000
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s33 offset:2004
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s33 offset:2008
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s33 offset:2012
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s33 offset:2016
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s33 offset:2020 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s33 offset:2024 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s33 offset:2028 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s33 offset:2032 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s33 offset:2036 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s33 offset:2040 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s33 offset:2044 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s33 offset:2048 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s33 offset:2052 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s33 offset:2056 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s33 offset:2060 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s33 offset:2064 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s33 offset:2068 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s33 offset:2072 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s33 offset:2076 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s33 offset:2080 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s33 offset:2084 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s33 offset:2088 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s33 offset:2092 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s33 offset:2096 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s33 offset:2100 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s33 offset:2104 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s33 offset:2108 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s33 offset:2112 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s33 offset:2116 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s33 offset:2120 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s33 offset:2124 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s33 offset:2128 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s33 offset:2132 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s33 offset:2136 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s33 offset:2140 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s33 offset:2144 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s33 offset:2148 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s33 offset:2152 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s33 offset:2156 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s33 offset:2160 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s33 offset:2164 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s33 offset:2168 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s33 offset:2172 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s33 offset:2176 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s33 offset:2180 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s33 offset:2184 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s33 offset:2188 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s33 offset:2192 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s33 offset:2196 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s33 offset:2200 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s33 offset:2204 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s33 offset:2208 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s33 offset:2212 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s33 offset:2216 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s33 offset:2220 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s33 offset:2224 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s33 offset:2228 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s33 offset:2232 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s33 offset:2236 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s33 offset:2240 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s33 offset:2244 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s33 offset:2248 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s33 offset:2252 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s33 offset:2256 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s33 offset:2260 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s33 offset:2264 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s33 offset:2268 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s33 offset:2020
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s33 offset:2024
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s33 offset:2028
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s33 offset:2032
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s33 offset:2036
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s33 offset:2040
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s33 offset:2044
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s33 offset:2048
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s33 offset:2052
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s33 offset:2056
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s33 offset:2060
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s33 offset:2064
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s33 offset:2068
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s33 offset:2072
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s33 offset:2076
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s33 offset:2080
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s33 offset:2084
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s33 offset:2088
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s33 offset:2092
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s33 offset:2096
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s33 offset:2100
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s33 offset:2104
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s33 offset:2108
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s33 offset:2112
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s33 offset:2116
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s33 offset:2120
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s33 offset:2124
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s33 offset:2128
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s33 offset:2132
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s33 offset:2136
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s33 offset:2140
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s33 offset:2144
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s33 offset:2148
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s33 offset:2152
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s33 offset:2156
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s33 offset:2160
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s33 offset:2164
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s33 offset:2168
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s33 offset:2172
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s33 offset:2176
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s33 offset:2180
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s33 offset:2184
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s33 offset:2188
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s33 offset:2192
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s33 offset:2196
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s33 offset:2200
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s33 offset:2204
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s33 offset:2208
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s33 offset:2212
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s33 offset:2216
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s33 offset:2220
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s33 offset:2224
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s33 offset:2228
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s33 offset:2232
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s33 offset:2236
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s33 offset:2240
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s33 offset:2244
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s33 offset:2248
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s33 offset:2252
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s33 offset:2256
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s33 offset:2260
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s33 offset:2264
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s33 offset:2268
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s33 offset:2272 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s33 offset:2276 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s33 offset:2280 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s33 offset:2284 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s33 offset:2288 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s33 offset:2292 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s33 offset:2296 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s33 offset:2300 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s33 offset:2304 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s33 offset:2308 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s33 offset:2312 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s33 offset:2316 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s33 offset:2320 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s33 offset:2324 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s33 offset:2328 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s33 offset:2332 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s33 offset:2336 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s33 offset:2340 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s33 offset:2344 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s33 offset:2348 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s33 offset:2352 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s33 offset:2356 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s33 offset:2360 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s33 offset:2364 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s33 offset:2368 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s33 offset:2372 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s33 offset:2376 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s33 offset:2380 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s33 offset:2384 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s33 offset:2388 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s33 offset:2392 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s33 offset:2396 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s33 offset:2400 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s33 offset:2404 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s33 offset:2408 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s33 offset:2412 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s33 offset:2416 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s33 offset:2420 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s33 offset:2424 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s33 offset:2428 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s33 offset:2432 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s33 offset:2436 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s33 offset:2440 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s33 offset:2444 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s33 offset:2448 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s33 offset:2452 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s33 offset:2456 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s33 offset:2460 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s33 offset:2464 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s33 offset:2468 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s33 offset:2472 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s33 offset:2476 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s33 offset:2480 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s33 offset:2484 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s33 offset:2488 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s33 offset:2492 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s33 offset:2496 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s33 offset:2500 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s33 offset:2504 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s33 offset:2508 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s33 offset:2512 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s33 offset:2516 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s33 offset:2520 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s33 offset:2272
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s33 offset:2276
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s33 offset:2280
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s33 offset:2284
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s33 offset:2288
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s33 offset:2292
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s33 offset:2296
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s33 offset:2300
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s33 offset:2304
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s33 offset:2308
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s33 offset:2312
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s33 offset:2316
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s33 offset:2320
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s33 offset:2324
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s33 offset:2328
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s33 offset:2332
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s33 offset:2336
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s33 offset:2340
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s33 offset:2344
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s33 offset:2348
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s33 offset:2352
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s33 offset:2356
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s33 offset:2360
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s33 offset:2364
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s33 offset:2368
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s33 offset:2372
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s33 offset:2376
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s33 offset:2380
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s33 offset:2384
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s33 offset:2388
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s33 offset:2392
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s33 offset:2396
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s33 offset:2400
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s33 offset:2404
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s33 offset:2408
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s33 offset:2412
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s33 offset:2416
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s33 offset:2420
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s33 offset:2424
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s33 offset:2428
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s33 offset:2432
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s33 offset:2436
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s33 offset:2440
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s33 offset:2444
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s33 offset:2448
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s33 offset:2452
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s33 offset:2456
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s33 offset:2460
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s33 offset:2464
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s33 offset:2468
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s33 offset:2472
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s33 offset:2476
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s33 offset:2480
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s33 offset:2484
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s33 offset:2488
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s33 offset:2492
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s33 offset:2496
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s33 offset:2500
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s33 offset:2504
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s33 offset:2508
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s33 offset:2512
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s33 offset:2516
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s33 offset:2520
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s33 offset:2524 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s33 offset:2528 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s33 offset:2532 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s33 offset:2536 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s33 offset:2540 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s33 offset:2544 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s33 offset:2548 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s33 offset:2552 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s33 offset:2556 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s33 offset:2560 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s33 offset:2564 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s33 offset:2568 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s33 offset:2572 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s33 offset:2576 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s33 offset:2580 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s33 offset:2584 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s33 offset:2588 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s33 offset:2592 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s33 offset:2596 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s33 offset:2600 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s33 offset:2604 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s33 offset:2608 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s33 offset:2612 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s33 offset:2616 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s33 offset:2620 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s33 offset:2624 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s33 offset:2524
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s33 offset:2528
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s33 offset:2532
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s33 offset:2536
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s33 offset:2540
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s33 offset:2544
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s33 offset:2548
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s33 offset:2552
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s33 offset:2556
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s33 offset:2560
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s33 offset:2564
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s33 offset:2568
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s33 offset:2572
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s33 offset:2576
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s33 offset:2580
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s33 offset:2584
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s33 offset:2588
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s33 offset:2592
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s33 offset:2596
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s33 offset:2600
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s33 offset:2604
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s33 offset:2608
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s33 offset:2612
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s33 offset:2616
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s33 offset:2620
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s33 offset:2624
; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 12 ; msbs: dst=0 src0=0 src1=3 src2=0
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s33 offset:2628 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s33 offset:2632 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s33 offset:2636 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s33 offset:2640 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s33 offset:2644 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s33 offset:2648 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s33 offset:2652 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s33 offset:2656 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s33 offset:2660 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s33 offset:2664 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s33 offset:2668 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s33 offset:2672 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s33 offset:2676 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s33 offset:2680 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s33 offset:2684 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s33 offset:2688 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s33 offset:2692 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s33 offset:2696 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s33 offset:2700 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s33 offset:2704 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s33 offset:2708 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s33 offset:2712 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s33 offset:2716 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s33 offset:2720 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s33 offset:2724 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s33 offset:2728 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s33 offset:2732 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s33 offset:2736 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s33 offset:2740 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s33 offset:2744 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s33 offset:2748 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s33 offset:2752 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s33 offset:2756 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s33 offset:2760 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s33 offset:2764 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s33 offset:2768 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s33 offset:2772 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s33 offset:2628
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s33 offset:2632
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s33 offset:2636
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s33 offset:2640
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s33 offset:2644
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s33 offset:2648
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s33 offset:2652
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s33 offset:2656
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s33 offset:2660
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s33 offset:2664
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s33 offset:2668
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s33 offset:2672
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s33 offset:2676
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s33 offset:2680
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s33 offset:2684
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s33 offset:2688
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s33 offset:2692
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s33 offset:2696
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s33 offset:2700
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s33 offset:2704
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s33 offset:2708
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s33 offset:2712
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s33 offset:2716
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s33 offset:2720
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s33 offset:2724
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s33 offset:2728
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s33 offset:2732
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s33 offset:2736
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s33 offset:2740
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s33 offset:2744
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s33 offset:2748
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s33 offset:2752
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s33 offset:2756
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s33 offset:2760
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s33 offset:2764
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s33 offset:2768
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s33 offset:2772
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s33 offset:2776 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s33 offset:2780 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s33 offset:2784 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s33 offset:2788 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s33 offset:2792 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s33 offset:2796 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s33 offset:2800 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s33 offset:2804 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s33 offset:2808 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s33 offset:2812 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s33 offset:2816 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s33 offset:2820 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s33 offset:2824 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s33 offset:2828 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s33 offset:2832 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s33 offset:2836 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s33 offset:2840 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s33 offset:2844 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s33 offset:2848 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s33 offset:2852 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s33 offset:2856 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s33 offset:2860 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s33 offset:2864 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s33 offset:2868 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s33 offset:2872 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s33 offset:2876 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s33 offset:2880 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s33 offset:2884 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s33 offset:2888 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s33 offset:2892 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s33 offset:2896 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s33 offset:2900 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s33 offset:2904 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s33 offset:2908 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s33 offset:2912 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s33 offset:2916 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s33 offset:2920 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s33 offset:2924 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s33 offset:2928 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s33 offset:2932 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s33 offset:2936 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s33 offset:2940 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s33 offset:2944 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s33 offset:2948 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s33 offset:2952 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s33 offset:2956 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s33 offset:2960 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s33 offset:2964 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s33 offset:2968 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s33 offset:2972 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s33 offset:2976 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s33 offset:2980 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s33 offset:2984 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s33 offset:2988 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s33 offset:2992 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s33 offset:2996 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s33 offset:3000 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s33 offset:3004 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s33 offset:3008 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s33 offset:3012 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s33 offset:3016 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s33 offset:3020 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s33 offset:3024 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s33 offset:2776
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s33 offset:2780
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s33 offset:2784
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s33 offset:2788
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s33 offset:2792
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s33 offset:2796
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s33 offset:2800
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s33 offset:2804
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s33 offset:2808
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s33 offset:2812
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s33 offset:2816
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s33 offset:2820
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s33 offset:2824
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s33 offset:2828
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s33 offset:2832
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s33 offset:2836
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s33 offset:2840
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s33 offset:2844
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s33 offset:2848
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s33 offset:2852
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s33 offset:2856
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s33 offset:2860
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s33 offset:2864
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s33 offset:2868
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s33 offset:2872
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s33 offset:2876
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s33 offset:2880
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s33 offset:2884
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s33 offset:2888
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s33 offset:2892
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s33 offset:2896
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s33 offset:2900
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s33 offset:2904
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s33 offset:2908
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s33 offset:2912
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s33 offset:2916
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s33 offset:2920
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s33 offset:2924
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s33 offset:2928
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s33 offset:2932
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s33 offset:2936
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s33 offset:2940
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s33 offset:2944
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s33 offset:2948
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s33 offset:2952
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s33 offset:2956
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s33 offset:2960
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s33 offset:2964
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s33 offset:2968
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s33 offset:2972
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s33 offset:2976
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s33 offset:2980
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s33 offset:2984
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s33 offset:2988
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s33 offset:2992
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s33 offset:2996
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s33 offset:3000
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s33 offset:3004
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s33 offset:3008
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s33 offset:3012
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s33 offset:3016
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s33 offset:3020
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s33 offset:3024
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s33 offset:3028 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s33 offset:3032 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s33 offset:3036 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s33 offset:3040 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s33 offset:3044 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s33 offset:3048 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s33 offset:3052 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s33 offset:3056 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s33 offset:3060 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s33 offset:3064 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s33 offset:3068 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s33 offset:3072 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s33 offset:3076 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s33 offset:3080 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s33 offset:3084 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s33 offset:3088 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s33 offset:3092 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s33 offset:3096 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s33 offset:3100 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s33 offset:3104 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s33 offset:3108 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s33 offset:3112 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s33 offset:3116 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s33 offset:3120 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s33 offset:3124 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s33 offset:3128 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s33 offset:3132 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s33 offset:3136 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s33 offset:3140 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s33 offset:3144 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s33 offset:3148 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s33 offset:3152 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s33 offset:3156 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s33 offset:3160 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s33 offset:3164 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s33 offset:3168 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s33 offset:3172 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s33 offset:3176 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s33 offset:3180 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s33 offset:3184 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s33 offset:3188 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s33 offset:3192 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s33 offset:3196 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s33 offset:3200 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s33 offset:3204 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s33 offset:3208 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s33 offset:3212 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s33 offset:3216 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s33 offset:3220 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s33 offset:3224 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s33 offset:3228 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s33 offset:3232 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s33 offset:3236 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s33 offset:3240 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s33 offset:3244 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s33 offset:3248 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s33 offset:3252 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s33 offset:3256 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s33 offset:3260 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s33 offset:3264 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s33 offset:3268 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s33 offset:3272 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s33 offset:3276 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s33 offset:3028
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s33 offset:3032
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s33 offset:3036
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s33 offset:3040
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s33 offset:3044
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s33 offset:3048
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s33 offset:3052
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s33 offset:3056
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s33 offset:3060
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s33 offset:3064
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s33 offset:3068
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s33 offset:3072
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s33 offset:3076
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s33 offset:3080
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s33 offset:3084
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s33 offset:3088
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s33 offset:3092
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s33 offset:3096
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s33 offset:3100
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s33 offset:3104
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s33 offset:3108
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s33 offset:3112
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s33 offset:3116
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s33 offset:3120
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s33 offset:3124
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s33 offset:3128
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s33 offset:3132
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s33 offset:3136
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s33 offset:3140
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s33 offset:3144
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s33 offset:3148
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s33 offset:3152
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s33 offset:3156
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s33 offset:3160
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s33 offset:3164
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s33 offset:3168
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s33 offset:3172
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s33 offset:3176
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s33 offset:3180
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s33 offset:3184
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s33 offset:3188
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s33 offset:3192
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s33 offset:3196
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s33 offset:3200
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s33 offset:3204
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s33 offset:3208
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s33 offset:3212
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s33 offset:3216
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s33 offset:3220
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s33 offset:3224
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s33 offset:3228
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s33 offset:3232
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s33 offset:3236
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s33 offset:3240
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s33 offset:3244
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s33 offset:3248
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s33 offset:3252
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s33 offset:3256
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s33 offset:3260
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s33 offset:3264
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s33 offset:3268
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s33 offset:3272
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s33 offset:3276
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s33 offset:3280 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s33 offset:3284 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s33 offset:3288 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s33 offset:3292 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s33 offset:3296 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s33 offset:3300 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s33 offset:3304 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s33 offset:3308 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s33 offset:3312 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s33 offset:3316 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s33 offset:3320 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s33 offset:3324 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s33 offset:3328 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s33 offset:3332 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s33 offset:3336 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s33 offset:3340 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s33 offset:3344 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s33 offset:3348 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s33 offset:3352 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s33 offset:3356 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s33 offset:3360 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s33 offset:3364 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s33 offset:3368 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s33 offset:3372 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s33 offset:3376 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s33 offset:3380 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s33 offset:3384 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s33 offset:3388 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s33 offset:3392 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s33 offset:3396 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s33 offset:3400 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s33 offset:3404 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s33 offset:3408 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s33 offset:3412 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s33 offset:3416 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s33 offset:3420 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s33 offset:3424 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s33 offset:3428 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s33 offset:3432 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s33 offset:3436 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s33 offset:3440 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s33 offset:3444 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s33 offset:3448 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s33 offset:3452 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s33 offset:3456 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s33 offset:3460 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s33 offset:3464 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s33 offset:3468 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s33 offset:3472 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s33 offset:3476 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s33 offset:3480 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s33 offset:3484 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s33 offset:3488 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s33 offset:3492 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s33 offset:3496 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s33 offset:3500 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s33 offset:3504 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s33 offset:3508 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s33 offset:3512 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s33 offset:3516 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s33 offset:3520 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s33 offset:3524 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s33 offset:3528 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s33 offset:3280
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s33 offset:3284
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s33 offset:3288
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s33 offset:3292
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s33 offset:3296
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s33 offset:3300
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s33 offset:3304
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s33 offset:3308
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s33 offset:3312
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s33 offset:3316
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s33 offset:3320
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s33 offset:3324
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s33 offset:3328
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s33 offset:3332
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s33 offset:3336
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s33 offset:3340
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s33 offset:3344
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s33 offset:3348
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s33 offset:3352
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s33 offset:3356
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s33 offset:3360
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s33 offset:3364
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s33 offset:3368
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s33 offset:3372
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s33 offset:3376
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s33 offset:3380
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s33 offset:3384
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s33 offset:3388
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s33 offset:3392
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s33 offset:3396
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s33 offset:3400
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s33 offset:3404
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s33 offset:3408
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s33 offset:3412
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s33 offset:3416
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s33 offset:3420
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s33 offset:3424
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s33 offset:3428
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s33 offset:3432
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s33 offset:3436
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s33 offset:3440
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s33 offset:3444
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s33 offset:3448
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s33 offset:3452
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s33 offset:3456
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s33 offset:3460
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s33 offset:3464
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s33 offset:3468
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s33 offset:3472
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s33 offset:3476
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s33 offset:3480
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s33 offset:3484
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s33 offset:3488
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s33 offset:3492
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s33 offset:3496
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s33 offset:3500
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s33 offset:3504
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s33 offset:3508
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s33 offset:3512
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s33 offset:3516
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s33 offset:3520
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s33 offset:3524
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s33 offset:3528
; GFX1250-DAGISEL-NEXT: s_clause 0x1d
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s33 offset:3532 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s33 offset:3536 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s33 offset:3540 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s33 offset:3544 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s33 offset:3548 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s33 offset:3552 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s33 offset:3556 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s33 offset:3560 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s33 offset:3564 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s33 offset:3568 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s33 offset:3572 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s33 offset:3576 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s33 offset:3580 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s33 offset:3584 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s33 offset:3588 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s33 offset:3592 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s33 offset:3596 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s33 offset:3600 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s33 offset:3604 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s33 offset:3608 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s33 offset:3612 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s33 offset:3616 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s33 offset:3620 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s33 offset:3624 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s33 offset:3628 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s33 offset:3632 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s33 offset:3636 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s33 offset:3640 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s33 offset:3644 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s33 offset:3648 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s33 offset:3532
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s33 offset:3536
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s33 offset:3540
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s33 offset:3544
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s33 offset:3548
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s33 offset:3552
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s33 offset:3556
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s33 offset:3560
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s33 offset:3564
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s33 offset:3568
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s33 offset:3572
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s33 offset:3576
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s33 offset:3580
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s33 offset:3584
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s33 offset:3588
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s33 offset:3592
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s33 offset:3596
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s33 offset:3600
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s33 offset:3604
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s33 offset:3608
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s33 offset:3612
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s33 offset:3616
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s33 offset:3620
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s33 offset:3624
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s33 offset:3628
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s33 offset:3632
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s33 offset:3636
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s33 offset:3640
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s33 offset:3644
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s33 offset:3648
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 scope:SCOPE_SE ; 4-byte Folded Spill
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s0, 3
; GFX1250-DAGISEL-NEXT: v_mov_b32_e32 v2, v0
@@ -4588,7 +4588,7 @@ define amdgpu_cs void @call_from_entry(<8 x float> %x, ptr %p) {
; GFX1250-DAGISEL-NEXT: s_mov_b32 s32, 0
; GFX1250-DAGISEL-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
; GFX1250-DAGISEL-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
-; GFX1250-DAGISEL-NEXT: flat_store_b32 v[40:41], v0 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: flat_store_b32 v[40:41], v0
; GFX1250-DAGISEL-NEXT: s_endpgm
%ret = call float(ptr, ...) @llvm.amdgcn.call.whole.wave(ptr @callee, <8 x float> %x) convergent
store float %ret, ptr %p
@@ -5974,942 +5974,942 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GFX1250-DAGISEL-NEXT: s_mov_b32 s33, s32
; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s4, -1
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:172 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:176 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:180 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:184 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:188 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:192 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:196 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:200 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:204 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:208 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:212 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:216 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:220 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:224 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:228 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:232 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:236 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:240 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:244 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:248 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:252 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:256 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:260 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:172
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:176
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:180
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:184
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:188
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:192
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:196
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:200
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:204
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:208
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:212
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:216
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:220
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:224
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:228
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:232
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:236
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:240
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:244
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:248
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:252
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:256
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:260
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:264 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:268 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:272 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:276 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:280 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:284 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:288 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:292 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:296 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:300 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:304 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:308 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:312 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:316 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:320 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:324 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:328 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:332 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:336 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:340 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:344 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:348 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:352 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:356 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:360 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:364 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:368 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:372 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:376 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:380 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:384 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:388 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:392 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:396 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:400 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:404 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:408 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:412 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:416 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:420 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:424 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:428 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:432 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:436 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:440 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:444 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:448 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:452 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:456 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:460 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:464 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:468 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:472 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:476 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:480 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:484 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:488 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:492 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:496 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:500 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:504 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:508 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:512 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:264
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:268
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:272
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:276
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:280
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:284
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:288
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:292
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:296
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:300
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:304
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:308
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:312
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:316
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:320
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:324
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:328
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:332
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:336
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:340
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:344
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:348
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:352
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:356
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:360
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:364
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:368
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:372
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:376
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:380
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:384
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:388
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:392
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:396
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:400
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:404
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:408
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:412
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:416
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:420
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:424
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:428
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:432
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:436
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:440
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:444
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:448
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:452
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:456
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:460
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:464
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:468
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:472
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:476
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:480
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:484
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:488
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:492
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:496
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:500
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:504
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:508
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:512
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:516 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:520 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:524 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:528 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:532 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:536 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:540 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:544 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:548 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:552 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:556 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:560 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:564 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:568 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:572 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:576 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:580 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:584 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:516
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:520
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:524
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:528
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:532
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:536
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:540
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:544
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:548
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:552
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:556
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:560
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:564
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:568
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:572
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:576
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:580
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:584
; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 4 ; msbs: dst=0 src0=0 src1=1 src2=0
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s33 offset:588 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s33 offset:592 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s33 offset:596 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s33 offset:600 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s33 offset:604 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s33 offset:608 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s33 offset:612 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s33 offset:616 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s33 offset:620 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s33 offset:624 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s33 offset:628 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s33 offset:632 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s33 offset:636 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s33 offset:640 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s33 offset:644 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s33 offset:648 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s33 offset:652 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s33 offset:656 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s33 offset:660 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s33 offset:664 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s33 offset:668 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s33 offset:672 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s33 offset:676 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s33 offset:680 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s33 offset:684 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s33 offset:688 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s33 offset:692 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s33 offset:696 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s33 offset:700 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s33 offset:704 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s33 offset:708 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s33 offset:712 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s33 offset:716 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s33 offset:720 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s33 offset:724 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s33 offset:728 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s33 offset:732 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s33 offset:736 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s33 offset:740 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s33 offset:744 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s33 offset:748 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s33 offset:752 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s33 offset:756 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s33 offset:760 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s33 offset:764 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s33 offset:588
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s33 offset:592
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s33 offset:596
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s33 offset:600
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s33 offset:604
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s33 offset:608
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s33 offset:612
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s33 offset:616
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s33 offset:620
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s33 offset:624
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s33 offset:628
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s33 offset:632
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s33 offset:636
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s33 offset:640
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s33 offset:644
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s33 offset:648
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s33 offset:652
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s33 offset:656
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s33 offset:660
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s33 offset:664
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s33 offset:668
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s33 offset:672
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s33 offset:676
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s33 offset:680
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s33 offset:684
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s33 offset:688
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s33 offset:692
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s33 offset:696
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s33 offset:700
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s33 offset:704
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s33 offset:708
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s33 offset:712
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s33 offset:716
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s33 offset:720
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s33 offset:724
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s33 offset:728
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s33 offset:732
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s33 offset:736
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s33 offset:740
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s33 offset:744
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s33 offset:748
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s33 offset:752
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s33 offset:756
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s33 offset:760
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s33 offset:764
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s33 offset:768 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s33 offset:772 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s33 offset:776 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s33 offset:780 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s33 offset:784 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s33 offset:788 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s33 offset:792 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s33 offset:796 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s33 offset:800 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s33 offset:804 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s33 offset:808 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s33 offset:812 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s33 offset:816 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s33 offset:820 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s33 offset:824 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s33 offset:828 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s33 offset:832 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s33 offset:836 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s33 offset:840 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s33 offset:844 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s33 offset:848 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s33 offset:852 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s33 offset:856 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s33 offset:860 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s33 offset:864 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s33 offset:868 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s33 offset:872 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s33 offset:876 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s33 offset:880 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s33 offset:884 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s33 offset:888 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s33 offset:892 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s33 offset:896 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s33 offset:900 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s33 offset:904 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s33 offset:908 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s33 offset:912 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s33 offset:916 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s33 offset:920 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s33 offset:924 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s33 offset:928 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s33 offset:932 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s33 offset:936 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s33 offset:940 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s33 offset:944 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s33 offset:948 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s33 offset:952 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s33 offset:956 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s33 offset:960 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s33 offset:964 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s33 offset:968 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s33 offset:972 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s33 offset:976 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s33 offset:980 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s33 offset:984 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s33 offset:988 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s33 offset:992 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s33 offset:996 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s33 offset:1000 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s33 offset:1004 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s33 offset:1008 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s33 offset:1012 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s33 offset:1016 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s33 offset:768
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s33 offset:772
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s33 offset:776
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s33 offset:780
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s33 offset:784
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s33 offset:788
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s33 offset:792
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s33 offset:796
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s33 offset:800
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s33 offset:804
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s33 offset:808
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s33 offset:812
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s33 offset:816
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s33 offset:820
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s33 offset:824
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s33 offset:828
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s33 offset:832
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s33 offset:836
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s33 offset:840
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s33 offset:844
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s33 offset:848
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s33 offset:852
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s33 offset:856
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s33 offset:860
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s33 offset:864
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s33 offset:868
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s33 offset:872
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s33 offset:876
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s33 offset:880
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s33 offset:884
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s33 offset:888
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s33 offset:892
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s33 offset:896
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s33 offset:900
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s33 offset:904
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s33 offset:908
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s33 offset:912
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s33 offset:916
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s33 offset:920
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s33 offset:924
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s33 offset:928
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s33 offset:932
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s33 offset:936
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s33 offset:940
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s33 offset:944
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s33 offset:948
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s33 offset:952
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s33 offset:956
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s33 offset:960
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s33 offset:964
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s33 offset:968
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s33 offset:972
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s33 offset:976
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s33 offset:980
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s33 offset:984
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s33 offset:988
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s33 offset:992
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s33 offset:996
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s33 offset:1000
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s33 offset:1004
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s33 offset:1008
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s33 offset:1012
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s33 offset:1016
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s33 offset:1020 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s33 offset:1024 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s33 offset:1028 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s33 offset:1032 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s33 offset:1036 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s33 offset:1040 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s33 offset:1044 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s33 offset:1048 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s33 offset:1052 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s33 offset:1056 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s33 offset:1060 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s33 offset:1064 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s33 offset:1068 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s33 offset:1072 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s33 offset:1076 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s33 offset:1080 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s33 offset:1084 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s33 offset:1088 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s33 offset:1092 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s33 offset:1096 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s33 offset:1100 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s33 offset:1104 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s33 offset:1108 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s33 offset:1112 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s33 offset:1116 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s33 offset:1120 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s33 offset:1124 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s33 offset:1128 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s33 offset:1132 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s33 offset:1136 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s33 offset:1140 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s33 offset:1144 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s33 offset:1148 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s33 offset:1152 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s33 offset:1156 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s33 offset:1160 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s33 offset:1164 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s33 offset:1168 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s33 offset:1172 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s33 offset:1176 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s33 offset:1180 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s33 offset:1184 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s33 offset:1188 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s33 offset:1192 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s33 offset:1196 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s33 offset:1200 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s33 offset:1204 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s33 offset:1208 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s33 offset:1212 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s33 offset:1216 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s33 offset:1220 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s33 offset:1224 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s33 offset:1228 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s33 offset:1232 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s33 offset:1236 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s33 offset:1240 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s33 offset:1244 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s33 offset:1248 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s33 offset:1252 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s33 offset:1256 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s33 offset:1260 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s33 offset:1264 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s33 offset:1268 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s33 offset:1020
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s33 offset:1024
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s33 offset:1028
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s33 offset:1032
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s33 offset:1036
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s33 offset:1040
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s33 offset:1044
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s33 offset:1048
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s33 offset:1052
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s33 offset:1056
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s33 offset:1060
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s33 offset:1064
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s33 offset:1068
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s33 offset:1072
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s33 offset:1076
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s33 offset:1080
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s33 offset:1084
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s33 offset:1088
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s33 offset:1092
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s33 offset:1096
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s33 offset:1100
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s33 offset:1104
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s33 offset:1108
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s33 offset:1112
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s33 offset:1116
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s33 offset:1120
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s33 offset:1124
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s33 offset:1128
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s33 offset:1132
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s33 offset:1136
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s33 offset:1140
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s33 offset:1144
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s33 offset:1148
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s33 offset:1152
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s33 offset:1156
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s33 offset:1160
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s33 offset:1164
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s33 offset:1168
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s33 offset:1172
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s33 offset:1176
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s33 offset:1180
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s33 offset:1184
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s33 offset:1188
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s33 offset:1192
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s33 offset:1196
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s33 offset:1200
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s33 offset:1204
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s33 offset:1208
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s33 offset:1212
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s33 offset:1216
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s33 offset:1220
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s33 offset:1224
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s33 offset:1228
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s33 offset:1232
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s33 offset:1236
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s33 offset:1240
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s33 offset:1244
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s33 offset:1248
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s33 offset:1252
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s33 offset:1256
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s33 offset:1260
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s33 offset:1264
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s33 offset:1268
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s33 offset:1272 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s33 offset:1276 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s33 offset:1280 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s33 offset:1284 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s33 offset:1288 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s33 offset:1292 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s33 offset:1296 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s33 offset:1300 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s33 offset:1304 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s33 offset:1308 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s33 offset:1312 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s33 offset:1316 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s33 offset:1320 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s33 offset:1324 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s33 offset:1328 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s33 offset:1332 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s33 offset:1336 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s33 offset:1340 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s33 offset:1344 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s33 offset:1348 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s33 offset:1352 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s33 offset:1356 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s33 offset:1360 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s33 offset:1364 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s33 offset:1368 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s33 offset:1372 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s33 offset:1376 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s33 offset:1380 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s33 offset:1384 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s33 offset:1388 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s33 offset:1392 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s33 offset:1396 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s33 offset:1400 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s33 offset:1404 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s33 offset:1408 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s33 offset:1412 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s33 offset:1416 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s33 offset:1420 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s33 offset:1424 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s33 offset:1428 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s33 offset:1432 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s33 offset:1436 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s33 offset:1440 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s33 offset:1444 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s33 offset:1448 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s33 offset:1452 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s33 offset:1456 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s33 offset:1460 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s33 offset:1464 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s33 offset:1468 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s33 offset:1472 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s33 offset:1476 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s33 offset:1480 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s33 offset:1484 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s33 offset:1488 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s33 offset:1492 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s33 offset:1496 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s33 offset:1500 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s33 offset:1504 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s33 offset:1508 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s33 offset:1512 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s33 offset:1516 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s33 offset:1520 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s33 offset:1272
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s33 offset:1276
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s33 offset:1280
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s33 offset:1284
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s33 offset:1288
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s33 offset:1292
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s33 offset:1296
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s33 offset:1300
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s33 offset:1304
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s33 offset:1308
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s33 offset:1312
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s33 offset:1316
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s33 offset:1320
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s33 offset:1324
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s33 offset:1328
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s33 offset:1332
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s33 offset:1336
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s33 offset:1340
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s33 offset:1344
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s33 offset:1348
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s33 offset:1352
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s33 offset:1356
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s33 offset:1360
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s33 offset:1364
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s33 offset:1368
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s33 offset:1372
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s33 offset:1376
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s33 offset:1380
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s33 offset:1384
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s33 offset:1388
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s33 offset:1392
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s33 offset:1396
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s33 offset:1400
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s33 offset:1404
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s33 offset:1408
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s33 offset:1412
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s33 offset:1416
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s33 offset:1420
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s33 offset:1424
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s33 offset:1428
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s33 offset:1432
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s33 offset:1436
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s33 offset:1440
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s33 offset:1444
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s33 offset:1448
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s33 offset:1452
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s33 offset:1456
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s33 offset:1460
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s33 offset:1464
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s33 offset:1468
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s33 offset:1472
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s33 offset:1476
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s33 offset:1480
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s33 offset:1484
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s33 offset:1488
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s33 offset:1492
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s33 offset:1496
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s33 offset:1500
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s33 offset:1504
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s33 offset:1508
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s33 offset:1512
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s33 offset:1516
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s33 offset:1520
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s33 offset:1524 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s33 offset:1528 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s33 offset:1532 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s33 offset:1536 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s33 offset:1540 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s33 offset:1544 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s33 offset:1548 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s33 offset:1552 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s33 offset:1556 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s33 offset:1560 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s33 offset:1564 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s33 offset:1568 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s33 offset:1572 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s33 offset:1576 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s33 offset:1580 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s33 offset:1584 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s33 offset:1588 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s33 offset:1592 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s33 offset:1596 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s33 offset:1600 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s33 offset:1604 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s33 offset:1608 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s33 offset:1524
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s33 offset:1528
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s33 offset:1532
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s33 offset:1536
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s33 offset:1540
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s33 offset:1544
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s33 offset:1548
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s33 offset:1552
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s33 offset:1556
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s33 offset:1560
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s33 offset:1564
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s33 offset:1568
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s33 offset:1572
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s33 offset:1576
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s33 offset:1580
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s33 offset:1584
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s33 offset:1588
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s33 offset:1592
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s33 offset:1596
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s33 offset:1600
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s33 offset:1604
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s33 offset:1608
; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 8 ; msbs: dst=0 src0=0 src1=2 src2=0
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s33 offset:1612 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s33 offset:1616 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s33 offset:1620 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s33 offset:1624 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s33 offset:1628 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s33 offset:1632 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s33 offset:1636 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s33 offset:1640 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s33 offset:1644 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s33 offset:1648 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s33 offset:1652 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s33 offset:1656 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s33 offset:1660 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s33 offset:1664 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s33 offset:1668 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s33 offset:1672 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s33 offset:1676 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s33 offset:1680 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s33 offset:1684 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s33 offset:1688 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s33 offset:1692 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s33 offset:1696 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s33 offset:1700 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s33 offset:1704 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s33 offset:1708 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s33 offset:1712 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s33 offset:1716 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s33 offset:1720 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s33 offset:1724 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s33 offset:1728 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s33 offset:1732 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s33 offset:1736 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s33 offset:1740 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s33 offset:1744 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s33 offset:1748 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s33 offset:1752 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s33 offset:1756 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s33 offset:1760 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s33 offset:1764 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s33 offset:1768 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s33 offset:1772 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s33 offset:1612
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s33 offset:1616
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s33 offset:1620
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s33 offset:1624
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s33 offset:1628
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s33 offset:1632
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s33 offset:1636
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s33 offset:1640
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s33 offset:1644
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s33 offset:1648
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s33 offset:1652
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s33 offset:1656
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s33 offset:1660
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s33 offset:1664
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s33 offset:1668
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s33 offset:1672
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s33 offset:1676
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s33 offset:1680
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s33 offset:1684
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s33 offset:1688
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s33 offset:1692
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s33 offset:1696
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s33 offset:1700
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s33 offset:1704
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s33 offset:1708
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s33 offset:1712
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s33 offset:1716
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s33 offset:1720
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s33 offset:1724
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s33 offset:1728
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s33 offset:1732
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s33 offset:1736
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s33 offset:1740
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s33 offset:1744
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s33 offset:1748
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s33 offset:1752
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s33 offset:1756
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s33 offset:1760
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s33 offset:1764
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s33 offset:1768
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s33 offset:1772
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s33 offset:1776 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s33 offset:1780 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s33 offset:1784 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s33 offset:1788 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s33 offset:1792 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s33 offset:1796 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s33 offset:1800 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s33 offset:1804 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s33 offset:1808 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s33 offset:1812 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s33 offset:1816 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s33 offset:1820 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s33 offset:1824 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s33 offset:1828 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s33 offset:1832 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s33 offset:1836 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s33 offset:1840 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s33 offset:1844 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s33 offset:1848 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s33 offset:1852 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s33 offset:1856 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s33 offset:1860 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s33 offset:1864 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s33 offset:1868 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s33 offset:1872 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s33 offset:1876 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s33 offset:1880 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s33 offset:1884 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s33 offset:1888 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s33 offset:1892 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s33 offset:1896 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s33 offset:1900 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s33 offset:1904 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s33 offset:1908 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s33 offset:1912 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s33 offset:1916 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s33 offset:1920 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s33 offset:1924 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s33 offset:1928 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s33 offset:1932 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s33 offset:1936 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s33 offset:1940 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s33 offset:1944 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s33 offset:1948 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s33 offset:1952 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s33 offset:1956 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s33 offset:1960 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s33 offset:1964 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s33 offset:1968 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s33 offset:1972 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s33 offset:1976 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s33 offset:1980 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s33 offset:1984 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s33 offset:1988 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s33 offset:1992 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s33 offset:1996 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s33 offset:2000 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s33 offset:2004 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s33 offset:2008 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s33 offset:2012 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s33 offset:2016 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s33 offset:2020 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s33 offset:2024 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s33 offset:1776
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s33 offset:1780
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s33 offset:1784
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s33 offset:1788
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s33 offset:1792
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s33 offset:1796
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s33 offset:1800
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s33 offset:1804
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s33 offset:1808
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s33 offset:1812
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s33 offset:1816
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s33 offset:1820
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s33 offset:1824
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s33 offset:1828
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s33 offset:1832
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s33 offset:1836
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s33 offset:1840
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s33 offset:1844
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s33 offset:1848
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s33 offset:1852
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s33 offset:1856
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s33 offset:1860
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s33 offset:1864
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s33 offset:1868
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s33 offset:1872
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s33 offset:1876
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s33 offset:1880
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s33 offset:1884
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s33 offset:1888
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s33 offset:1892
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s33 offset:1896
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s33 offset:1900
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s33 offset:1904
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s33 offset:1908
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s33 offset:1912
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s33 offset:1916
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s33 offset:1920
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s33 offset:1924
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s33 offset:1928
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s33 offset:1932
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s33 offset:1936
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s33 offset:1940
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s33 offset:1944
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s33 offset:1948
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s33 offset:1952
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s33 offset:1956
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s33 offset:1960
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s33 offset:1964
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s33 offset:1968
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s33 offset:1972
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s33 offset:1976
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s33 offset:1980
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s33 offset:1984
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s33 offset:1988
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s33 offset:1992
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s33 offset:1996
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s33 offset:2000
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s33 offset:2004
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s33 offset:2008
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s33 offset:2012
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s33 offset:2016
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s33 offset:2020
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s33 offset:2024
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s33 offset:2028 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s33 offset:2032 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s33 offset:2036 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s33 offset:2040 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s33 offset:2044 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s33 offset:2048 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s33 offset:2052 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s33 offset:2056 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s33 offset:2060 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s33 offset:2064 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s33 offset:2068 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s33 offset:2072 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s33 offset:2076 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s33 offset:2080 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s33 offset:2084 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s33 offset:2088 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s33 offset:2092 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s33 offset:2096 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s33 offset:2100 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s33 offset:2104 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s33 offset:2108 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s33 offset:2112 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s33 offset:2116 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s33 offset:2120 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s33 offset:2124 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s33 offset:2128 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s33 offset:2132 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s33 offset:2136 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s33 offset:2140 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s33 offset:2144 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s33 offset:2148 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s33 offset:2152 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s33 offset:2156 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s33 offset:2160 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s33 offset:2164 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s33 offset:2168 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s33 offset:2172 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s33 offset:2176 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s33 offset:2180 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s33 offset:2184 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s33 offset:2188 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s33 offset:2192 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s33 offset:2196 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s33 offset:2200 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s33 offset:2204 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s33 offset:2208 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s33 offset:2212 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s33 offset:2216 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s33 offset:2220 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s33 offset:2224 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s33 offset:2228 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s33 offset:2232 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s33 offset:2236 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s33 offset:2240 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s33 offset:2244 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s33 offset:2248 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s33 offset:2252 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s33 offset:2256 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s33 offset:2260 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s33 offset:2264 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s33 offset:2268 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s33 offset:2272 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s33 offset:2276 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s33 offset:2028
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s33 offset:2032
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s33 offset:2036
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s33 offset:2040
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s33 offset:2044
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s33 offset:2048
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s33 offset:2052
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s33 offset:2056
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s33 offset:2060
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s33 offset:2064
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s33 offset:2068
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s33 offset:2072
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s33 offset:2076
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s33 offset:2080
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s33 offset:2084
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s33 offset:2088
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s33 offset:2092
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s33 offset:2096
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s33 offset:2100
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s33 offset:2104
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s33 offset:2108
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s33 offset:2112
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s33 offset:2116
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s33 offset:2120
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s33 offset:2124
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s33 offset:2128
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s33 offset:2132
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s33 offset:2136
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s33 offset:2140
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s33 offset:2144
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s33 offset:2148
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s33 offset:2152
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s33 offset:2156
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s33 offset:2160
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s33 offset:2164
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s33 offset:2168
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s33 offset:2172
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s33 offset:2176
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s33 offset:2180
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s33 offset:2184
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s33 offset:2188
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s33 offset:2192
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s33 offset:2196
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s33 offset:2200
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s33 offset:2204
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s33 offset:2208
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s33 offset:2212
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s33 offset:2216
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s33 offset:2220
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s33 offset:2224
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s33 offset:2228
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s33 offset:2232
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s33 offset:2236
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s33 offset:2240
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s33 offset:2244
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s33 offset:2248
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s33 offset:2252
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s33 offset:2256
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s33 offset:2260
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s33 offset:2264
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s33 offset:2268
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s33 offset:2272
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s33 offset:2276
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s33 offset:2280 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s33 offset:2284 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s33 offset:2288 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s33 offset:2292 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s33 offset:2296 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s33 offset:2300 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s33 offset:2304 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s33 offset:2308 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s33 offset:2312 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s33 offset:2316 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s33 offset:2320 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s33 offset:2324 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s33 offset:2328 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s33 offset:2332 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s33 offset:2336 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s33 offset:2340 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s33 offset:2344 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s33 offset:2348 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s33 offset:2352 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s33 offset:2356 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s33 offset:2360 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s33 offset:2364 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s33 offset:2368 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s33 offset:2372 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s33 offset:2376 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s33 offset:2380 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s33 offset:2384 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s33 offset:2388 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s33 offset:2392 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s33 offset:2396 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s33 offset:2400 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s33 offset:2404 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s33 offset:2408 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s33 offset:2412 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s33 offset:2416 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s33 offset:2420 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s33 offset:2424 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s33 offset:2428 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s33 offset:2432 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s33 offset:2436 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s33 offset:2440 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s33 offset:2444 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s33 offset:2448 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s33 offset:2452 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s33 offset:2456 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s33 offset:2460 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s33 offset:2464 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s33 offset:2468 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s33 offset:2472 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s33 offset:2476 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s33 offset:2480 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s33 offset:2484 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s33 offset:2488 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s33 offset:2492 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s33 offset:2496 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s33 offset:2500 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s33 offset:2504 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s33 offset:2508 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s33 offset:2512 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s33 offset:2516 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s33 offset:2520 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s33 offset:2524 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s33 offset:2528 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s33 offset:2280
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s33 offset:2284
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s33 offset:2288
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s33 offset:2292
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s33 offset:2296
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s33 offset:2300
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s33 offset:2304
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s33 offset:2308
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s33 offset:2312
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s33 offset:2316
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s33 offset:2320
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s33 offset:2324
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s33 offset:2328
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s33 offset:2332
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s33 offset:2336
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s33 offset:2340
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s33 offset:2344
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s33 offset:2348
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s33 offset:2352
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s33 offset:2356
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s33 offset:2360
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s33 offset:2364
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s33 offset:2368
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s33 offset:2372
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s33 offset:2376
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s33 offset:2380
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s33 offset:2384
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s33 offset:2388
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s33 offset:2392
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s33 offset:2396
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s33 offset:2400
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s33 offset:2404
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s33 offset:2408
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s33 offset:2412
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s33 offset:2416
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s33 offset:2420
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s33 offset:2424
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s33 offset:2428
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s33 offset:2432
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s33 offset:2436
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s33 offset:2440
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s33 offset:2444
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s33 offset:2448
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s33 offset:2452
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s33 offset:2456
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s33 offset:2460
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s33 offset:2464
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s33 offset:2468
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s33 offset:2472
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s33 offset:2476
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s33 offset:2480
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s33 offset:2484
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s33 offset:2488
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s33 offset:2492
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s33 offset:2496
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s33 offset:2500
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s33 offset:2504
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s33 offset:2508
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s33 offset:2512
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s33 offset:2516
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s33 offset:2520
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s33 offset:2524
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s33 offset:2528
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s33 offset:2532 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s33 offset:2536 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s33 offset:2540 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s33 offset:2544 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s33 offset:2548 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s33 offset:2552 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s33 offset:2556 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s33 offset:2560 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s33 offset:2564 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s33 offset:2568 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s33 offset:2572 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s33 offset:2576 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s33 offset:2580 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s33 offset:2584 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s33 offset:2588 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s33 offset:2592 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s33 offset:2596 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s33 offset:2600 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s33 offset:2604 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s33 offset:2608 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s33 offset:2612 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s33 offset:2616 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s33 offset:2620 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s33 offset:2624 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s33 offset:2628 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s33 offset:2632 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s33 offset:2532
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s33 offset:2536
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s33 offset:2540
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s33 offset:2544
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s33 offset:2548
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s33 offset:2552
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s33 offset:2556
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s33 offset:2560
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s33 offset:2564
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s33 offset:2568
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s33 offset:2572
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s33 offset:2576
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s33 offset:2580
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s33 offset:2584
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s33 offset:2588
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s33 offset:2592
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s33 offset:2596
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s33 offset:2600
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s33 offset:2604
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s33 offset:2608
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s33 offset:2612
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s33 offset:2616
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s33 offset:2620
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s33 offset:2624
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s33 offset:2628
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s33 offset:2632
; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 12 ; msbs: dst=0 src0=0 src1=3 src2=0
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s33 offset:2636 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s33 offset:2640 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s33 offset:2644 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s33 offset:2648 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s33 offset:2652 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s33 offset:2656 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s33 offset:2660 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s33 offset:2664 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s33 offset:2668 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s33 offset:2672 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s33 offset:2676 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s33 offset:2680 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s33 offset:2684 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s33 offset:2688 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s33 offset:2692 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s33 offset:2696 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s33 offset:2700 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s33 offset:2704 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s33 offset:2708 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s33 offset:2712 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s33 offset:2716 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s33 offset:2720 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s33 offset:2724 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s33 offset:2728 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s33 offset:2732 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s33 offset:2736 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s33 offset:2740 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s33 offset:2744 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s33 offset:2748 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s33 offset:2752 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s33 offset:2756 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s33 offset:2760 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s33 offset:2764 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s33 offset:2768 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s33 offset:2772 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s33 offset:2776 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s33 offset:2780 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s33 offset:2636
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s33 offset:2640
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s33 offset:2644
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s33 offset:2648
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s33 offset:2652
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s33 offset:2656
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s33 offset:2660
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s33 offset:2664
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s33 offset:2668
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s33 offset:2672
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s33 offset:2676
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s33 offset:2680
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s33 offset:2684
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s33 offset:2688
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s33 offset:2692
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s33 offset:2696
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s33 offset:2700
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s33 offset:2704
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s33 offset:2708
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s33 offset:2712
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s33 offset:2716
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s33 offset:2720
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s33 offset:2724
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s33 offset:2728
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s33 offset:2732
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s33 offset:2736
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s33 offset:2740
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s33 offset:2744
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s33 offset:2748
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s33 offset:2752
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s33 offset:2756
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s33 offset:2760
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s33 offset:2764
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s33 offset:2768
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s33 offset:2772
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s33 offset:2776
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s33 offset:2780
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s33 offset:2784 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s33 offset:2788 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s33 offset:2792 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s33 offset:2796 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s33 offset:2800 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s33 offset:2804 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s33 offset:2808 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s33 offset:2812 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s33 offset:2816 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s33 offset:2820 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s33 offset:2824 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s33 offset:2828 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s33 offset:2832 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s33 offset:2836 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s33 offset:2840 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s33 offset:2844 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s33 offset:2848 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s33 offset:2852 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s33 offset:2856 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s33 offset:2860 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s33 offset:2864 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s33 offset:2868 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s33 offset:2872 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s33 offset:2876 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s33 offset:2880 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s33 offset:2884 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s33 offset:2888 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s33 offset:2892 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s33 offset:2896 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s33 offset:2900 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s33 offset:2904 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s33 offset:2908 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s33 offset:2912 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s33 offset:2916 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s33 offset:2920 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s33 offset:2924 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s33 offset:2928 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s33 offset:2932 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s33 offset:2936 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s33 offset:2940 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s33 offset:2944 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s33 offset:2948 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s33 offset:2952 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s33 offset:2956 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s33 offset:2960 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s33 offset:2964 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s33 offset:2968 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s33 offset:2972 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s33 offset:2976 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s33 offset:2980 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s33 offset:2984 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s33 offset:2988 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s33 offset:2992 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s33 offset:2996 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s33 offset:3000 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s33 offset:3004 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s33 offset:3008 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s33 offset:3012 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s33 offset:3016 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s33 offset:3020 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s33 offset:3024 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s33 offset:3028 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s33 offset:3032 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s33 offset:2784
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s33 offset:2788
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s33 offset:2792
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s33 offset:2796
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s33 offset:2800
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s33 offset:2804
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s33 offset:2808
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s33 offset:2812
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s33 offset:2816
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s33 offset:2820
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s33 offset:2824
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s33 offset:2828
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s33 offset:2832
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s33 offset:2836
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s33 offset:2840
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s33 offset:2844
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s33 offset:2848
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s33 offset:2852
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s33 offset:2856
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s33 offset:2860
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s33 offset:2864
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s33 offset:2868
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s33 offset:2872
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s33 offset:2876
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s33 offset:2880
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s33 offset:2884
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s33 offset:2888
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s33 offset:2892
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s33 offset:2896
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s33 offset:2900
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s33 offset:2904
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s33 offset:2908
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s33 offset:2912
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s33 offset:2916
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s33 offset:2920
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s33 offset:2924
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s33 offset:2928
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s33 offset:2932
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s33 offset:2936
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s33 offset:2940
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s33 offset:2944
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s33 offset:2948
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s33 offset:2952
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s33 offset:2956
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s33 offset:2960
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s33 offset:2964
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s33 offset:2968
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s33 offset:2972
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s33 offset:2976
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s33 offset:2980
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s33 offset:2984
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s33 offset:2988
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s33 offset:2992
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s33 offset:2996
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s33 offset:3000
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s33 offset:3004
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s33 offset:3008
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s33 offset:3012
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s33 offset:3016
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s33 offset:3020
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s33 offset:3024
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s33 offset:3028
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s33 offset:3032
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s33 offset:3036 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s33 offset:3040 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s33 offset:3044 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s33 offset:3048 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s33 offset:3052 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s33 offset:3056 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s33 offset:3060 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s33 offset:3064 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s33 offset:3068 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s33 offset:3072 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s33 offset:3076 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s33 offset:3080 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s33 offset:3084 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s33 offset:3088 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s33 offset:3092 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s33 offset:3096 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s33 offset:3100 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s33 offset:3104 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s33 offset:3108 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s33 offset:3112 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s33 offset:3116 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s33 offset:3120 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s33 offset:3124 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s33 offset:3128 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s33 offset:3132 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s33 offset:3136 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s33 offset:3140 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s33 offset:3144 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s33 offset:3148 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s33 offset:3152 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s33 offset:3156 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s33 offset:3160 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s33 offset:3164 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s33 offset:3168 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s33 offset:3172 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s33 offset:3176 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s33 offset:3180 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s33 offset:3184 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s33 offset:3188 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s33 offset:3192 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s33 offset:3196 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s33 offset:3200 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s33 offset:3204 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s33 offset:3208 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s33 offset:3212 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s33 offset:3216 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s33 offset:3220 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s33 offset:3224 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s33 offset:3228 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s33 offset:3232 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s33 offset:3236 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s33 offset:3240 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s33 offset:3244 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s33 offset:3248 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s33 offset:3252 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s33 offset:3256 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s33 offset:3260 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s33 offset:3264 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s33 offset:3268 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s33 offset:3272 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s33 offset:3276 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s33 offset:3280 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s33 offset:3284 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s33 offset:3036
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s33 offset:3040
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s33 offset:3044
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s33 offset:3048
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s33 offset:3052
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s33 offset:3056
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s33 offset:3060
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s33 offset:3064
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s33 offset:3068
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s33 offset:3072
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s33 offset:3076
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s33 offset:3080
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s33 offset:3084
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s33 offset:3088
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s33 offset:3092
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s33 offset:3096
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s33 offset:3100
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s33 offset:3104
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s33 offset:3108
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s33 offset:3112
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s33 offset:3116
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s33 offset:3120
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s33 offset:3124
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s33 offset:3128
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s33 offset:3132
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s33 offset:3136
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s33 offset:3140
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s33 offset:3144
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s33 offset:3148
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s33 offset:3152
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s33 offset:3156
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s33 offset:3160
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s33 offset:3164
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s33 offset:3168
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s33 offset:3172
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s33 offset:3176
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s33 offset:3180
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s33 offset:3184
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s33 offset:3188
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s33 offset:3192
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s33 offset:3196
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s33 offset:3200
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s33 offset:3204
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s33 offset:3208
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s33 offset:3212
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s33 offset:3216
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s33 offset:3220
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s33 offset:3224
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s33 offset:3228
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s33 offset:3232
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s33 offset:3236
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s33 offset:3240
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s33 offset:3244
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s33 offset:3248
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s33 offset:3252
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s33 offset:3256
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s33 offset:3260
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s33 offset:3264
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s33 offset:3268
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s33 offset:3272
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s33 offset:3276
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s33 offset:3280
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s33 offset:3284
; GFX1250-DAGISEL-NEXT: s_clause 0x3e
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s33 offset:3288 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s33 offset:3292 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s33 offset:3296 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s33 offset:3300 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s33 offset:3304 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s33 offset:3308 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s33 offset:3312 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s33 offset:3316 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s33 offset:3320 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s33 offset:3324 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s33 offset:3328 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s33 offset:3332 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s33 offset:3336 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s33 offset:3340 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s33 offset:3344 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s33 offset:3348 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s33 offset:3352 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s33 offset:3356 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s33 offset:3360 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s33 offset:3364 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s33 offset:3368 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s33 offset:3372 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s33 offset:3376 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s33 offset:3380 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s33 offset:3384 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s33 offset:3388 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s33 offset:3392 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s33 offset:3396 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s33 offset:3400 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s33 offset:3404 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s33 offset:3408 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s33 offset:3412 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s33 offset:3416 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s33 offset:3420 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s33 offset:3424 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s33 offset:3428 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s33 offset:3432 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s33 offset:3436 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s33 offset:3440 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s33 offset:3444 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s33 offset:3448 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s33 offset:3452 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s33 offset:3456 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s33 offset:3460 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s33 offset:3464 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s33 offset:3468 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s33 offset:3472 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s33 offset:3476 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s33 offset:3480 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s33 offset:3484 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s33 offset:3488 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s33 offset:3492 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s33 offset:3496 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s33 offset:3500 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s33 offset:3504 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s33 offset:3508 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s33 offset:3512 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s33 offset:3516 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s33 offset:3520 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s33 offset:3524 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s33 offset:3528 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s33 offset:3532 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s33 offset:3536 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s33 offset:3288
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s33 offset:3292
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s33 offset:3296
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s33 offset:3300
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s33 offset:3304
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s33 offset:3308
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s33 offset:3312
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s33 offset:3316
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s33 offset:3320
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s33 offset:3324
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s33 offset:3328
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s33 offset:3332
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s33 offset:3336
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s33 offset:3340
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s33 offset:3344
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s33 offset:3348
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s33 offset:3352
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s33 offset:3356
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s33 offset:3360
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s33 offset:3364
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s33 offset:3368
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s33 offset:3372
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s33 offset:3376
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s33 offset:3380
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s33 offset:3384
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s33 offset:3388
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s33 offset:3392
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s33 offset:3396
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s33 offset:3400
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s33 offset:3404
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s33 offset:3408
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s33 offset:3412
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s33 offset:3416
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s33 offset:3420
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s33 offset:3424
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s33 offset:3428
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s33 offset:3432
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s33 offset:3436
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s33 offset:3440
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s33 offset:3444
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s33 offset:3448
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s33 offset:3452
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s33 offset:3456
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s33 offset:3460
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s33 offset:3464
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s33 offset:3468
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s33 offset:3472
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s33 offset:3476
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s33 offset:3480
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s33 offset:3484
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s33 offset:3488
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s33 offset:3492
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s33 offset:3496
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s33 offset:3500
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s33 offset:3504
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s33 offset:3508
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s33 offset:3512
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s33 offset:3516
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s33 offset:3520
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s33 offset:3524
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s33 offset:3528
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s33 offset:3532
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s33 offset:3536
; GFX1250-DAGISEL-NEXT: s_clause 0x1d
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s33 offset:3540 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s33 offset:3544 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s33 offset:3548 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s33 offset:3552 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s33 offset:3556 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s33 offset:3560 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s33 offset:3564 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s33 offset:3568 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s33 offset:3572 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s33 offset:3576 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s33 offset:3580 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s33 offset:3584 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s33 offset:3588 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s33 offset:3592 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s33 offset:3596 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s33 offset:3600 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s33 offset:3604 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s33 offset:3608 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s33 offset:3612 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s33 offset:3616 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s33 offset:3620 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s33 offset:3624 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s33 offset:3628 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s33 offset:3632 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s33 offset:3636 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s33 offset:3640 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s33 offset:3644 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s33 offset:3648 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s33 offset:3652 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s33 offset:3656 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s33 offset:3540
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s33 offset:3544
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s33 offset:3548
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s33 offset:3552
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s33 offset:3556
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s33 offset:3560
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s33 offset:3564
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s33 offset:3568
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s33 offset:3572
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s33 offset:3576
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s33 offset:3580
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s33 offset:3584
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s33 offset:3588
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s33 offset:3592
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s33 offset:3596
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s33 offset:3600
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s33 offset:3604
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s33 offset:3608
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s33 offset:3612
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s33 offset:3616
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s33 offset:3620
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s33 offset:3624
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s33 offset:3628
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s33 offset:3632
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s33 offset:3636
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s33 offset:3640
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s33 offset:3644
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s33 offset:3648
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s33 offset:3652
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s33 offset:3656
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-DAGISEL-NEXT: s_clause 0x2
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42, s33 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:164 scope:SCOPE_SE
-; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42, s33
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:164
+; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x2
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s0, 3
; GFX1250-DAGISEL-NEXT: s_mov_b64 s[0:1], callee at abs64
@@ -6920,7 +6920,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s30, 1
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s31, 2
; GFX1250-DAGISEL-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
-; GFX1250-DAGISEL-NEXT: flat_store_b32 v[40:41], v0 scope:SCOPE_SE
+; GFX1250-DAGISEL-NEXT: flat_store_b32 v[40:41], v0
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s31, v42, 2
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s30, v42, 1
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s4, v42, 0
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