[llvm] [AArch64][GlobalISel] Add codegen for simd fpcvt intrinsics (PR #157680)

[David Green via llvm-commits]

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@@ -7949,6 +7950,21 @@ multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm> {
   }
 }
 
+let mayRaiseFPException = 1, Uses = [FPCR] in
+multiclass SIMDFPTwoScalarFCVT<bit U, bit S, bits<5> opc, string asm,
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davemgreen wrote:

I think you can fold this into SIMDFPTwoScalar providing they pass null_frag.

https://github.com/llvm/llvm-project/pull/157680