[llvm] [TargetInstrInfo] Add target hook for InstrSchedModel latency. [NFCI] (PR #128925)

[Austin Kerbow via llvm-commits]

https://github.com/kerbowa updated https://github.com/llvm/llvm-project/pull/128925

>From 4058cecd6689df512213e0c8d61de620146438c2 Mon Sep 17 00:00:00 2001
From: Austin Kerbow <Austin.Kerbow at amd.com>
Date: Tue, 25 Feb 2025 19:37:46 -0800
Subject: [PATCH] [TargetInstrInfo] Add target hook for InstrSchedModel
 latency. [NFCI]

Allows targets to dynamically set latency values in the DAG builder.
This is useful in multi-pass schedulers like in the AMDGUP backend where
we may want to schedule a region multiple times with a different machine
model or tweaked latencies for a specific instruction type.
---
 llvm/include/llvm/CodeGen/TargetInstrInfo.h | 13 ++++++++++++
 llvm/include/llvm/CodeGen/TargetSchedule.h  |  3 +--
 llvm/lib/CodeGen/TargetInstrInfo.cpp        | 22 +++++++++++++++++++++
 llvm/lib/CodeGen/TargetSchedule.cpp         |  9 +++------
 4 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 087affcfd55ce..aaca45afa4857 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1849,6 +1849,14 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
                     const MachineInstr &DefMI, unsigned DefIdx,
                     const MachineInstr &UseMI, unsigned UseIdx) const;
 
+  /// Compute the latency of a register data dependence (DefIdx -> UseIdx)
+  /// using the InstrSchedModel.
+  virtual unsigned getOperandLatency(const TargetSchedModel &SchedModel,
+                                     const MachineInstr *DefMI,
+                                     unsigned DefIdx,
+                                     const MachineInstr *UseMI,
+                                     unsigned UseIdx) const;
+
   /// Compute the instruction latency of a given instruction.
   /// If the instruction has higher cost when predicated, it's returned via
   /// PredCost.
@@ -1856,6 +1864,11 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
                                    const MachineInstr &MI,
                                    unsigned *PredCost = nullptr) const;
 
+  /// Compute the instruction latency using the InstrSchedModel or the default
+  /// def latency when no model is available.
+  virtual unsigned getInstrLatency(const TargetSchedModel &TargetSchedModel,
+                                   const MachineInstr &MI) const;
+
   virtual unsigned getPredicationCost(const MachineInstr &MI) const;
 
   virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
diff --git a/llvm/include/llvm/CodeGen/TargetSchedule.h b/llvm/include/llvm/CodeGen/TargetSchedule.h
index 74f8ed5a18d33..b033ed65aed1a 100644
--- a/llvm/include/llvm/CodeGen/TargetSchedule.h
+++ b/llvm/include/llvm/CodeGen/TargetSchedule.h
@@ -44,8 +44,6 @@ class TargetSchedModel {
   // Resource units per cycle. Latency normalization factor.
   unsigned ResourceLCM = 0;
 
-  unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
-
   // EnableSchedModel and EnableSchedItins are used to control whether or not to
   // use the Target's {SchedMachineModel, InstrItins} for hardware infor based
   // Scheduling decisions. If both are enabled, as is the default, preference
@@ -203,6 +201,7 @@ class TargetSchedModel {
                                         bool UseDefaultDefLatency = true) const;
   LLVM_ABI unsigned computeInstrLatency(const MCInst &Inst) const;
   LLVM_ABI unsigned computeInstrLatency(unsigned Opcode) const;
+  LLVM_ABI unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
 
   /// Output dependency latency of a pair of defs of the same register.
   ///
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 0d7b128fc736e..cba99ee9efeb8 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1831,6 +1831,28 @@ unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
   return ItinData->getStageLatency(MI.getDesc().getSchedClass());
 }
 
+unsigned
+TargetInstrInfo::getInstrLatency(const TargetSchedModel &TargetSchedModel,
+                                 const MachineInstr &MI) const {
+  if (TargetSchedModel.hasInstrSchedModel()) {
+    const MCSchedClassDesc *SCDesc = TargetSchedModel.resolveSchedClass(&MI);
+    if (SCDesc->isValid())
+      return TargetSchedModel.computeInstrLatency(*SCDesc);
+  }
+
+  return defaultDefLatency(*TargetSchedModel.getMCSchedModel(), MI);
+}
+
+unsigned TargetInstrInfo::getOperandLatency(const TargetSchedModel &SchedModel,
+                                            const MachineInstr *DefMI,
+                                            unsigned DefOperIdx,
+                                            const MachineInstr *UseMI,
+                                            unsigned UseOperIdx) const {
+  // Keep the default hook minimal: delegate to the scheduling model so
+  // targets can override either side as needed.
+  return SchedModel.computeOperandLatency(DefMI, DefOperIdx, UseMI, UseOperIdx);
+}
+
 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
                                        const MachineInstr &DefMI,
                                        unsigned DefIdx) const {
diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp
index 7ae9e0e37bbab..960b6463165e7 100644
--- a/llvm/lib/CodeGen/TargetSchedule.cpp
+++ b/llvm/lib/CodeGen/TargetSchedule.cpp
@@ -259,12 +259,9 @@ TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
       (!hasInstrSchedModel() && !UseDefaultDefLatency))
     return TII->getInstrLatency(&InstrItins, *MI);
 
-  if (hasInstrSchedModel()) {
-    const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
-    if (SCDesc->isValid())
-      return computeInstrLatency(*SCDesc);
-  }
-  return TII->defaultDefLatency(SchedModel, *MI);
+  // This is used by targets that define an InstrSchedModel or want to use the
+  // default def latency.
+  return TII->getInstrLatency(*this, *MI);
 }
 
 unsigned TargetSchedModel::