[llvm] [PowerPC] Add intrinsic definition for load and store with Right Length Left-justified (PR #148873)

Lei Huang via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 9 12:00:19 PDT 2025


https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/148873

>From 094756499bdf64cb1fbf5536fb2049fe28906a9f Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 11 Jul 2025 20:10:23 +0000
Subject: [PATCH 01/10] add intrinsic def for ld/st with Right Length
 Left-justified

---
 llvm/include/llvm/IR/IntrinsicsPowerPC.td     | 25 ++++++++++++++++
 llvm/lib/Target/PowerPC/PPCInstrFuture.td     |  9 ++++++
 .../CodeGen/PowerPC/vsx-ldst-with-length.ll   | 29 +++++++++++++++++++
 3 files changed, 63 insertions(+)
 create mode 100644 llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll

diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index fb97230e0f8eb..1da5c43d09284 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1358,6 +1358,18 @@ def int_ppc_vsx_lxvll :
 def int_ppc_vsx_lxvp :
     DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty],
                           [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvrl :
+    DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_ptr_ty, llvm_i64_ty],
+                          [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvrll :
+    DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_ptr_ty, llvm_i64_ty],
+                          [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvprl :
+    DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty, llvm_i64_ty],
+                          [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvprll :
+    DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty, llvm_i64_ty],
+                          [IntrReadMem, IntrArgMemOnly]>;
 
 // Vector store.
 def int_ppc_vsx_stxvw4x : Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
@@ -1377,6 +1389,19 @@ def int_ppc_vsx_stxvll :
 def int_ppc_vsx_stxvp :
       Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty], [IntrWriteMem,
       IntrArgMemOnly]>;
+def int_ppc_vsx_stxvrl :
+      Intrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i64_ty],
+      [IntrWriteMem, IntrArgMemOnly]>;
+def int_ppc_vsx_stxvrll :
+      Intrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i64_ty],
+      [IntrWriteMem, IntrArgMemOnly]>;
+def int_ppc_vsx_stxvprl :
+      Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem,
+      IntrArgMemOnly]>;
+def int_ppc_vsx_stxvprll :
+      Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem,
+      IntrArgMemOnly]>;
+
 // Vector and scalar maximum.
 def int_ppc_vsx_xvmaxdp : PowerPC_VSX_Vec_DDD_Intrinsic<"xvmaxdp">;
 def int_ppc_vsx_xvmaxsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvmaxsp">;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index a12dfae2a0d7f..3e75dbbe70e05 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -192,3 +192,12 @@ let Predicates = [HasVSX, IsISAFuture] in {
       : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
                       "vucmprlh $VRT, $VRA, $VRB", []>;
 }
+
+def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
+def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
+def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
+def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
+/*
+def : Pat<(int_ppc_vsx_stxvrl v256i1:$XT, addr:$RA, i64:$RB),
+          (STXVRL $XT, $RA, $RB)>;
+*/
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
new file mode 100644
index 0000000000000..d55e27697804f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
+; RUN:   FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
+; RUN:   FileCheck %s
+
+define <4 x i32> @testLXVRL(ptr %a, i64 %b) {
+; CHECK-LABEL: testLXVRL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvrl v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrl(ptr %a, i64 %b)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.vsx.lxvrl(ptr, i64)
+
+define <4 x i32> @testLXVRLL(ptr %a, i64 %b) {
+; CHECK-LABEL: testLXVRLL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvrll v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrll(ptr %a, i64 %b)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)

>From 2286d3db73a3912649ef3d3b8c177982e8ff3b03 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 11 Jul 2025 20:38:19 +0000
Subject: [PATCH 02/10] add ld tests

---
 .../CodeGen/PowerPC/vsx-ldst-with-length.ll   | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index d55e27697804f..aa32be404960b 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -27,3 +27,26 @@ entry:
   ret <4 x i32> %0
 }
 declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
+
+define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
+; CHECK-LABEL: testLXVPRL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvprl vsp34, r4, r5
+; CHECK:         blr
+entry:
+  %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
+  ret <256 x i1> %0
+}
+declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
+
+define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
+; CHECK-LABEL: testLXVPRLL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvprll vsp34, r4, r5
+; CHECK:         blr
+entry:
+  %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
+  ret <256 x i1> %0
+}
+declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
+

>From f9e0633df45a6ef38a052efe7fad41353a950a8b Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 11 Jul 2025 21:22:29 +0000
Subject: [PATCH 03/10] add stxvprl[l]

---
 llvm/lib/Target/PowerPC/PPCInstrFuture.td     | 13 ++++++++---
 .../CodeGen/PowerPC/vsx-ldst-with-length.ll   | 22 ++++++++++++++++++-
 2 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 3e75dbbe70e05..f3ac88dea35ea 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -193,11 +193,18 @@ let Predicates = [HasVSX, IsISAFuture] in {
                       "vucmprlh $VRT, $VRA, $VRB", []>;
 }
 
+// Load VSX Vector with Right Length Left-justified.
 def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
 def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
 def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
 def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
-/*
-def : Pat<(int_ppc_vsx_stxvrl v256i1:$XT, addr:$RA, i64:$RB),
+
+// Store VSX Vector with Right Length Left-justified.
+def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB),
           (STXVRL $XT, $RA, $RB)>;
-*/
+def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB),
+          (STXVRLL $XT, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprl v256i1:$XT, addr:$RA, i64:$RB),
+          (STXVPRL $XT, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprll v256i1:$XT, addr:$RA, i64:$RB),
+          (STXVPRLL $XT, $RA, $RB)>;
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index aa32be404960b..0fc9508fb9b10 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
 ; RUN:   FileCheck %s
@@ -50,3 +49,24 @@ entry:
 }
 declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
 
+define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
+; CHECK:         blr
+entry:
+  tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
+  ret void
+}
+declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
+
+define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRLL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
+; CHECK:         blr
+entry:
+  tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
+  ret void
+}
+declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)

>From 11f73c21a3852fe326f05376c746afb52c55f250 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 11 Jul 2025 21:39:25 +0000
Subject: [PATCH 04/10] add stxvprl[l]

---
 llvm/lib/Target/PowerPC/PPCInstrFuture.td     |  8 +++---
 .../CodeGen/PowerPC/vsx-ldst-with-length.ll   | 28 +++++++++++++++++++
 2 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index f3ac88dea35ea..033d53e60b05f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -204,7 +204,7 @@ def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB),
           (STXVRL $XT, $RA, $RB)>;
 def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB),
           (STXVRLL $XT, $RA, $RB)>;
-def : Pat<(int_ppc_vsx_stxvprl v256i1:$XT, addr:$RA, i64:$RB),
-          (STXVPRL $XT, $RA, $RB)>;
-def : Pat<(int_ppc_vsx_stxvprll v256i1:$XT, addr:$RA, i64:$RB),
-          (STXVPRLL $XT, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB),
+          (STXVPRL $XTp, $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB),
+          (STXVPRLL $XTp, $RA, $RB)>;
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index 0fc9508fb9b10..c1bbf64e5b09b 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -70,3 +70,31 @@ entry:
   ret void
 }
 declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
+
+define void @testSTXVPRL(ptr %v, ptr %vp, i64 %len) {
+; CHECK-LABEL: testSTXVPRL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxv v2
+; CHECK-NEXT:    lxv v3
+; CHECK-NEXT:    stxvprl vsp34, r4, r5
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <256 x i1>, ptr %v, align 32
+  tail call void @llvm.ppc.vsx.stxvprl(<256 x i1> %0, ptr %vp, i64 %len)
+  ret void
+}
+declare void @llvm.ppc.vsx.stxvprl(<256 x i1>, ptr, i64)
+
+define void @testSTXVPRLL(ptr %v, ptr %vp, i64 %len) {
+; CHECK-LABEL: testSTXVPRLL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxv v2
+; CHECK-NEXT:    lxv v3
+; CHECK-NEXT:    stxvprll vsp34, r4, r5
+; CHECK-NEXT:    blr
+entry:
+  %0 = load <256 x i1>, ptr %v, align 32
+  tail call void @llvm.ppc.vsx.stxvprll(<256 x i1> %0, ptr %vp, i64 %len)
+  ret void
+}
+declare void @llvm.ppc.vsx.stxvprll(<256 x i1>, ptr, i64)

>From 89e2ed20cdb840790095e3be78d03f0347c569c7 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 15 Jul 2025 15:40:59 +0000
Subject: [PATCH 05/10] add support and test for v2i64

---
 llvm/lib/Target/PowerPC/PPCInstrFuture.td     | 27 +++---
 .../CodeGen/PowerPC/vsx-ldst-with-length.ll   | 90 ++++++++++++++-----
 2 files changed, 86 insertions(+), 31 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 033d53e60b05f..a4df6551aaff1 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -193,17 +193,22 @@ let Predicates = [HasVSX, IsISAFuture] in {
                       "vucmprlh $VRT, $VRA, $VRB", []>;
 }
 
-// Load VSX Vector with Right Length Left-justified.
-def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
-def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
-def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
-def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
-
-// Store VSX Vector with Right Length Left-justified.
-def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB),
-          (STXVRL $XT, $RA, $RB)>;
-def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB),
-          (STXVRLL $XT, $RA, $RB)>;
+// Load/Store VSX Vector with Right Length Left-justified.
+// foreach Ty = [v4i32, v2i64, v128i1] in {
+foreach Ty = [v4i32, v2i64] in {
+  def : Pat<(Ty (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)),
+            (LXVRL memr:$RA, g8rc:$RB)>;
+  def : Pat<(Ty (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)),
+            (LXVRLL $RA, $RB)>;
+  def : Pat<(int_ppc_vsx_stxvrl Ty:$XT, addr:$RA, i64:$RB),
+            (STXVRL $XT, $RA, $RB)>;
+  def : Pat<(int_ppc_vsx_stxvrll Ty:$XT, addr:$RA, i64:$RB),
+            (STXVRLL $XT, $RA, $RB)>;
+}
+
+// Load/Store VSX Vector pair with Right Length Left-justified.
+def : Pat<(v256i1(int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
+def : Pat<(v256i1(int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
 def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB),
           (STXVPRL $XTp, $RA, $RB)>;
 def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB),
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index c1bbf64e5b09b..2cbaf3c548d28 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -5,6 +5,8 @@
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
 ; RUN:   FileCheck %s
 
+; Test for load/store to/from v4i32.
+
 define <4 x i32> @testLXVRL(ptr %a, i64 %b) {
 ; CHECK-LABEL: testLXVRL:
 ; CHECK:       # %bb.0: # %entry
@@ -27,49 +29,97 @@ entry:
 }
 declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
 
-define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
-; CHECK-LABEL: testLXVPRL:
+define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRL:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvprl vsp34, r4, r5
+; CHECK-NEXT:    stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
 ; CHECK:         blr
 entry:
-  %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
-  ret <256 x i1> %0
+  tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
+  ret void
 }
-declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
+declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
 
-define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
-; CHECK-LABEL: testLXVPRLL:
+define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRLL:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvprll vsp34, r4, r5
+; CHECK-NEXT:    stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
 ; CHECK:         blr
 entry:
-  %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
-  ret <256 x i1> %0
+  tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
+  ret void
 }
-declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
+declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
 
-define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
-; CHECK-LABEL: testSTXVRL:
+; Test for load/store to/from v2i64.
+
+define <2 x i64> @testLXVRL2(ptr %a, i64 %b) {
+; CHECK-LABEL: testLXVRL2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvrl v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr %a, i64 %b)
+  ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr, i64)
+
+define <2 x i64> @testLXVRLL2(ptr %a, i64 %b) {
+; CHECK-LABEL: testLXVRLL2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvrll v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr %a, i64 %b)
+  ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr, i64)
+
+define void @testSTXVRL2(<2 x i64> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRL2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
 ; CHECK:         blr
 entry:
-  tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
+  tail call void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64> %a, ptr %b, i64 %c)
   ret void
 }
-declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
+declare void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64>, ptr, i64)
 
-define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
-; CHECK-LABEL: testSTXVRLL:
+define void @testSTXVRLL2(<2 x i64> %a, ptr %b, i64 %c) {
+; CHECK-LABEL: testSTXVRLL2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
 ; CHECK:         blr
 entry:
-  tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
+  tail call void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64> %a, ptr %b, i64 %c)
   ret void
 }
-declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
+declare void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64>, ptr, i64)
+
+; Test for load/store vectore pair.
+
+define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
+; CHECK-LABEL: testLXVPRL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvprl vsp34, r4, r5
+; CHECK:         blr
+entry:
+  %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
+  ret <256 x i1> %0
+}
+declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
+
+define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
+; CHECK-LABEL: testLXVPRLL:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvprll vsp34, r4, r5
+; CHECK:         blr
+entry:
+  %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
+  ret <256 x i1> %0
+}
+declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
 
 define void @testSTXVPRL(ptr %v, ptr %vp, i64 %len) {
 ; CHECK-LABEL: testSTXVPRL:

>From 5049230a766e7e7e86f3e73e42a6f9c9e48a3f65 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 15 Jul 2025 17:56:45 +0000
Subject: [PATCH 06/10] remove comments

---
 llvm/lib/Target/PowerPC/PPCInstrFuture.td | 1 -
 1 file changed, 1 deletion(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index a4df6551aaff1..ad5ef1e5f488f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -194,7 +194,6 @@ let Predicates = [HasVSX, IsISAFuture] in {
 }
 
 // Load/Store VSX Vector with Right Length Left-justified.
-// foreach Ty = [v4i32, v2i64, v128i1] in {
 foreach Ty = [v4i32, v2i64] in {
   def : Pat<(Ty (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)),
             (LXVRL memr:$RA, g8rc:$RB)>;

>From 79ce304918d68789ed965df54c8416bbb32549f9 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 5 Sep 2025 12:17:17 -0400
Subject: [PATCH 07/10] Update llvm/lib/Target/PowerPC/PPCInstrFuture.td to
 remove types from pattern

---
 llvm/lib/Target/PowerPC/PPCInstrFuture.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index ad5ef1e5f488f..055a397f1e191 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -196,7 +196,7 @@ let Predicates = [HasVSX, IsISAFuture] in {
 // Load/Store VSX Vector with Right Length Left-justified.
 foreach Ty = [v4i32, v2i64] in {
   def : Pat<(Ty (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)),
-            (LXVRL memr:$RA, g8rc:$RB)>;
+            (LXVRL $RA, $RB)>;
   def : Pat<(Ty (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)),
             (LXVRLL $RA, $RB)>;
   def : Pat<(int_ppc_vsx_stxvrl Ty:$XT, addr:$RA, i64:$RB),

>From 32f77b8b7e044e9f898aeaf2a9753d065b0850c7 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 5 Sep 2025 12:19:25 -0500
Subject: [PATCH 08/10] update to use anonymous pattern matching

---
 llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index 2cbaf3c548d28..48e554b560cb0 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -32,7 +32,7 @@ declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
 define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
 ; CHECK-LABEL: testSTXVRL:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
+; CHECK-NEXT:    stxvrl v2, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK:         blr
 entry:
   tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
@@ -43,7 +43,7 @@ declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
 define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
 ; CHECK-LABEL: testSTXVRLL:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
+; CHECK-NEXT:    stxvrll v2, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK:         blr
 entry:
   tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
@@ -78,7 +78,7 @@ declare <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr, i64)
 define void @testSTXVRL2(<2 x i64> %a, ptr %b, i64 %c) {
 ; CHECK-LABEL: testSTXVRL2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
+; CHECK-NEXT:    stxvrl v2, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK:         blr
 entry:
   tail call void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64> %a, ptr %b, i64 %c)
@@ -89,7 +89,7 @@ declare void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64>, ptr, i64)
 define void @testSTXVRLL2(<2 x i64> %a, ptr %b, i64 %c) {
 ; CHECK-LABEL: testSTXVRLL2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
+; CHECK-NEXT:    stxvrll v2, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK:         blr
 entry:
   tail call void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64> %a, ptr %b, i64 %c)

>From aa98a11c47daf01a3b5b6e77a63100be0cdb7fa5 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 5 Sep 2025 12:26:32 -0500
Subject: [PATCH 09/10] update test checks with update_llc_test_checks.py

---
 .../CodeGen/PowerPC/vsx-ldst-with-length.ll   | 103 +++++++++++++++---
 1 file changed, 88 insertions(+), 15 deletions(-)

diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index 48e554b560cb0..c52e8a217e38b 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -1,9 +1,10 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
 ; RUN:   FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
-; RUN:   FileCheck %s
+; RUN:   FileCheck %s --check-prefix=AIX
 
 ; Test for load/store to/from v4i32.
 
@@ -12,6 +13,11 @@ define <4 x i32> @testLXVRL(ptr %a, i64 %b) {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxvrl v2, r3, r4
 ; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testLXVRL:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    lxvrl v2, r3, r4
+; AIX-NEXT:    blr
 entry:
   %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrl(ptr %a, i64 %b)
   ret <4 x i32> %0
@@ -23,6 +29,11 @@ define <4 x i32> @testLXVRLL(ptr %a, i64 %b) {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxvrll v2, r3, r4
 ; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testLXVRLL:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    lxvrll v2, r3, r4
+; AIX-NEXT:    blr
 entry:
   %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvrll(ptr %a, i64 %b)
   ret <4 x i32> %0
@@ -32,8 +43,13 @@ declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
 define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
 ; CHECK-LABEL: testSTXVRL:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrl v2, r{{[0-9]+}}, r{{[0-9]+}}
-; CHECK:         blr
+; CHECK-NEXT:    stxvrl v2, r5, r6
+; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testSTXVRL:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    stxvrl v2, r3, r4
+; AIX-NEXT:    blr
 entry:
   tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
   ret void
@@ -43,8 +59,13 @@ declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
 define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
 ; CHECK-LABEL: testSTXVRLL:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrll v2, r{{[0-9]+}}, r{{[0-9]+}}
-; CHECK:         blr
+; CHECK-NEXT:    stxvrll v2, r5, r6
+; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testSTXVRLL:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    stxvrll v2, r3, r4
+; AIX-NEXT:    blr
 entry:
   tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
   ret void
@@ -58,6 +79,11 @@ define <2 x i64> @testLXVRL2(ptr %a, i64 %b) {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxvrl v2, r3, r4
 ; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testLXVRL2:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    lxvrl v2, r3, r4
+; AIX-NEXT:    blr
 entry:
   %0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr %a, i64 %b)
   ret <2 x i64> %0
@@ -69,6 +95,11 @@ define <2 x i64> @testLXVRLL2(ptr %a, i64 %b) {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxvrll v2, r3, r4
 ; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testLXVRLL2:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    lxvrll v2, r3, r4
+; AIX-NEXT:    blr
 entry:
   %0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr %a, i64 %b)
   ret <2 x i64> %0
@@ -78,8 +109,13 @@ declare <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr, i64)
 define void @testSTXVRL2(<2 x i64> %a, ptr %b, i64 %c) {
 ; CHECK-LABEL: testSTXVRL2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrl v2, r{{[0-9]+}}, r{{[0-9]+}}
-; CHECK:         blr
+; CHECK-NEXT:    stxvrl v2, r5, r6
+; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testSTXVRL2:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    stxvrl v2, r3, r4
+; AIX-NEXT:    blr
 entry:
   tail call void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64> %a, ptr %b, i64 %c)
   ret void
@@ -89,8 +125,13 @@ declare void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64>, ptr, i64)
 define void @testSTXVRLL2(<2 x i64> %a, ptr %b, i64 %c) {
 ; CHECK-LABEL: testSTXVRLL2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrll v2, r{{[0-9]+}}, r{{[0-9]+}}
-; CHECK:         blr
+; CHECK-NEXT:    stxvrll v2, r5, r6
+; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testSTXVRLL2:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    stxvrll v2, r3, r4
+; AIX-NEXT:    blr
 entry:
   tail call void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64> %a, ptr %b, i64 %c)
   ret void
@@ -103,7 +144,16 @@ define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
 ; CHECK-LABEL: testLXVPRL:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxvprl vsp34, r4, r5
-; CHECK:         blr
+; CHECK-NEXT:    stxv v2, 16(r3)
+; CHECK-NEXT:    stxv v3, 0(r3)
+; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testLXVPRL:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    lxvprl vsp34, r4, r5
+; AIX-NEXT:    stxv v3, 16(r3)
+; AIX-NEXT:    stxv v2, 0(r3)
+; AIX-NEXT:    blr
 entry:
   %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
   ret <256 x i1> %0
@@ -114,7 +164,16 @@ define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
 ; CHECK-LABEL: testLXVPRLL:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxvprll vsp34, r4, r5
-; CHECK:         blr
+; CHECK-NEXT:    stxv v2, 16(r3)
+; CHECK-NEXT:    stxv v3, 0(r3)
+; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testLXVPRLL:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    lxvprll vsp34, r4, r5
+; AIX-NEXT:    stxv v3, 16(r3)
+; AIX-NEXT:    stxv v2, 0(r3)
+; AIX-NEXT:    blr
 entry:
   %0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
   ret <256 x i1> %0
@@ -124,10 +183,17 @@ declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
 define void @testSTXVPRL(ptr %v, ptr %vp, i64 %len) {
 ; CHECK-LABEL: testSTXVPRL:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2
-; CHECK-NEXT:    lxv v3
+; CHECK-NEXT:    lxv v2, 16(r3)
+; CHECK-NEXT:    lxv v3, 0(r3)
 ; CHECK-NEXT:    stxvprl vsp34, r4, r5
 ; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testSTXVPRL:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    lxv v2, 0(r3)
+; AIX-NEXT:    lxv v3, 16(r3)
+; AIX-NEXT:    stxvprl vsp34, r4, r5
+; AIX-NEXT:    blr
 entry:
   %0 = load <256 x i1>, ptr %v, align 32
   tail call void @llvm.ppc.vsx.stxvprl(<256 x i1> %0, ptr %vp, i64 %len)
@@ -138,10 +204,17 @@ declare void @llvm.ppc.vsx.stxvprl(<256 x i1>, ptr, i64)
 define void @testSTXVPRLL(ptr %v, ptr %vp, i64 %len) {
 ; CHECK-LABEL: testSTXVPRLL:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv v2
-; CHECK-NEXT:    lxv v3
+; CHECK-NEXT:    lxv v2, 16(r3)
+; CHECK-NEXT:    lxv v3, 0(r3)
 ; CHECK-NEXT:    stxvprll vsp34, r4, r5
 ; CHECK-NEXT:    blr
+;
+; AIX-LABEL: testSTXVPRLL:
+; AIX:       # %bb.0: # %entry
+; AIX-NEXT:    lxv v2, 0(r3)
+; AIX-NEXT:    lxv v3, 16(r3)
+; AIX-NEXT:    stxvprll vsp34, r4, r5
+; AIX-NEXT:    blr
 entry:
   %0 = load <256 x i1>, ptr %v, align 32
   tail call void @llvm.ppc.vsx.stxvprll(<256 x i1> %0, ptr %vp, i64 %len)

>From b518ca029793e1ce1cf53bac3f2ea2f5f38bd44c Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 9 Sep 2025 14:00:00 -0500
Subject: [PATCH 10/10] udpate to only add support for v4i32 types

---
 llvm/include/llvm/IR/IntrinsicsPowerPC.td     |  8 +--
 llvm/lib/Target/PowerPC/PPCInstrFuture.td     | 30 ++++-----
 .../CodeGen/PowerPC/vsx-ldst-with-length.ll   | 66 -------------------
 3 files changed, 18 insertions(+), 86 deletions(-)

diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 1da5c43d09284..636e88898a55e 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1359,10 +1359,10 @@ def int_ppc_vsx_lxvp :
     DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty],
                           [IntrReadMem, IntrArgMemOnly]>;
 def int_ppc_vsx_lxvrl :
-    DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_ptr_ty, llvm_i64_ty],
+    DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty],
                           [IntrReadMem, IntrArgMemOnly]>;
 def int_ppc_vsx_lxvrll :
-    DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_ptr_ty, llvm_i64_ty],
+    DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty],
                           [IntrReadMem, IntrArgMemOnly]>;
 def int_ppc_vsx_lxvprl :
     DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_ptr_ty, llvm_i64_ty],
@@ -1390,10 +1390,10 @@ def int_ppc_vsx_stxvp :
       Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty], [IntrWriteMem,
       IntrArgMemOnly]>;
 def int_ppc_vsx_stxvrl :
-      Intrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i64_ty],
+      Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
       [IntrWriteMem, IntrArgMemOnly]>;
 def int_ppc_vsx_stxvrll :
-      Intrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i64_ty],
+      Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
       [IntrWriteMem, IntrArgMemOnly]>;
 def int_ppc_vsx_stxvprl :
       Intrinsic<[], [llvm_v256i1_ty, llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 055a397f1e191..338d579665ba4 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -193,22 +193,20 @@ let Predicates = [HasVSX, IsISAFuture] in {
                       "vucmprlh $VRT, $VRA, $VRB", []>;
 }
 
+//---------------------------- Anonymous Patterns ----------------------------//
+
 // Load/Store VSX Vector with Right Length Left-justified.
-foreach Ty = [v4i32, v2i64] in {
-  def : Pat<(Ty (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)),
-            (LXVRL $RA, $RB)>;
-  def : Pat<(Ty (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)),
-            (LXVRLL $RA, $RB)>;
-  def : Pat<(int_ppc_vsx_stxvrl Ty:$XT, addr:$RA, i64:$RB),
-            (STXVRL $XT, $RA, $RB)>;
-  def : Pat<(int_ppc_vsx_stxvrll Ty:$XT, addr:$RA, i64:$RB),
-            (STXVRLL $XT, $RA, $RB)>;
-}
+def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
+def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB), (STXVRL $XT, $RA,
+                                                                 $RB)>;
+def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB), (STXVRLL $XT, $RA,
+                                                                  $RB)>;
 
 // Load/Store VSX Vector pair with Right Length Left-justified.
-def : Pat<(v256i1(int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
-def : Pat<(v256i1(int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
-def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB),
-          (STXVPRL $XTp, $RA, $RB)>;
-def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB),
-          (STXVPRLL $XTp, $RA, $RB)>;
+def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
+def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRL $XTp,
+                                                                    $RA, $RB)>;
+def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB), (STXVPRLL $XTp,
+                                                                     $RA, $RB)>;
diff --git a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
index c52e8a217e38b..e7bc8fbca3202 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
@@ -72,72 +72,6 @@ entry:
 }
 declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
 
-; Test for load/store to/from v2i64.
-
-define <2 x i64> @testLXVRL2(ptr %a, i64 %b) {
-; CHECK-LABEL: testLXVRL2:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvrl v2, r3, r4
-; CHECK-NEXT:    blr
-;
-; AIX-LABEL: testLXVRL2:
-; AIX:       # %bb.0: # %entry
-; AIX-NEXT:    lxvrl v2, r3, r4
-; AIX-NEXT:    blr
-entry:
-  %0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr %a, i64 %b)
-  ret <2 x i64> %0
-}
-declare <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr, i64)
-
-define <2 x i64> @testLXVRLL2(ptr %a, i64 %b) {
-; CHECK-LABEL: testLXVRLL2:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvrll v2, r3, r4
-; CHECK-NEXT:    blr
-;
-; AIX-LABEL: testLXVRLL2:
-; AIX:       # %bb.0: # %entry
-; AIX-NEXT:    lxvrll v2, r3, r4
-; AIX-NEXT:    blr
-entry:
-  %0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr %a, i64 %b)
-  ret <2 x i64> %0
-}
-declare <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr, i64)
-
-define void @testSTXVRL2(<2 x i64> %a, ptr %b, i64 %c) {
-; CHECK-LABEL: testSTXVRL2:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrl v2, r5, r6
-; CHECK-NEXT:    blr
-;
-; AIX-LABEL: testSTXVRL2:
-; AIX:       # %bb.0: # %entry
-; AIX-NEXT:    stxvrl v2, r3, r4
-; AIX-NEXT:    blr
-entry:
-  tail call void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64> %a, ptr %b, i64 %c)
-  ret void
-}
-declare void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64>, ptr, i64)
-
-define void @testSTXVRLL2(<2 x i64> %a, ptr %b, i64 %c) {
-; CHECK-LABEL: testSTXVRLL2:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrll v2, r5, r6
-; CHECK-NEXT:    blr
-;
-; AIX-LABEL: testSTXVRLL2:
-; AIX:       # %bb.0: # %entry
-; AIX-NEXT:    stxvrll v2, r3, r4
-; AIX-NEXT:    blr
-entry:
-  tail call void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64> %a, ptr %b, i64 %c)
-  ret void
-}
-declare void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64>, ptr, i64)
-
 ; Test for load/store vectore pair.
 
 define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {



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