[llvm] [X86] Remove redundant code in X86 (PR #157687)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 9 08:28:28 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/157687
>From 1129f0ab4a4122065e5cd6c541d2de45f878cb9a Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 9 Sep 2025 11:08:21 -0400
Subject: [PATCH 1/2] [X86] Remove redundant code in X86
These transforms are now handled in DAGCombine, so enable hasAndNotCompare for the same cases for X86, and remove the platform-specific code that does the same thing.
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 52 +------------------------
1 file changed, 2 insertions(+), 50 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 08ae0d52d795e..f4df70206105e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3489,19 +3489,8 @@ bool X86TargetLowering::isMaskAndCmp0FoldingBeneficial(
}
bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
- EVT VT = Y.getValueType();
-
- if (VT.isVector())
- return false;
-
- if (!Subtarget.hasBMI())
- return false;
-
- // There are only 32-bit and 64-bit forms for 'andn'.
- if (VT != MVT::i32 && VT != MVT::i64)
- return false;
-
- return !isa<ConstantSDNode>(Y) || cast<ConstantSDNode>(Y)->isOpaque();
+ // Can use andn for any scalar integer.
+ return Y.getValueType().isScalarInteger();
}
bool X86TargetLowering::hasAndNot(SDValue Y) const {
@@ -3511,7 +3500,6 @@ bool X86TargetLowering::hasAndNot(SDValue Y) const {
return hasAndNotCompare(Y);
// Vector.
-
if (!Subtarget.hasSSE1() || VT.getSizeInBits() < 128)
return false;
@@ -56333,42 +56321,6 @@ static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG,
if (CC == ISD::SETNE || CC == ISD::SETEQ) {
if (OpVT.isScalarInteger()) {
- // cmpeq(or(X,Y),X) --> cmpeq(and(~X,Y),0)
- // cmpne(or(X,Y),X) --> cmpne(and(~X,Y),0)
- auto MatchOrCmpEq = [&](SDValue N0, SDValue N1) {
- if (N0.getOpcode() == ISD::OR && N0->hasOneUse()) {
- if (N0.getOperand(0) == N1)
- return DAG.getNode(ISD::AND, DL, OpVT, DAG.getNOT(DL, N1, OpVT),
- N0.getOperand(1));
- if (N0.getOperand(1) == N1)
- return DAG.getNode(ISD::AND, DL, OpVT, DAG.getNOT(DL, N1, OpVT),
- N0.getOperand(0));
- }
- return SDValue();
- };
- if (SDValue AndN = MatchOrCmpEq(LHS, RHS))
- return DAG.getSetCC(DL, VT, AndN, DAG.getConstant(0, DL, OpVT), CC);
- if (SDValue AndN = MatchOrCmpEq(RHS, LHS))
- return DAG.getSetCC(DL, VT, AndN, DAG.getConstant(0, DL, OpVT), CC);
-
- // cmpeq(and(X,Y),Y) --> cmpeq(and(~X,Y),0)
- // cmpne(and(X,Y),Y) --> cmpne(and(~X,Y),0)
- auto MatchAndCmpEq = [&](SDValue N0, SDValue N1) {
- if (N0.getOpcode() == ISD::AND && N0->hasOneUse()) {
- if (N0.getOperand(0) == N1)
- return DAG.getNode(ISD::AND, DL, OpVT, N1,
- DAG.getNOT(DL, N0.getOperand(1), OpVT));
- if (N0.getOperand(1) == N1)
- return DAG.getNode(ISD::AND, DL, OpVT, N1,
- DAG.getNOT(DL, N0.getOperand(0), OpVT));
- }
- return SDValue();
- };
- if (SDValue AndN = MatchAndCmpEq(LHS, RHS))
- return DAG.getSetCC(DL, VT, AndN, DAG.getConstant(0, DL, OpVT), CC);
- if (SDValue AndN = MatchAndCmpEq(RHS, LHS))
- return DAG.getSetCC(DL, VT, AndN, DAG.getConstant(0, DL, OpVT), CC);
-
// cmpeq(trunc(x),C) --> cmpeq(x,C)
// cmpne(trunc(x),C) --> cmpne(x,C)
// iff x upper bits are zero.
>From a453f8ba2b547fcee9751c1a76e9d8b98d990b3a Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 9 Sep 2025 11:28:17 -0400
Subject: [PATCH 2/2] Update X86ISelLowering.cpp
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f4df70206105e..d3752c7a84a3e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3496,8 +3496,9 @@ bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
bool X86TargetLowering::hasAndNot(SDValue Y) const {
EVT VT = Y.getValueType();
- if (!VT.isVector())
- return hasAndNotCompare(Y);
+ if (!VT.isVector()) {
+ return !isa<ConstantSDNode>(Y) || cast<ConstantSDNode>(Y)->isOpaque();
+ }
// Vector.
if (!Subtarget.hasSSE1() || VT.getSizeInBits() < 128)
More information about the llvm-commits
mailing list