[llvm] [AMDGPU] Identify vector idiom to unlock SROA (PR #156791)

[Yaxun Liu via llvm-commits]

yxsamliu wrote:

> https://reviews.llvm.org/D140493 related?

Thanks, yes, it's similar in spirit to D140493. Both aim to unblock SROA by reshaping memory idioms. But D140493 already showed that profitability and legality here are highly target-specific, and that trying to fit this into generic SROA/InstCombine causes difficulty and delay.

On AMDGPU, costs and safety depend on address spaces, proven alignment, how byte and small vectors legalize, and when it's safe to speculate loads (but not stores). This also needs a precise spot in our pipeline (after inlining, before infer-AS/SROA). Keeping it as an AMDGPU pass lets us tune behavior per subtarget and avoid cross-target regressions.

https://github.com/llvm/llvm-project/pull/156791