[llvm] 6ef4a7b - [RISCV] Exclude LPAD in machine outliner (#157220)

[via llvm-commits]

Author: Jesse Huang
Date: 2025-09-09T22:50:22+08:00
New Revision: 6ef4a7bf16d2e1f960237a635ef114dd6fc07b16

URL: https://github.com/llvm/llvm-project/commit/6ef4a7bf16d2e1f960237a635ef114dd6fc07b16
DIFF: https://github.com/llvm/llvm-project/commit/6ef4a7bf16d2e1f960237a635ef114dd6fc07b16.diff

LOG: [RISCV] Exclude LPAD in machine outliner (#157220)

After https://github.com/llvm/llvm-project/pull/139993, the
RISCVIndirectBranchTracking pass is also ran before the Machine Outliner
pass, this yield a possibility that the outliner could also outline the
LPAD instruction that should be placed at the target of an indirect
branch. This patch excludes LPAD instruction from the candidate of
machine outliner.

Added: 
    llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/lib/Target/RISCV/RISCVInstrPredicates.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index f2e6e8959a726..d0bb57a3eaa13 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3511,6 +3511,9 @@ RISCVInstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI,
       return outliner::InstrType::Illegal;
   }
 
+  if (isLPAD(MI))
+    return outliner::InstrType::Illegal;
+
   return outliner::InstrType::Legal;
 }
 

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
index 4abe62f4e874c..06309262f1b08 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
@@ -148,6 +148,14 @@ def isNonZeroLoadImmediate
                      CheckNot<CheckImmOperand<2, 0>>
                    ]>>>;
 
+def isLPAD
+    : TIIPredicate<"isLPAD",
+                   MCReturnStatement<CheckAll<[
+                     CheckOpcode<[AUIPC]>,
+                     CheckIsRegOperand<0>,
+                     CheckRegOperand<0, X0>,
+                   ]>>>;
+
 def ignoresVXRM
     : TIIPredicate<"ignoresVXRM",
                    MCOpcodeSwitchStatement<

diff  --git a/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll b/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll
new file mode 100644
index 0000000000000..a6e019981f26a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s
+; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp < %s | FileCheck %s
+
+define i16 @test1(i16 %x) #0 {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lpad 0
+; CHECK-NEXT:    tail OUTLINED_FUNCTION_0
+entry:
+  %y = add i16 5, %x
+  %z = mul i16 4, %y
+  ret i16 %z
+}
+
+define i16 @test2(i16 %x) #0 {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lpad 0
+; CHECK-NEXT:    tail OUTLINED_FUNCTION_0
+entry:
+  %y = add i16 5, %x
+  %z = mul i16 4, %y
+  ret i16 %z
+}
+
+define i16 @test3(i16 %x) #0 {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lpad 0
+; CHECK-NEXT:    tail OUTLINED_FUNCTION_0
+entry:
+  %y = add i16 5, %x
+  %z = mul i16 4, %y
+  ret i16 %z
+}
+
+define i16 @test4(i16 %x) #0 {
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lpad 0
+; CHECK-NEXT:    tail OUTLINED_FUNCTION_0
+entry:
+  %y = add i16 5, %x
+  %z = mul i16 4, %y
+  ret i16 %z
+}
+
+define i16 @main(i16 %x) #0 {
+; CHECK-LABEL: main:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lpad 0
+; CHECK-NEXT:    tail OUTLINED_FUNCTION_0
+entry:
+  %y = add i16 5, %x
+  %z = mul i16 4, %y
+  ret i16 %z
+}
+
+attributes #0 = { minsize }
+
+!llvm.module.flags = !{!0, !1}
+
+!0 = !{i32 8, !"cf-protection-branch", i32 1}
+!1 = !{i32 1, !"cf-branch-label-scheme", !"unlabeled"}