[llvm] [RISCV][RFC] Prevent folding ADD_LO into load/store if we can't fold all uses. (PR #155935)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 8 20:49:52 PDT 2025
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/155935
>From 7857192d44558bf0bd068d6412617b26ee0b8445 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 28 Aug 2025 14:15:37 -0700
Subject: [PATCH 1/3] [RISCV][RFC] Prevent folding ADD_LO into load/store if we
can't fold all uses.
If we don't fold all uses, we end up with an LUI that is used by
an ADDI and some loads/stores. This requires the LUI to write a
different register than the ADDI or the load/stores uses have to be
scheduled between the LUI and ADDI. It prevents macrofusion of the
LUI+ADDI on CPUs that support it. It prevents the use of
PseudoMovAddr which prevents the LUI+ADDI from being rematerializable.
This is based on a patch we have had in our downstream for a while
that we originally wrote because of macrofusion and rematerialization.
I no longer have any relevant performance or code size numbers for it.
Co-authored-by: Jesse Huang <jesse.huang at sifive.com>
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 75 +-
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 2 +
llvm/test/CodeGen/RISCV/bfloat-mem.ll | 10 +-
llvm/test/CodeGen/RISCV/byval.ll | 8 +-
.../test/CodeGen/RISCV/callee-saved-fpr32s.ll | 2388 +++++++------
.../test/CodeGen/RISCV/callee-saved-fpr64s.ll | 1458 ++++----
llvm/test/CodeGen/RISCV/callee-saved-gprs.ll | 2910 ++++++++--------
llvm/test/CodeGen/RISCV/double-mem.ll | 48 +-
llvm/test/CodeGen/RISCV/float-mem.ll | 20 +-
.../test/CodeGen/RISCV/fold-addi-loadstore.ll | 20 +-
.../global-merge-minsize-smalldata-nonzero.ll | 2 +-
.../global-merge-minsize-smalldata-zero.ll | 2 +-
.../CodeGen/RISCV/global-merge-minsize.ll | 2 +-
.../test/CodeGen/RISCV/global-merge-offset.ll | 14 +-
llvm/test/CodeGen/RISCV/global-merge.ll | 8 +-
llvm/test/CodeGen/RISCV/half-mem.ll | 40 +-
.../CodeGen/RISCV/hoist-global-addr-base.ll | 4 +-
llvm/test/CodeGen/RISCV/mem.ll | 10 +-
llvm/test/CodeGen/RISCV/mem64.ll | 10 +-
llvm/test/CodeGen/RISCV/push-pop-popret.ll | 2954 ++++++++---------
.../CodeGen/RISCV/qci-interrupt-attr-fpr.ll | 1352 ++++----
llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll | 2696 ++++++++-------
.../rvv/fixed-vectors-store-merge-crash.ll | 12 +-
llvm/test/CodeGen/RISCV/saverestore.ll | 48 +-
.../CodeGen/RISCV/xqccmp-callee-saved-gprs.ll | 1026 +++---
.../CodeGen/RISCV/xqccmp-push-pop-popret.ll | 2780 ++++++++--------
llvm/test/CodeGen/RISCV/xqcilsm-memset.ll | 28 +-
.../CodeGen/RISCV/zdinx-boundary-check.ll | 110 +-
.../CodeGen/RISCV/zext-with-load-is-free.ll | 8 +-
29 files changed, 8942 insertions(+), 9103 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index f9f35f66319b5..c5b68ccd1ba8d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2951,6 +2951,60 @@ static bool isWorthFoldingAdd(SDValue Add) {
return true;
}
+bool isRegImmLoadOrStore(SDNode *User, SDValue Add) {
+ // If the user is a load or store, then the offset is 0.
+ if (User->getOpcode() != ISD::LOAD && User->getOpcode() != ISD::STORE &&
+ User->getOpcode() != RISCVISD::LD_RV32 &&
+ User->getOpcode() != RISCVISD::SD_RV32 &&
+ User->getOpcode() != ISD::ATOMIC_LOAD &&
+ User->getOpcode() != ISD::ATOMIC_STORE)
+ return false;
+
+ // Don't allow stores of the value. It must be used as the address.
+ if (User->getOpcode() == ISD::STORE &&
+ cast<StoreSDNode>(User)->getValue() == Add)
+ return false;
+ if (User->getOpcode() == RISCVISD::SD_RV32 &&
+ (User->getOperand(0) == Add || User->getOperand(1) == Add))
+ return false;
+ if (User->getOpcode() == ISD::ATOMIC_STORE &&
+ cast<AtomicSDNode>(User)->getVal() == Add)
+ return false;
+
+ return true;
+}
+
+// To prevent SelectAddrRegImm from folding offsets that conflicts with the
+// fusion of PseudoMovAddr, check if the offset of every use of a given address
+// is within the alignment.
+bool RISCVDAGToDAGISel::areOffsetsWithinAlignment(SDValue Addr,
+ Align Alignment) {
+ assert(Addr->getOpcode() == RISCVISD::ADD_LO);
+ for (auto *User : Addr->users()) {
+ // If the user is a load or store, then the offset is 0 which is always
+ // within alignment.
+ if (isRegImmLoadOrStore(User, Addr))
+ continue;
+
+ if (CurDAG->isBaseWithConstantOffset(SDValue(User, 0))) {
+ int64_t CVal = cast<ConstantSDNode>(User->getOperand(1))->getSExtValue();
+ if (!isInt<12>(CVal) || Alignment <= CVal)
+ return false;
+
+ // Make sure all uses are foldable load/stores.
+ for (auto *AddUser : User->users())
+ if (!isRegImmLoadOrStore(AddUser, SDValue(User, 0)))
+ return false;
+
+ continue;
+ }
+
+ return false;
+ }
+
+ return true;
+}
+
bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
SDValue &Offset) {
if (SelectAddrFrameIndex(Addr, Base, Offset))
@@ -2960,9 +3014,21 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
MVT VT = Addr.getSimpleValueType();
if (Addr.getOpcode() == RISCVISD::ADD_LO) {
- Base = Addr.getOperand(0);
- Offset = Addr.getOperand(1);
- return true;
+ bool CanFold = true;
+ // Unconditionally fold if operand 1 is not a global address (e.g.
+ // externsymbol)
+ if (auto *GA = dyn_cast<GlobalAddressSDNode>(Addr.getOperand(1))) {
+ const DataLayout &DL = CurDAG->getDataLayout();
+ Align Alignment = commonAlignment(
+ GA->getGlobal()->getPointerAlignment(DL), GA->getOffset());
+ if (!areOffsetsWithinAlignment(Addr, Alignment))
+ CanFold = false;
+ }
+ if (CanFold) {
+ Base = Addr.getOperand(0);
+ Offset = Addr.getOperand(1);
+ return true;
+ }
}
if (CurDAG->isBaseWithConstantOffset(Addr)) {
@@ -2980,7 +3046,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
const DataLayout &DL = CurDAG->getDataLayout();
Align Alignment = commonAlignment(
GA->getGlobal()->getPointerAlignment(DL), GA->getOffset());
- if ((CVal == 0 || Alignment > CVal)) {
+ if ((CVal == 0 || Alignment > CVal) &&
+ areOffsetsWithinAlignment(Base, Alignment)) {
int64_t CombinedOffset = CVal + GA->getOffset();
Base = Base.getOperand(0);
Offset = CurDAG->getTargetGlobalAddress(
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index c329a4c6ec62e..89217e1487bbc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -45,6 +45,8 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
InlineAsm::ConstraintCode ConstraintID,
std::vector<SDValue> &OutOps) override;
+ bool areOffsetsWithinAlignment(SDValue Addr, Align Alignment);
+
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectAddrRegImm9(SDValue Addr, SDValue &Base, SDValue &Offset);
diff --git a/llvm/test/CodeGen/RISCV/bfloat-mem.ll b/llvm/test/CodeGen/RISCV/bfloat-mem.ll
index f9cf4e523b77d..cccbb04e6ae99 100644
--- a/llvm/test/CodeGen/RISCV/bfloat-mem.ll
+++ b/llvm/test/CodeGen/RISCV/bfloat-mem.ll
@@ -51,13 +51,13 @@ define bfloat @flh_fsh_global(bfloat %a, bfloat %b) nounwind {
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK-NEXT: lui a0, %hi(G)
+; CHECK-NEXT: addi a0, a0, %lo(G)
; CHECK-NEXT: fadd.s fa5, fa4, fa5
-; CHECK-NEXT: flh fa4, %lo(G)(a0)
; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: addi a1, a0, %lo(G)
-; CHECK-NEXT: fsh fa0, %lo(G)(a0)
-; CHECK-NEXT: flh fa5, 18(a1)
-; CHECK-NEXT: fsh fa0, 18(a1)
+; CHECK-NEXT: flh fa5, 0(a0)
+; CHECK-NEXT: fsh fa0, 0(a0)
+; CHECK-NEXT: flh fa5, 18(a0)
+; CHECK-NEXT: fsh fa0, 18(a0)
; CHECK-NEXT: ret
%1 = fadd bfloat %a, %b
%2 = load volatile bfloat, ptr @G
diff --git a/llvm/test/CodeGen/RISCV/byval.ll b/llvm/test/CodeGen/RISCV/byval.ll
index 9151f3b03e7c2..c5e48ee75e482 100644
--- a/llvm/test/CodeGen/RISCV/byval.ll
+++ b/llvm/test/CodeGen/RISCV/byval.ll
@@ -22,15 +22,15 @@ define void @caller() nounwind {
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, %hi(foo)
-; RV32I-NEXT: lw a1, %lo(foo)(a0)
-; RV32I-NEXT: sw a1, 12(sp)
; RV32I-NEXT: addi a0, a0, %lo(foo)
; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: sw a1, 24(sp)
; RV32I-NEXT: lw a1, 8(a0)
; RV32I-NEXT: sw a1, 20(sp)
-; RV32I-NEXT: lw a0, 4(a0)
-; RV32I-NEXT: sw a0, 16(sp)
+; RV32I-NEXT: lw a1, 4(a0)
+; RV32I-NEXT: sw a1, 16(sp)
+; RV32I-NEXT: lw a0, 0(a0)
+; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: addi a0, sp, 12
; RV32I-NEXT: call callee
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
index 337e9bc5845f9..2999a7e4981bc 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
@@ -28,281 +28,281 @@ define void @callee() nounwind {
; ILP32-LABEL: callee:
; ILP32: # %bb.0:
; ILP32-NEXT: lui a0, %hi(var)
-; ILP32-NEXT: flw fa5, %lo(var)(a0)
-; ILP32-NEXT: flw fa4, %lo(var+4)(a0)
-; ILP32-NEXT: flw fa3, %lo(var+8)(a0)
-; ILP32-NEXT: flw fa2, %lo(var+12)(a0)
-; ILP32-NEXT: addi a1, a0, %lo(var)
-; ILP32-NEXT: flw fa1, 16(a1)
-; ILP32-NEXT: flw fa0, 20(a1)
-; ILP32-NEXT: flw ft0, 24(a1)
-; ILP32-NEXT: flw ft1, 28(a1)
-; ILP32-NEXT: flw ft2, 32(a1)
-; ILP32-NEXT: flw ft3, 36(a1)
-; ILP32-NEXT: flw ft4, 40(a1)
-; ILP32-NEXT: flw ft5, 44(a1)
-; ILP32-NEXT: flw ft6, 48(a1)
-; ILP32-NEXT: flw ft7, 52(a1)
-; ILP32-NEXT: flw fa6, 56(a1)
-; ILP32-NEXT: flw fa7, 60(a1)
-; ILP32-NEXT: flw ft8, 64(a1)
-; ILP32-NEXT: flw ft9, 68(a1)
-; ILP32-NEXT: flw ft10, 72(a1)
-; ILP32-NEXT: flw ft11, 76(a1)
-; ILP32-NEXT: flw fs0, 80(a1)
-; ILP32-NEXT: flw fs1, 84(a1)
-; ILP32-NEXT: flw fs2, 88(a1)
-; ILP32-NEXT: flw fs3, 92(a1)
-; ILP32-NEXT: flw fs4, 112(a1)
-; ILP32-NEXT: flw fs5, 116(a1)
-; ILP32-NEXT: flw fs6, 120(a1)
-; ILP32-NEXT: flw fs7, 124(a1)
-; ILP32-NEXT: flw fs8, 96(a1)
-; ILP32-NEXT: flw fs9, 100(a1)
-; ILP32-NEXT: flw fs10, 104(a1)
-; ILP32-NEXT: flw fs11, 108(a1)
-; ILP32-NEXT: fsw fs7, 124(a1)
-; ILP32-NEXT: fsw fs6, 120(a1)
-; ILP32-NEXT: fsw fs5, 116(a1)
-; ILP32-NEXT: fsw fs4, 112(a1)
-; ILP32-NEXT: fsw fs11, 108(a1)
-; ILP32-NEXT: fsw fs10, 104(a1)
-; ILP32-NEXT: fsw fs9, 100(a1)
-; ILP32-NEXT: fsw fs8, 96(a1)
-; ILP32-NEXT: fsw fs3, 92(a1)
-; ILP32-NEXT: fsw fs2, 88(a1)
-; ILP32-NEXT: fsw fs1, 84(a1)
-; ILP32-NEXT: fsw fs0, 80(a1)
-; ILP32-NEXT: fsw ft11, 76(a1)
-; ILP32-NEXT: fsw ft10, 72(a1)
-; ILP32-NEXT: fsw ft9, 68(a1)
-; ILP32-NEXT: fsw ft8, 64(a1)
-; ILP32-NEXT: fsw fa7, 60(a1)
-; ILP32-NEXT: fsw fa6, 56(a1)
-; ILP32-NEXT: fsw ft7, 52(a1)
-; ILP32-NEXT: fsw ft6, 48(a1)
-; ILP32-NEXT: fsw ft5, 44(a1)
-; ILP32-NEXT: fsw ft4, 40(a1)
-; ILP32-NEXT: fsw ft3, 36(a1)
-; ILP32-NEXT: fsw ft2, 32(a1)
-; ILP32-NEXT: fsw ft1, 28(a1)
-; ILP32-NEXT: fsw ft0, 24(a1)
-; ILP32-NEXT: fsw fa0, 20(a1)
-; ILP32-NEXT: fsw fa1, 16(a1)
-; ILP32-NEXT: fsw fa2, %lo(var+12)(a0)
-; ILP32-NEXT: fsw fa3, %lo(var+8)(a0)
-; ILP32-NEXT: fsw fa4, %lo(var+4)(a0)
-; ILP32-NEXT: fsw fa5, %lo(var)(a0)
+; ILP32-NEXT: addi a0, a0, %lo(var)
+; ILP32-NEXT: flw fa5, 0(a0)
+; ILP32-NEXT: flw fa4, 4(a0)
+; ILP32-NEXT: flw fa3, 8(a0)
+; ILP32-NEXT: flw fa2, 12(a0)
+; ILP32-NEXT: flw fa1, 16(a0)
+; ILP32-NEXT: flw fa0, 20(a0)
+; ILP32-NEXT: flw ft0, 24(a0)
+; ILP32-NEXT: flw ft1, 28(a0)
+; ILP32-NEXT: flw ft2, 32(a0)
+; ILP32-NEXT: flw ft3, 36(a0)
+; ILP32-NEXT: flw ft4, 40(a0)
+; ILP32-NEXT: flw ft5, 44(a0)
+; ILP32-NEXT: flw ft6, 48(a0)
+; ILP32-NEXT: flw ft7, 52(a0)
+; ILP32-NEXT: flw fa6, 56(a0)
+; ILP32-NEXT: flw fa7, 60(a0)
+; ILP32-NEXT: flw ft8, 64(a0)
+; ILP32-NEXT: flw ft9, 68(a0)
+; ILP32-NEXT: flw ft10, 72(a0)
+; ILP32-NEXT: flw ft11, 76(a0)
+; ILP32-NEXT: flw fs0, 80(a0)
+; ILP32-NEXT: flw fs1, 84(a0)
+; ILP32-NEXT: flw fs2, 88(a0)
+; ILP32-NEXT: flw fs3, 92(a0)
+; ILP32-NEXT: flw fs4, 112(a0)
+; ILP32-NEXT: flw fs5, 116(a0)
+; ILP32-NEXT: flw fs6, 120(a0)
+; ILP32-NEXT: flw fs7, 124(a0)
+; ILP32-NEXT: flw fs8, 96(a0)
+; ILP32-NEXT: flw fs9, 100(a0)
+; ILP32-NEXT: flw fs10, 104(a0)
+; ILP32-NEXT: flw fs11, 108(a0)
+; ILP32-NEXT: fsw fs7, 124(a0)
+; ILP32-NEXT: fsw fs6, 120(a0)
+; ILP32-NEXT: fsw fs5, 116(a0)
+; ILP32-NEXT: fsw fs4, 112(a0)
+; ILP32-NEXT: fsw fs11, 108(a0)
+; ILP32-NEXT: fsw fs10, 104(a0)
+; ILP32-NEXT: fsw fs9, 100(a0)
+; ILP32-NEXT: fsw fs8, 96(a0)
+; ILP32-NEXT: fsw fs3, 92(a0)
+; ILP32-NEXT: fsw fs2, 88(a0)
+; ILP32-NEXT: fsw fs1, 84(a0)
+; ILP32-NEXT: fsw fs0, 80(a0)
+; ILP32-NEXT: fsw ft11, 76(a0)
+; ILP32-NEXT: fsw ft10, 72(a0)
+; ILP32-NEXT: fsw ft9, 68(a0)
+; ILP32-NEXT: fsw ft8, 64(a0)
+; ILP32-NEXT: fsw fa7, 60(a0)
+; ILP32-NEXT: fsw fa6, 56(a0)
+; ILP32-NEXT: fsw ft7, 52(a0)
+; ILP32-NEXT: fsw ft6, 48(a0)
+; ILP32-NEXT: fsw ft5, 44(a0)
+; ILP32-NEXT: fsw ft4, 40(a0)
+; ILP32-NEXT: fsw ft3, 36(a0)
+; ILP32-NEXT: fsw ft2, 32(a0)
+; ILP32-NEXT: fsw ft1, 28(a0)
+; ILP32-NEXT: fsw ft0, 24(a0)
+; ILP32-NEXT: fsw fa0, 20(a0)
+; ILP32-NEXT: fsw fa1, 16(a0)
+; ILP32-NEXT: fsw fa2, 12(a0)
+; ILP32-NEXT: fsw fa3, 8(a0)
+; ILP32-NEXT: fsw fa4, 4(a0)
+; ILP32-NEXT: fsw fa5, 0(a0)
; ILP32-NEXT: ret
;
; ILP32E-LABEL: callee:
; ILP32E: # %bb.0:
; ILP32E-NEXT: lui a0, %hi(var)
-; ILP32E-NEXT: flw fa5, %lo(var)(a0)
-; ILP32E-NEXT: flw fa4, %lo(var+4)(a0)
-; ILP32E-NEXT: flw fa3, %lo(var+8)(a0)
-; ILP32E-NEXT: flw fa2, %lo(var+12)(a0)
-; ILP32E-NEXT: addi a1, a0, %lo(var)
-; ILP32E-NEXT: flw fa1, 16(a1)
-; ILP32E-NEXT: flw fa0, 20(a1)
-; ILP32E-NEXT: flw ft0, 24(a1)
-; ILP32E-NEXT: flw ft1, 28(a1)
-; ILP32E-NEXT: flw ft2, 32(a1)
-; ILP32E-NEXT: flw ft3, 36(a1)
-; ILP32E-NEXT: flw ft4, 40(a1)
-; ILP32E-NEXT: flw ft5, 44(a1)
-; ILP32E-NEXT: flw ft6, 48(a1)
-; ILP32E-NEXT: flw ft7, 52(a1)
-; ILP32E-NEXT: flw fa6, 56(a1)
-; ILP32E-NEXT: flw fa7, 60(a1)
-; ILP32E-NEXT: flw ft8, 64(a1)
-; ILP32E-NEXT: flw ft9, 68(a1)
-; ILP32E-NEXT: flw ft10, 72(a1)
-; ILP32E-NEXT: flw ft11, 76(a1)
-; ILP32E-NEXT: flw fs0, 80(a1)
-; ILP32E-NEXT: flw fs1, 84(a1)
-; ILP32E-NEXT: flw fs2, 88(a1)
-; ILP32E-NEXT: flw fs3, 92(a1)
-; ILP32E-NEXT: flw fs4, 112(a1)
-; ILP32E-NEXT: flw fs5, 116(a1)
-; ILP32E-NEXT: flw fs6, 120(a1)
-; ILP32E-NEXT: flw fs7, 124(a1)
-; ILP32E-NEXT: flw fs8, 96(a1)
-; ILP32E-NEXT: flw fs9, 100(a1)
-; ILP32E-NEXT: flw fs10, 104(a1)
-; ILP32E-NEXT: flw fs11, 108(a1)
-; ILP32E-NEXT: fsw fs7, 124(a1)
-; ILP32E-NEXT: fsw fs6, 120(a1)
-; ILP32E-NEXT: fsw fs5, 116(a1)
-; ILP32E-NEXT: fsw fs4, 112(a1)
-; ILP32E-NEXT: fsw fs11, 108(a1)
-; ILP32E-NEXT: fsw fs10, 104(a1)
-; ILP32E-NEXT: fsw fs9, 100(a1)
-; ILP32E-NEXT: fsw fs8, 96(a1)
-; ILP32E-NEXT: fsw fs3, 92(a1)
-; ILP32E-NEXT: fsw fs2, 88(a1)
-; ILP32E-NEXT: fsw fs1, 84(a1)
-; ILP32E-NEXT: fsw fs0, 80(a1)
-; ILP32E-NEXT: fsw ft11, 76(a1)
-; ILP32E-NEXT: fsw ft10, 72(a1)
-; ILP32E-NEXT: fsw ft9, 68(a1)
-; ILP32E-NEXT: fsw ft8, 64(a1)
-; ILP32E-NEXT: fsw fa7, 60(a1)
-; ILP32E-NEXT: fsw fa6, 56(a1)
-; ILP32E-NEXT: fsw ft7, 52(a1)
-; ILP32E-NEXT: fsw ft6, 48(a1)
-; ILP32E-NEXT: fsw ft5, 44(a1)
-; ILP32E-NEXT: fsw ft4, 40(a1)
-; ILP32E-NEXT: fsw ft3, 36(a1)
-; ILP32E-NEXT: fsw ft2, 32(a1)
-; ILP32E-NEXT: fsw ft1, 28(a1)
-; ILP32E-NEXT: fsw ft0, 24(a1)
-; ILP32E-NEXT: fsw fa0, 20(a1)
-; ILP32E-NEXT: fsw fa1, 16(a1)
-; ILP32E-NEXT: fsw fa2, %lo(var+12)(a0)
-; ILP32E-NEXT: fsw fa3, %lo(var+8)(a0)
-; ILP32E-NEXT: fsw fa4, %lo(var+4)(a0)
-; ILP32E-NEXT: fsw fa5, %lo(var)(a0)
+; ILP32E-NEXT: addi a0, a0, %lo(var)
+; ILP32E-NEXT: flw fa5, 0(a0)
+; ILP32E-NEXT: flw fa4, 4(a0)
+; ILP32E-NEXT: flw fa3, 8(a0)
+; ILP32E-NEXT: flw fa2, 12(a0)
+; ILP32E-NEXT: flw fa1, 16(a0)
+; ILP32E-NEXT: flw fa0, 20(a0)
+; ILP32E-NEXT: flw ft0, 24(a0)
+; ILP32E-NEXT: flw ft1, 28(a0)
+; ILP32E-NEXT: flw ft2, 32(a0)
+; ILP32E-NEXT: flw ft3, 36(a0)
+; ILP32E-NEXT: flw ft4, 40(a0)
+; ILP32E-NEXT: flw ft5, 44(a0)
+; ILP32E-NEXT: flw ft6, 48(a0)
+; ILP32E-NEXT: flw ft7, 52(a0)
+; ILP32E-NEXT: flw fa6, 56(a0)
+; ILP32E-NEXT: flw fa7, 60(a0)
+; ILP32E-NEXT: flw ft8, 64(a0)
+; ILP32E-NEXT: flw ft9, 68(a0)
+; ILP32E-NEXT: flw ft10, 72(a0)
+; ILP32E-NEXT: flw ft11, 76(a0)
+; ILP32E-NEXT: flw fs0, 80(a0)
+; ILP32E-NEXT: flw fs1, 84(a0)
+; ILP32E-NEXT: flw fs2, 88(a0)
+; ILP32E-NEXT: flw fs3, 92(a0)
+; ILP32E-NEXT: flw fs4, 112(a0)
+; ILP32E-NEXT: flw fs5, 116(a0)
+; ILP32E-NEXT: flw fs6, 120(a0)
+; ILP32E-NEXT: flw fs7, 124(a0)
+; ILP32E-NEXT: flw fs8, 96(a0)
+; ILP32E-NEXT: flw fs9, 100(a0)
+; ILP32E-NEXT: flw fs10, 104(a0)
+; ILP32E-NEXT: flw fs11, 108(a0)
+; ILP32E-NEXT: fsw fs7, 124(a0)
+; ILP32E-NEXT: fsw fs6, 120(a0)
+; ILP32E-NEXT: fsw fs5, 116(a0)
+; ILP32E-NEXT: fsw fs4, 112(a0)
+; ILP32E-NEXT: fsw fs11, 108(a0)
+; ILP32E-NEXT: fsw fs10, 104(a0)
+; ILP32E-NEXT: fsw fs9, 100(a0)
+; ILP32E-NEXT: fsw fs8, 96(a0)
+; ILP32E-NEXT: fsw fs3, 92(a0)
+; ILP32E-NEXT: fsw fs2, 88(a0)
+; ILP32E-NEXT: fsw fs1, 84(a0)
+; ILP32E-NEXT: fsw fs0, 80(a0)
+; ILP32E-NEXT: fsw ft11, 76(a0)
+; ILP32E-NEXT: fsw ft10, 72(a0)
+; ILP32E-NEXT: fsw ft9, 68(a0)
+; ILP32E-NEXT: fsw ft8, 64(a0)
+; ILP32E-NEXT: fsw fa7, 60(a0)
+; ILP32E-NEXT: fsw fa6, 56(a0)
+; ILP32E-NEXT: fsw ft7, 52(a0)
+; ILP32E-NEXT: fsw ft6, 48(a0)
+; ILP32E-NEXT: fsw ft5, 44(a0)
+; ILP32E-NEXT: fsw ft4, 40(a0)
+; ILP32E-NEXT: fsw ft3, 36(a0)
+; ILP32E-NEXT: fsw ft2, 32(a0)
+; ILP32E-NEXT: fsw ft1, 28(a0)
+; ILP32E-NEXT: fsw ft0, 24(a0)
+; ILP32E-NEXT: fsw fa0, 20(a0)
+; ILP32E-NEXT: fsw fa1, 16(a0)
+; ILP32E-NEXT: fsw fa2, 12(a0)
+; ILP32E-NEXT: fsw fa3, 8(a0)
+; ILP32E-NEXT: fsw fa4, 4(a0)
+; ILP32E-NEXT: fsw fa5, 0(a0)
; ILP32E-NEXT: ret
;
; LP64-LABEL: callee:
; LP64: # %bb.0:
; LP64-NEXT: lui a0, %hi(var)
-; LP64-NEXT: flw fa5, %lo(var)(a0)
-; LP64-NEXT: flw fa4, %lo(var+4)(a0)
-; LP64-NEXT: flw fa3, %lo(var+8)(a0)
-; LP64-NEXT: flw fa2, %lo(var+12)(a0)
-; LP64-NEXT: addi a1, a0, %lo(var)
-; LP64-NEXT: flw fa1, 16(a1)
-; LP64-NEXT: flw fa0, 20(a1)
-; LP64-NEXT: flw ft0, 24(a1)
-; LP64-NEXT: flw ft1, 28(a1)
-; LP64-NEXT: flw ft2, 32(a1)
-; LP64-NEXT: flw ft3, 36(a1)
-; LP64-NEXT: flw ft4, 40(a1)
-; LP64-NEXT: flw ft5, 44(a1)
-; LP64-NEXT: flw ft6, 48(a1)
-; LP64-NEXT: flw ft7, 52(a1)
-; LP64-NEXT: flw fa6, 56(a1)
-; LP64-NEXT: flw fa7, 60(a1)
-; LP64-NEXT: flw ft8, 64(a1)
-; LP64-NEXT: flw ft9, 68(a1)
-; LP64-NEXT: flw ft10, 72(a1)
-; LP64-NEXT: flw ft11, 76(a1)
-; LP64-NEXT: flw fs0, 80(a1)
-; LP64-NEXT: flw fs1, 84(a1)
-; LP64-NEXT: flw fs2, 88(a1)
-; LP64-NEXT: flw fs3, 92(a1)
-; LP64-NEXT: flw fs4, 112(a1)
-; LP64-NEXT: flw fs5, 116(a1)
-; LP64-NEXT: flw fs6, 120(a1)
-; LP64-NEXT: flw fs7, 124(a1)
-; LP64-NEXT: flw fs8, 96(a1)
-; LP64-NEXT: flw fs9, 100(a1)
-; LP64-NEXT: flw fs10, 104(a1)
-; LP64-NEXT: flw fs11, 108(a1)
-; LP64-NEXT: fsw fs7, 124(a1)
-; LP64-NEXT: fsw fs6, 120(a1)
-; LP64-NEXT: fsw fs5, 116(a1)
-; LP64-NEXT: fsw fs4, 112(a1)
-; LP64-NEXT: fsw fs11, 108(a1)
-; LP64-NEXT: fsw fs10, 104(a1)
-; LP64-NEXT: fsw fs9, 100(a1)
-; LP64-NEXT: fsw fs8, 96(a1)
-; LP64-NEXT: fsw fs3, 92(a1)
-; LP64-NEXT: fsw fs2, 88(a1)
-; LP64-NEXT: fsw fs1, 84(a1)
-; LP64-NEXT: fsw fs0, 80(a1)
-; LP64-NEXT: fsw ft11, 76(a1)
-; LP64-NEXT: fsw ft10, 72(a1)
-; LP64-NEXT: fsw ft9, 68(a1)
-; LP64-NEXT: fsw ft8, 64(a1)
-; LP64-NEXT: fsw fa7, 60(a1)
-; LP64-NEXT: fsw fa6, 56(a1)
-; LP64-NEXT: fsw ft7, 52(a1)
-; LP64-NEXT: fsw ft6, 48(a1)
-; LP64-NEXT: fsw ft5, 44(a1)
-; LP64-NEXT: fsw ft4, 40(a1)
-; LP64-NEXT: fsw ft3, 36(a1)
-; LP64-NEXT: fsw ft2, 32(a1)
-; LP64-NEXT: fsw ft1, 28(a1)
-; LP64-NEXT: fsw ft0, 24(a1)
-; LP64-NEXT: fsw fa0, 20(a1)
-; LP64-NEXT: fsw fa1, 16(a1)
-; LP64-NEXT: fsw fa2, %lo(var+12)(a0)
-; LP64-NEXT: fsw fa3, %lo(var+8)(a0)
-; LP64-NEXT: fsw fa4, %lo(var+4)(a0)
-; LP64-NEXT: fsw fa5, %lo(var)(a0)
+; LP64-NEXT: addi a0, a0, %lo(var)
+; LP64-NEXT: flw fa5, 0(a0)
+; LP64-NEXT: flw fa4, 4(a0)
+; LP64-NEXT: flw fa3, 8(a0)
+; LP64-NEXT: flw fa2, 12(a0)
+; LP64-NEXT: flw fa1, 16(a0)
+; LP64-NEXT: flw fa0, 20(a0)
+; LP64-NEXT: flw ft0, 24(a0)
+; LP64-NEXT: flw ft1, 28(a0)
+; LP64-NEXT: flw ft2, 32(a0)
+; LP64-NEXT: flw ft3, 36(a0)
+; LP64-NEXT: flw ft4, 40(a0)
+; LP64-NEXT: flw ft5, 44(a0)
+; LP64-NEXT: flw ft6, 48(a0)
+; LP64-NEXT: flw ft7, 52(a0)
+; LP64-NEXT: flw fa6, 56(a0)
+; LP64-NEXT: flw fa7, 60(a0)
+; LP64-NEXT: flw ft8, 64(a0)
+; LP64-NEXT: flw ft9, 68(a0)
+; LP64-NEXT: flw ft10, 72(a0)
+; LP64-NEXT: flw ft11, 76(a0)
+; LP64-NEXT: flw fs0, 80(a0)
+; LP64-NEXT: flw fs1, 84(a0)
+; LP64-NEXT: flw fs2, 88(a0)
+; LP64-NEXT: flw fs3, 92(a0)
+; LP64-NEXT: flw fs4, 112(a0)
+; LP64-NEXT: flw fs5, 116(a0)
+; LP64-NEXT: flw fs6, 120(a0)
+; LP64-NEXT: flw fs7, 124(a0)
+; LP64-NEXT: flw fs8, 96(a0)
+; LP64-NEXT: flw fs9, 100(a0)
+; LP64-NEXT: flw fs10, 104(a0)
+; LP64-NEXT: flw fs11, 108(a0)
+; LP64-NEXT: fsw fs7, 124(a0)
+; LP64-NEXT: fsw fs6, 120(a0)
+; LP64-NEXT: fsw fs5, 116(a0)
+; LP64-NEXT: fsw fs4, 112(a0)
+; LP64-NEXT: fsw fs11, 108(a0)
+; LP64-NEXT: fsw fs10, 104(a0)
+; LP64-NEXT: fsw fs9, 100(a0)
+; LP64-NEXT: fsw fs8, 96(a0)
+; LP64-NEXT: fsw fs3, 92(a0)
+; LP64-NEXT: fsw fs2, 88(a0)
+; LP64-NEXT: fsw fs1, 84(a0)
+; LP64-NEXT: fsw fs0, 80(a0)
+; LP64-NEXT: fsw ft11, 76(a0)
+; LP64-NEXT: fsw ft10, 72(a0)
+; LP64-NEXT: fsw ft9, 68(a0)
+; LP64-NEXT: fsw ft8, 64(a0)
+; LP64-NEXT: fsw fa7, 60(a0)
+; LP64-NEXT: fsw fa6, 56(a0)
+; LP64-NEXT: fsw ft7, 52(a0)
+; LP64-NEXT: fsw ft6, 48(a0)
+; LP64-NEXT: fsw ft5, 44(a0)
+; LP64-NEXT: fsw ft4, 40(a0)
+; LP64-NEXT: fsw ft3, 36(a0)
+; LP64-NEXT: fsw ft2, 32(a0)
+; LP64-NEXT: fsw ft1, 28(a0)
+; LP64-NEXT: fsw ft0, 24(a0)
+; LP64-NEXT: fsw fa0, 20(a0)
+; LP64-NEXT: fsw fa1, 16(a0)
+; LP64-NEXT: fsw fa2, 12(a0)
+; LP64-NEXT: fsw fa3, 8(a0)
+; LP64-NEXT: fsw fa4, 4(a0)
+; LP64-NEXT: fsw fa5, 0(a0)
; LP64-NEXT: ret
;
; LP64E-LABEL: callee:
; LP64E: # %bb.0:
; LP64E-NEXT: lui a0, %hi(var)
-; LP64E-NEXT: flw fa5, %lo(var)(a0)
-; LP64E-NEXT: flw fa4, %lo(var+4)(a0)
-; LP64E-NEXT: flw fa3, %lo(var+8)(a0)
-; LP64E-NEXT: flw fa2, %lo(var+12)(a0)
-; LP64E-NEXT: addi a1, a0, %lo(var)
-; LP64E-NEXT: flw fa1, 16(a1)
-; LP64E-NEXT: flw fa0, 20(a1)
-; LP64E-NEXT: flw ft0, 24(a1)
-; LP64E-NEXT: flw ft1, 28(a1)
-; LP64E-NEXT: flw ft2, 32(a1)
-; LP64E-NEXT: flw ft3, 36(a1)
-; LP64E-NEXT: flw ft4, 40(a1)
-; LP64E-NEXT: flw ft5, 44(a1)
-; LP64E-NEXT: flw ft6, 48(a1)
-; LP64E-NEXT: flw ft7, 52(a1)
-; LP64E-NEXT: flw fa6, 56(a1)
-; LP64E-NEXT: flw fa7, 60(a1)
-; LP64E-NEXT: flw ft8, 64(a1)
-; LP64E-NEXT: flw ft9, 68(a1)
-; LP64E-NEXT: flw ft10, 72(a1)
-; LP64E-NEXT: flw ft11, 76(a1)
-; LP64E-NEXT: flw fs0, 80(a1)
-; LP64E-NEXT: flw fs1, 84(a1)
-; LP64E-NEXT: flw fs2, 88(a1)
-; LP64E-NEXT: flw fs3, 92(a1)
-; LP64E-NEXT: flw fs4, 112(a1)
-; LP64E-NEXT: flw fs5, 116(a1)
-; LP64E-NEXT: flw fs6, 120(a1)
-; LP64E-NEXT: flw fs7, 124(a1)
-; LP64E-NEXT: flw fs8, 96(a1)
-; LP64E-NEXT: flw fs9, 100(a1)
-; LP64E-NEXT: flw fs10, 104(a1)
-; LP64E-NEXT: flw fs11, 108(a1)
-; LP64E-NEXT: fsw fs7, 124(a1)
-; LP64E-NEXT: fsw fs6, 120(a1)
-; LP64E-NEXT: fsw fs5, 116(a1)
-; LP64E-NEXT: fsw fs4, 112(a1)
-; LP64E-NEXT: fsw fs11, 108(a1)
-; LP64E-NEXT: fsw fs10, 104(a1)
-; LP64E-NEXT: fsw fs9, 100(a1)
-; LP64E-NEXT: fsw fs8, 96(a1)
-; LP64E-NEXT: fsw fs3, 92(a1)
-; LP64E-NEXT: fsw fs2, 88(a1)
-; LP64E-NEXT: fsw fs1, 84(a1)
-; LP64E-NEXT: fsw fs0, 80(a1)
-; LP64E-NEXT: fsw ft11, 76(a1)
-; LP64E-NEXT: fsw ft10, 72(a1)
-; LP64E-NEXT: fsw ft9, 68(a1)
-; LP64E-NEXT: fsw ft8, 64(a1)
-; LP64E-NEXT: fsw fa7, 60(a1)
-; LP64E-NEXT: fsw fa6, 56(a1)
-; LP64E-NEXT: fsw ft7, 52(a1)
-; LP64E-NEXT: fsw ft6, 48(a1)
-; LP64E-NEXT: fsw ft5, 44(a1)
-; LP64E-NEXT: fsw ft4, 40(a1)
-; LP64E-NEXT: fsw ft3, 36(a1)
-; LP64E-NEXT: fsw ft2, 32(a1)
-; LP64E-NEXT: fsw ft1, 28(a1)
-; LP64E-NEXT: fsw ft0, 24(a1)
-; LP64E-NEXT: fsw fa0, 20(a1)
-; LP64E-NEXT: fsw fa1, 16(a1)
-; LP64E-NEXT: fsw fa2, %lo(var+12)(a0)
-; LP64E-NEXT: fsw fa3, %lo(var+8)(a0)
-; LP64E-NEXT: fsw fa4, %lo(var+4)(a0)
-; LP64E-NEXT: fsw fa5, %lo(var)(a0)
+; LP64E-NEXT: addi a0, a0, %lo(var)
+; LP64E-NEXT: flw fa5, 0(a0)
+; LP64E-NEXT: flw fa4, 4(a0)
+; LP64E-NEXT: flw fa3, 8(a0)
+; LP64E-NEXT: flw fa2, 12(a0)
+; LP64E-NEXT: flw fa1, 16(a0)
+; LP64E-NEXT: flw fa0, 20(a0)
+; LP64E-NEXT: flw ft0, 24(a0)
+; LP64E-NEXT: flw ft1, 28(a0)
+; LP64E-NEXT: flw ft2, 32(a0)
+; LP64E-NEXT: flw ft3, 36(a0)
+; LP64E-NEXT: flw ft4, 40(a0)
+; LP64E-NEXT: flw ft5, 44(a0)
+; LP64E-NEXT: flw ft6, 48(a0)
+; LP64E-NEXT: flw ft7, 52(a0)
+; LP64E-NEXT: flw fa6, 56(a0)
+; LP64E-NEXT: flw fa7, 60(a0)
+; LP64E-NEXT: flw ft8, 64(a0)
+; LP64E-NEXT: flw ft9, 68(a0)
+; LP64E-NEXT: flw ft10, 72(a0)
+; LP64E-NEXT: flw ft11, 76(a0)
+; LP64E-NEXT: flw fs0, 80(a0)
+; LP64E-NEXT: flw fs1, 84(a0)
+; LP64E-NEXT: flw fs2, 88(a0)
+; LP64E-NEXT: flw fs3, 92(a0)
+; LP64E-NEXT: flw fs4, 112(a0)
+; LP64E-NEXT: flw fs5, 116(a0)
+; LP64E-NEXT: flw fs6, 120(a0)
+; LP64E-NEXT: flw fs7, 124(a0)
+; LP64E-NEXT: flw fs8, 96(a0)
+; LP64E-NEXT: flw fs9, 100(a0)
+; LP64E-NEXT: flw fs10, 104(a0)
+; LP64E-NEXT: flw fs11, 108(a0)
+; LP64E-NEXT: fsw fs7, 124(a0)
+; LP64E-NEXT: fsw fs6, 120(a0)
+; LP64E-NEXT: fsw fs5, 116(a0)
+; LP64E-NEXT: fsw fs4, 112(a0)
+; LP64E-NEXT: fsw fs11, 108(a0)
+; LP64E-NEXT: fsw fs10, 104(a0)
+; LP64E-NEXT: fsw fs9, 100(a0)
+; LP64E-NEXT: fsw fs8, 96(a0)
+; LP64E-NEXT: fsw fs3, 92(a0)
+; LP64E-NEXT: fsw fs2, 88(a0)
+; LP64E-NEXT: fsw fs1, 84(a0)
+; LP64E-NEXT: fsw fs0, 80(a0)
+; LP64E-NEXT: fsw ft11, 76(a0)
+; LP64E-NEXT: fsw ft10, 72(a0)
+; LP64E-NEXT: fsw ft9, 68(a0)
+; LP64E-NEXT: fsw ft8, 64(a0)
+; LP64E-NEXT: fsw fa7, 60(a0)
+; LP64E-NEXT: fsw fa6, 56(a0)
+; LP64E-NEXT: fsw ft7, 52(a0)
+; LP64E-NEXT: fsw ft6, 48(a0)
+; LP64E-NEXT: fsw ft5, 44(a0)
+; LP64E-NEXT: fsw ft4, 40(a0)
+; LP64E-NEXT: fsw ft3, 36(a0)
+; LP64E-NEXT: fsw ft2, 32(a0)
+; LP64E-NEXT: fsw ft1, 28(a0)
+; LP64E-NEXT: fsw ft0, 24(a0)
+; LP64E-NEXT: fsw fa0, 20(a0)
+; LP64E-NEXT: fsw fa1, 16(a0)
+; LP64E-NEXT: fsw fa2, 12(a0)
+; LP64E-NEXT: fsw fa3, 8(a0)
+; LP64E-NEXT: fsw fa4, 4(a0)
+; LP64E-NEXT: fsw fa5, 0(a0)
; LP64E-NEXT: ret
;
; ILP32F-LABEL: callee:
@@ -321,71 +321,71 @@ define void @callee() nounwind {
; ILP32F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; ILP32F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; ILP32F-NEXT: lui a0, %hi(var)
-; ILP32F-NEXT: flw fa5, %lo(var)(a0)
-; ILP32F-NEXT: flw fa4, %lo(var+4)(a0)
-; ILP32F-NEXT: flw fa3, %lo(var+8)(a0)
-; ILP32F-NEXT: flw fa2, %lo(var+12)(a0)
-; ILP32F-NEXT: addi a1, a0, %lo(var)
-; ILP32F-NEXT: flw fa1, 16(a1)
-; ILP32F-NEXT: flw fa0, 20(a1)
-; ILP32F-NEXT: flw ft0, 24(a1)
-; ILP32F-NEXT: flw ft1, 28(a1)
-; ILP32F-NEXT: flw ft2, 32(a1)
-; ILP32F-NEXT: flw ft3, 36(a1)
-; ILP32F-NEXT: flw ft4, 40(a1)
-; ILP32F-NEXT: flw ft5, 44(a1)
-; ILP32F-NEXT: flw ft6, 48(a1)
-; ILP32F-NEXT: flw ft7, 52(a1)
-; ILP32F-NEXT: flw fa6, 56(a1)
-; ILP32F-NEXT: flw fa7, 60(a1)
-; ILP32F-NEXT: flw ft8, 64(a1)
-; ILP32F-NEXT: flw ft9, 68(a1)
-; ILP32F-NEXT: flw ft10, 72(a1)
-; ILP32F-NEXT: flw ft11, 76(a1)
-; ILP32F-NEXT: flw fs0, 80(a1)
-; ILP32F-NEXT: flw fs1, 84(a1)
-; ILP32F-NEXT: flw fs2, 88(a1)
-; ILP32F-NEXT: flw fs3, 92(a1)
-; ILP32F-NEXT: flw fs4, 112(a1)
-; ILP32F-NEXT: flw fs5, 116(a1)
-; ILP32F-NEXT: flw fs6, 120(a1)
-; ILP32F-NEXT: flw fs7, 124(a1)
-; ILP32F-NEXT: flw fs8, 96(a1)
-; ILP32F-NEXT: flw fs9, 100(a1)
-; ILP32F-NEXT: flw fs10, 104(a1)
-; ILP32F-NEXT: flw fs11, 108(a1)
-; ILP32F-NEXT: fsw fs7, 124(a1)
-; ILP32F-NEXT: fsw fs6, 120(a1)
-; ILP32F-NEXT: fsw fs5, 116(a1)
-; ILP32F-NEXT: fsw fs4, 112(a1)
-; ILP32F-NEXT: fsw fs11, 108(a1)
-; ILP32F-NEXT: fsw fs10, 104(a1)
-; ILP32F-NEXT: fsw fs9, 100(a1)
-; ILP32F-NEXT: fsw fs8, 96(a1)
-; ILP32F-NEXT: fsw fs3, 92(a1)
-; ILP32F-NEXT: fsw fs2, 88(a1)
-; ILP32F-NEXT: fsw fs1, 84(a1)
-; ILP32F-NEXT: fsw fs0, 80(a1)
-; ILP32F-NEXT: fsw ft11, 76(a1)
-; ILP32F-NEXT: fsw ft10, 72(a1)
-; ILP32F-NEXT: fsw ft9, 68(a1)
-; ILP32F-NEXT: fsw ft8, 64(a1)
-; ILP32F-NEXT: fsw fa7, 60(a1)
-; ILP32F-NEXT: fsw fa6, 56(a1)
-; ILP32F-NEXT: fsw ft7, 52(a1)
-; ILP32F-NEXT: fsw ft6, 48(a1)
-; ILP32F-NEXT: fsw ft5, 44(a1)
-; ILP32F-NEXT: fsw ft4, 40(a1)
-; ILP32F-NEXT: fsw ft3, 36(a1)
-; ILP32F-NEXT: fsw ft2, 32(a1)
-; ILP32F-NEXT: fsw ft1, 28(a1)
-; ILP32F-NEXT: fsw ft0, 24(a1)
-; ILP32F-NEXT: fsw fa0, 20(a1)
-; ILP32F-NEXT: fsw fa1, 16(a1)
-; ILP32F-NEXT: fsw fa2, %lo(var+12)(a0)
-; ILP32F-NEXT: fsw fa3, %lo(var+8)(a0)
-; ILP32F-NEXT: fsw fa4, %lo(var+4)(a0)
-; ILP32F-NEXT: fsw fa5, %lo(var)(a0)
+; ILP32F-NEXT: addi a0, a0, %lo(var)
+; ILP32F-NEXT: flw fa5, 0(a0)
+; ILP32F-NEXT: flw fa4, 4(a0)
+; ILP32F-NEXT: flw fa3, 8(a0)
+; ILP32F-NEXT: flw fa2, 12(a0)
+; ILP32F-NEXT: flw fa1, 16(a0)
+; ILP32F-NEXT: flw fa0, 20(a0)
+; ILP32F-NEXT: flw ft0, 24(a0)
+; ILP32F-NEXT: flw ft1, 28(a0)
+; ILP32F-NEXT: flw ft2, 32(a0)
+; ILP32F-NEXT: flw ft3, 36(a0)
+; ILP32F-NEXT: flw ft4, 40(a0)
+; ILP32F-NEXT: flw ft5, 44(a0)
+; ILP32F-NEXT: flw ft6, 48(a0)
+; ILP32F-NEXT: flw ft7, 52(a0)
+; ILP32F-NEXT: flw fa6, 56(a0)
+; ILP32F-NEXT: flw fa7, 60(a0)
+; ILP32F-NEXT: flw ft8, 64(a0)
+; ILP32F-NEXT: flw ft9, 68(a0)
+; ILP32F-NEXT: flw ft10, 72(a0)
+; ILP32F-NEXT: flw ft11, 76(a0)
+; ILP32F-NEXT: flw fs0, 80(a0)
+; ILP32F-NEXT: flw fs1, 84(a0)
+; ILP32F-NEXT: flw fs2, 88(a0)
+; ILP32F-NEXT: flw fs3, 92(a0)
+; ILP32F-NEXT: flw fs4, 112(a0)
+; ILP32F-NEXT: flw fs5, 116(a0)
+; ILP32F-NEXT: flw fs6, 120(a0)
+; ILP32F-NEXT: flw fs7, 124(a0)
+; ILP32F-NEXT: flw fs8, 96(a0)
+; ILP32F-NEXT: flw fs9, 100(a0)
+; ILP32F-NEXT: flw fs10, 104(a0)
+; ILP32F-NEXT: flw fs11, 108(a0)
+; ILP32F-NEXT: fsw fs7, 124(a0)
+; ILP32F-NEXT: fsw fs6, 120(a0)
+; ILP32F-NEXT: fsw fs5, 116(a0)
+; ILP32F-NEXT: fsw fs4, 112(a0)
+; ILP32F-NEXT: fsw fs11, 108(a0)
+; ILP32F-NEXT: fsw fs10, 104(a0)
+; ILP32F-NEXT: fsw fs9, 100(a0)
+; ILP32F-NEXT: fsw fs8, 96(a0)
+; ILP32F-NEXT: fsw fs3, 92(a0)
+; ILP32F-NEXT: fsw fs2, 88(a0)
+; ILP32F-NEXT: fsw fs1, 84(a0)
+; ILP32F-NEXT: fsw fs0, 80(a0)
+; ILP32F-NEXT: fsw ft11, 76(a0)
+; ILP32F-NEXT: fsw ft10, 72(a0)
+; ILP32F-NEXT: fsw ft9, 68(a0)
+; ILP32F-NEXT: fsw ft8, 64(a0)
+; ILP32F-NEXT: fsw fa7, 60(a0)
+; ILP32F-NEXT: fsw fa6, 56(a0)
+; ILP32F-NEXT: fsw ft7, 52(a0)
+; ILP32F-NEXT: fsw ft6, 48(a0)
+; ILP32F-NEXT: fsw ft5, 44(a0)
+; ILP32F-NEXT: fsw ft4, 40(a0)
+; ILP32F-NEXT: fsw ft3, 36(a0)
+; ILP32F-NEXT: fsw ft2, 32(a0)
+; ILP32F-NEXT: fsw ft1, 28(a0)
+; ILP32F-NEXT: fsw ft0, 24(a0)
+; ILP32F-NEXT: fsw fa0, 20(a0)
+; ILP32F-NEXT: fsw fa1, 16(a0)
+; ILP32F-NEXT: fsw fa2, 12(a0)
+; ILP32F-NEXT: fsw fa3, 8(a0)
+; ILP32F-NEXT: fsw fa4, 4(a0)
+; ILP32F-NEXT: fsw fa5, 0(a0)
; ILP32F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; ILP32F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
@@ -417,71 +417,71 @@ define void @callee() nounwind {
; LP64F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill
; LP64F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill
; LP64F-NEXT: lui a0, %hi(var)
-; LP64F-NEXT: flw fa5, %lo(var)(a0)
-; LP64F-NEXT: flw fa4, %lo(var+4)(a0)
-; LP64F-NEXT: flw fa3, %lo(var+8)(a0)
-; LP64F-NEXT: flw fa2, %lo(var+12)(a0)
-; LP64F-NEXT: addi a1, a0, %lo(var)
-; LP64F-NEXT: flw fa1, 16(a1)
-; LP64F-NEXT: flw fa0, 20(a1)
-; LP64F-NEXT: flw ft0, 24(a1)
-; LP64F-NEXT: flw ft1, 28(a1)
-; LP64F-NEXT: flw ft2, 32(a1)
-; LP64F-NEXT: flw ft3, 36(a1)
-; LP64F-NEXT: flw ft4, 40(a1)
-; LP64F-NEXT: flw ft5, 44(a1)
-; LP64F-NEXT: flw ft6, 48(a1)
-; LP64F-NEXT: flw ft7, 52(a1)
-; LP64F-NEXT: flw fa6, 56(a1)
-; LP64F-NEXT: flw fa7, 60(a1)
-; LP64F-NEXT: flw ft8, 64(a1)
-; LP64F-NEXT: flw ft9, 68(a1)
-; LP64F-NEXT: flw ft10, 72(a1)
-; LP64F-NEXT: flw ft11, 76(a1)
-; LP64F-NEXT: flw fs0, 80(a1)
-; LP64F-NEXT: flw fs1, 84(a1)
-; LP64F-NEXT: flw fs2, 88(a1)
-; LP64F-NEXT: flw fs3, 92(a1)
-; LP64F-NEXT: flw fs4, 112(a1)
-; LP64F-NEXT: flw fs5, 116(a1)
-; LP64F-NEXT: flw fs6, 120(a1)
-; LP64F-NEXT: flw fs7, 124(a1)
-; LP64F-NEXT: flw fs8, 96(a1)
-; LP64F-NEXT: flw fs9, 100(a1)
-; LP64F-NEXT: flw fs10, 104(a1)
-; LP64F-NEXT: flw fs11, 108(a1)
-; LP64F-NEXT: fsw fs7, 124(a1)
-; LP64F-NEXT: fsw fs6, 120(a1)
-; LP64F-NEXT: fsw fs5, 116(a1)
-; LP64F-NEXT: fsw fs4, 112(a1)
-; LP64F-NEXT: fsw fs11, 108(a1)
-; LP64F-NEXT: fsw fs10, 104(a1)
-; LP64F-NEXT: fsw fs9, 100(a1)
-; LP64F-NEXT: fsw fs8, 96(a1)
-; LP64F-NEXT: fsw fs3, 92(a1)
-; LP64F-NEXT: fsw fs2, 88(a1)
-; LP64F-NEXT: fsw fs1, 84(a1)
-; LP64F-NEXT: fsw fs0, 80(a1)
-; LP64F-NEXT: fsw ft11, 76(a1)
-; LP64F-NEXT: fsw ft10, 72(a1)
-; LP64F-NEXT: fsw ft9, 68(a1)
-; LP64F-NEXT: fsw ft8, 64(a1)
-; LP64F-NEXT: fsw fa7, 60(a1)
-; LP64F-NEXT: fsw fa6, 56(a1)
-; LP64F-NEXT: fsw ft7, 52(a1)
-; LP64F-NEXT: fsw ft6, 48(a1)
-; LP64F-NEXT: fsw ft5, 44(a1)
-; LP64F-NEXT: fsw ft4, 40(a1)
-; LP64F-NEXT: fsw ft3, 36(a1)
-; LP64F-NEXT: fsw ft2, 32(a1)
-; LP64F-NEXT: fsw ft1, 28(a1)
-; LP64F-NEXT: fsw ft0, 24(a1)
-; LP64F-NEXT: fsw fa0, 20(a1)
-; LP64F-NEXT: fsw fa1, 16(a1)
-; LP64F-NEXT: fsw fa2, %lo(var+12)(a0)
-; LP64F-NEXT: fsw fa3, %lo(var+8)(a0)
-; LP64F-NEXT: fsw fa4, %lo(var+4)(a0)
-; LP64F-NEXT: fsw fa5, %lo(var)(a0)
+; LP64F-NEXT: addi a0, a0, %lo(var)
+; LP64F-NEXT: flw fa5, 0(a0)
+; LP64F-NEXT: flw fa4, 4(a0)
+; LP64F-NEXT: flw fa3, 8(a0)
+; LP64F-NEXT: flw fa2, 12(a0)
+; LP64F-NEXT: flw fa1, 16(a0)
+; LP64F-NEXT: flw fa0, 20(a0)
+; LP64F-NEXT: flw ft0, 24(a0)
+; LP64F-NEXT: flw ft1, 28(a0)
+; LP64F-NEXT: flw ft2, 32(a0)
+; LP64F-NEXT: flw ft3, 36(a0)
+; LP64F-NEXT: flw ft4, 40(a0)
+; LP64F-NEXT: flw ft5, 44(a0)
+; LP64F-NEXT: flw ft6, 48(a0)
+; LP64F-NEXT: flw ft7, 52(a0)
+; LP64F-NEXT: flw fa6, 56(a0)
+; LP64F-NEXT: flw fa7, 60(a0)
+; LP64F-NEXT: flw ft8, 64(a0)
+; LP64F-NEXT: flw ft9, 68(a0)
+; LP64F-NEXT: flw ft10, 72(a0)
+; LP64F-NEXT: flw ft11, 76(a0)
+; LP64F-NEXT: flw fs0, 80(a0)
+; LP64F-NEXT: flw fs1, 84(a0)
+; LP64F-NEXT: flw fs2, 88(a0)
+; LP64F-NEXT: flw fs3, 92(a0)
+; LP64F-NEXT: flw fs4, 112(a0)
+; LP64F-NEXT: flw fs5, 116(a0)
+; LP64F-NEXT: flw fs6, 120(a0)
+; LP64F-NEXT: flw fs7, 124(a0)
+; LP64F-NEXT: flw fs8, 96(a0)
+; LP64F-NEXT: flw fs9, 100(a0)
+; LP64F-NEXT: flw fs10, 104(a0)
+; LP64F-NEXT: flw fs11, 108(a0)
+; LP64F-NEXT: fsw fs7, 124(a0)
+; LP64F-NEXT: fsw fs6, 120(a0)
+; LP64F-NEXT: fsw fs5, 116(a0)
+; LP64F-NEXT: fsw fs4, 112(a0)
+; LP64F-NEXT: fsw fs11, 108(a0)
+; LP64F-NEXT: fsw fs10, 104(a0)
+; LP64F-NEXT: fsw fs9, 100(a0)
+; LP64F-NEXT: fsw fs8, 96(a0)
+; LP64F-NEXT: fsw fs3, 92(a0)
+; LP64F-NEXT: fsw fs2, 88(a0)
+; LP64F-NEXT: fsw fs1, 84(a0)
+; LP64F-NEXT: fsw fs0, 80(a0)
+; LP64F-NEXT: fsw ft11, 76(a0)
+; LP64F-NEXT: fsw ft10, 72(a0)
+; LP64F-NEXT: fsw ft9, 68(a0)
+; LP64F-NEXT: fsw ft8, 64(a0)
+; LP64F-NEXT: fsw fa7, 60(a0)
+; LP64F-NEXT: fsw fa6, 56(a0)
+; LP64F-NEXT: fsw ft7, 52(a0)
+; LP64F-NEXT: fsw ft6, 48(a0)
+; LP64F-NEXT: fsw ft5, 44(a0)
+; LP64F-NEXT: fsw ft4, 40(a0)
+; LP64F-NEXT: fsw ft3, 36(a0)
+; LP64F-NEXT: fsw ft2, 32(a0)
+; LP64F-NEXT: fsw ft1, 28(a0)
+; LP64F-NEXT: fsw ft0, 24(a0)
+; LP64F-NEXT: fsw fa0, 20(a0)
+; LP64F-NEXT: fsw fa1, 16(a0)
+; LP64F-NEXT: fsw fa2, 12(a0)
+; LP64F-NEXT: fsw fa3, 8(a0)
+; LP64F-NEXT: fsw fa4, 4(a0)
+; LP64F-NEXT: fsw fa5, 0(a0)
; LP64F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload
; LP64F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload
@@ -513,71 +513,71 @@ define void @callee() nounwind {
; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui a0, %hi(var)
-; ILP32D-NEXT: flw fa5, %lo(var)(a0)
-; ILP32D-NEXT: flw fa4, %lo(var+4)(a0)
-; ILP32D-NEXT: flw fa3, %lo(var+8)(a0)
-; ILP32D-NEXT: flw fa2, %lo(var+12)(a0)
-; ILP32D-NEXT: addi a1, a0, %lo(var)
-; ILP32D-NEXT: flw fa1, 16(a1)
-; ILP32D-NEXT: flw fa0, 20(a1)
-; ILP32D-NEXT: flw ft0, 24(a1)
-; ILP32D-NEXT: flw ft1, 28(a1)
-; ILP32D-NEXT: flw ft2, 32(a1)
-; ILP32D-NEXT: flw ft3, 36(a1)
-; ILP32D-NEXT: flw ft4, 40(a1)
-; ILP32D-NEXT: flw ft5, 44(a1)
-; ILP32D-NEXT: flw ft6, 48(a1)
-; ILP32D-NEXT: flw ft7, 52(a1)
-; ILP32D-NEXT: flw fa6, 56(a1)
-; ILP32D-NEXT: flw fa7, 60(a1)
-; ILP32D-NEXT: flw ft8, 64(a1)
-; ILP32D-NEXT: flw ft9, 68(a1)
-; ILP32D-NEXT: flw ft10, 72(a1)
-; ILP32D-NEXT: flw ft11, 76(a1)
-; ILP32D-NEXT: flw fs0, 80(a1)
-; ILP32D-NEXT: flw fs1, 84(a1)
-; ILP32D-NEXT: flw fs2, 88(a1)
-; ILP32D-NEXT: flw fs3, 92(a1)
-; ILP32D-NEXT: flw fs4, 112(a1)
-; ILP32D-NEXT: flw fs5, 116(a1)
-; ILP32D-NEXT: flw fs6, 120(a1)
-; ILP32D-NEXT: flw fs7, 124(a1)
-; ILP32D-NEXT: flw fs8, 96(a1)
-; ILP32D-NEXT: flw fs9, 100(a1)
-; ILP32D-NEXT: flw fs10, 104(a1)
-; ILP32D-NEXT: flw fs11, 108(a1)
-; ILP32D-NEXT: fsw fs7, 124(a1)
-; ILP32D-NEXT: fsw fs6, 120(a1)
-; ILP32D-NEXT: fsw fs5, 116(a1)
-; ILP32D-NEXT: fsw fs4, 112(a1)
-; ILP32D-NEXT: fsw fs11, 108(a1)
-; ILP32D-NEXT: fsw fs10, 104(a1)
-; ILP32D-NEXT: fsw fs9, 100(a1)
-; ILP32D-NEXT: fsw fs8, 96(a1)
-; ILP32D-NEXT: fsw fs3, 92(a1)
-; ILP32D-NEXT: fsw fs2, 88(a1)
-; ILP32D-NEXT: fsw fs1, 84(a1)
-; ILP32D-NEXT: fsw fs0, 80(a1)
-; ILP32D-NEXT: fsw ft11, 76(a1)
-; ILP32D-NEXT: fsw ft10, 72(a1)
-; ILP32D-NEXT: fsw ft9, 68(a1)
-; ILP32D-NEXT: fsw ft8, 64(a1)
-; ILP32D-NEXT: fsw fa7, 60(a1)
-; ILP32D-NEXT: fsw fa6, 56(a1)
-; ILP32D-NEXT: fsw ft7, 52(a1)
-; ILP32D-NEXT: fsw ft6, 48(a1)
-; ILP32D-NEXT: fsw ft5, 44(a1)
-; ILP32D-NEXT: fsw ft4, 40(a1)
-; ILP32D-NEXT: fsw ft3, 36(a1)
-; ILP32D-NEXT: fsw ft2, 32(a1)
-; ILP32D-NEXT: fsw ft1, 28(a1)
-; ILP32D-NEXT: fsw ft0, 24(a1)
-; ILP32D-NEXT: fsw fa0, 20(a1)
-; ILP32D-NEXT: fsw fa1, 16(a1)
-; ILP32D-NEXT: fsw fa2, %lo(var+12)(a0)
-; ILP32D-NEXT: fsw fa3, %lo(var+8)(a0)
-; ILP32D-NEXT: fsw fa4, %lo(var+4)(a0)
-; ILP32D-NEXT: fsw fa5, %lo(var)(a0)
+; ILP32D-NEXT: addi a0, a0, %lo(var)
+; ILP32D-NEXT: flw fa5, 0(a0)
+; ILP32D-NEXT: flw fa4, 4(a0)
+; ILP32D-NEXT: flw fa3, 8(a0)
+; ILP32D-NEXT: flw fa2, 12(a0)
+; ILP32D-NEXT: flw fa1, 16(a0)
+; ILP32D-NEXT: flw fa0, 20(a0)
+; ILP32D-NEXT: flw ft0, 24(a0)
+; ILP32D-NEXT: flw ft1, 28(a0)
+; ILP32D-NEXT: flw ft2, 32(a0)
+; ILP32D-NEXT: flw ft3, 36(a0)
+; ILP32D-NEXT: flw ft4, 40(a0)
+; ILP32D-NEXT: flw ft5, 44(a0)
+; ILP32D-NEXT: flw ft6, 48(a0)
+; ILP32D-NEXT: flw ft7, 52(a0)
+; ILP32D-NEXT: flw fa6, 56(a0)
+; ILP32D-NEXT: flw fa7, 60(a0)
+; ILP32D-NEXT: flw ft8, 64(a0)
+; ILP32D-NEXT: flw ft9, 68(a0)
+; ILP32D-NEXT: flw ft10, 72(a0)
+; ILP32D-NEXT: flw ft11, 76(a0)
+; ILP32D-NEXT: flw fs0, 80(a0)
+; ILP32D-NEXT: flw fs1, 84(a0)
+; ILP32D-NEXT: flw fs2, 88(a0)
+; ILP32D-NEXT: flw fs3, 92(a0)
+; ILP32D-NEXT: flw fs4, 112(a0)
+; ILP32D-NEXT: flw fs5, 116(a0)
+; ILP32D-NEXT: flw fs6, 120(a0)
+; ILP32D-NEXT: flw fs7, 124(a0)
+; ILP32D-NEXT: flw fs8, 96(a0)
+; ILP32D-NEXT: flw fs9, 100(a0)
+; ILP32D-NEXT: flw fs10, 104(a0)
+; ILP32D-NEXT: flw fs11, 108(a0)
+; ILP32D-NEXT: fsw fs7, 124(a0)
+; ILP32D-NEXT: fsw fs6, 120(a0)
+; ILP32D-NEXT: fsw fs5, 116(a0)
+; ILP32D-NEXT: fsw fs4, 112(a0)
+; ILP32D-NEXT: fsw fs11, 108(a0)
+; ILP32D-NEXT: fsw fs10, 104(a0)
+; ILP32D-NEXT: fsw fs9, 100(a0)
+; ILP32D-NEXT: fsw fs8, 96(a0)
+; ILP32D-NEXT: fsw fs3, 92(a0)
+; ILP32D-NEXT: fsw fs2, 88(a0)
+; ILP32D-NEXT: fsw fs1, 84(a0)
+; ILP32D-NEXT: fsw fs0, 80(a0)
+; ILP32D-NEXT: fsw ft11, 76(a0)
+; ILP32D-NEXT: fsw ft10, 72(a0)
+; ILP32D-NEXT: fsw ft9, 68(a0)
+; ILP32D-NEXT: fsw ft8, 64(a0)
+; ILP32D-NEXT: fsw fa7, 60(a0)
+; ILP32D-NEXT: fsw fa6, 56(a0)
+; ILP32D-NEXT: fsw ft7, 52(a0)
+; ILP32D-NEXT: fsw ft6, 48(a0)
+; ILP32D-NEXT: fsw ft5, 44(a0)
+; ILP32D-NEXT: fsw ft4, 40(a0)
+; ILP32D-NEXT: fsw ft3, 36(a0)
+; ILP32D-NEXT: fsw ft2, 32(a0)
+; ILP32D-NEXT: fsw ft1, 28(a0)
+; ILP32D-NEXT: fsw ft0, 24(a0)
+; ILP32D-NEXT: fsw fa0, 20(a0)
+; ILP32D-NEXT: fsw fa1, 16(a0)
+; ILP32D-NEXT: fsw fa2, 12(a0)
+; ILP32D-NEXT: fsw fa3, 8(a0)
+; ILP32D-NEXT: fsw fa4, 4(a0)
+; ILP32D-NEXT: fsw fa5, 0(a0)
; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
@@ -609,71 +609,71 @@ define void @callee() nounwind {
; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui a0, %hi(var)
-; LP64D-NEXT: flw fa5, %lo(var)(a0)
-; LP64D-NEXT: flw fa4, %lo(var+4)(a0)
-; LP64D-NEXT: flw fa3, %lo(var+8)(a0)
-; LP64D-NEXT: flw fa2, %lo(var+12)(a0)
-; LP64D-NEXT: addi a1, a0, %lo(var)
-; LP64D-NEXT: flw fa1, 16(a1)
-; LP64D-NEXT: flw fa0, 20(a1)
-; LP64D-NEXT: flw ft0, 24(a1)
-; LP64D-NEXT: flw ft1, 28(a1)
-; LP64D-NEXT: flw ft2, 32(a1)
-; LP64D-NEXT: flw ft3, 36(a1)
-; LP64D-NEXT: flw ft4, 40(a1)
-; LP64D-NEXT: flw ft5, 44(a1)
-; LP64D-NEXT: flw ft6, 48(a1)
-; LP64D-NEXT: flw ft7, 52(a1)
-; LP64D-NEXT: flw fa6, 56(a1)
-; LP64D-NEXT: flw fa7, 60(a1)
-; LP64D-NEXT: flw ft8, 64(a1)
-; LP64D-NEXT: flw ft9, 68(a1)
-; LP64D-NEXT: flw ft10, 72(a1)
-; LP64D-NEXT: flw ft11, 76(a1)
-; LP64D-NEXT: flw fs0, 80(a1)
-; LP64D-NEXT: flw fs1, 84(a1)
-; LP64D-NEXT: flw fs2, 88(a1)
-; LP64D-NEXT: flw fs3, 92(a1)
-; LP64D-NEXT: flw fs4, 112(a1)
-; LP64D-NEXT: flw fs5, 116(a1)
-; LP64D-NEXT: flw fs6, 120(a1)
-; LP64D-NEXT: flw fs7, 124(a1)
-; LP64D-NEXT: flw fs8, 96(a1)
-; LP64D-NEXT: flw fs9, 100(a1)
-; LP64D-NEXT: flw fs10, 104(a1)
-; LP64D-NEXT: flw fs11, 108(a1)
-; LP64D-NEXT: fsw fs7, 124(a1)
-; LP64D-NEXT: fsw fs6, 120(a1)
-; LP64D-NEXT: fsw fs5, 116(a1)
-; LP64D-NEXT: fsw fs4, 112(a1)
-; LP64D-NEXT: fsw fs11, 108(a1)
-; LP64D-NEXT: fsw fs10, 104(a1)
-; LP64D-NEXT: fsw fs9, 100(a1)
-; LP64D-NEXT: fsw fs8, 96(a1)
-; LP64D-NEXT: fsw fs3, 92(a1)
-; LP64D-NEXT: fsw fs2, 88(a1)
-; LP64D-NEXT: fsw fs1, 84(a1)
-; LP64D-NEXT: fsw fs0, 80(a1)
-; LP64D-NEXT: fsw ft11, 76(a1)
-; LP64D-NEXT: fsw ft10, 72(a1)
-; LP64D-NEXT: fsw ft9, 68(a1)
-; LP64D-NEXT: fsw ft8, 64(a1)
-; LP64D-NEXT: fsw fa7, 60(a1)
-; LP64D-NEXT: fsw fa6, 56(a1)
-; LP64D-NEXT: fsw ft7, 52(a1)
-; LP64D-NEXT: fsw ft6, 48(a1)
-; LP64D-NEXT: fsw ft5, 44(a1)
-; LP64D-NEXT: fsw ft4, 40(a1)
-; LP64D-NEXT: fsw ft3, 36(a1)
-; LP64D-NEXT: fsw ft2, 32(a1)
-; LP64D-NEXT: fsw ft1, 28(a1)
-; LP64D-NEXT: fsw ft0, 24(a1)
-; LP64D-NEXT: fsw fa0, 20(a1)
-; LP64D-NEXT: fsw fa1, 16(a1)
-; LP64D-NEXT: fsw fa2, %lo(var+12)(a0)
-; LP64D-NEXT: fsw fa3, %lo(var+8)(a0)
-; LP64D-NEXT: fsw fa4, %lo(var+4)(a0)
-; LP64D-NEXT: fsw fa5, %lo(var)(a0)
+; LP64D-NEXT: addi a0, a0, %lo(var)
+; LP64D-NEXT: flw fa5, 0(a0)
+; LP64D-NEXT: flw fa4, 4(a0)
+; LP64D-NEXT: flw fa3, 8(a0)
+; LP64D-NEXT: flw fa2, 12(a0)
+; LP64D-NEXT: flw fa1, 16(a0)
+; LP64D-NEXT: flw fa0, 20(a0)
+; LP64D-NEXT: flw ft0, 24(a0)
+; LP64D-NEXT: flw ft1, 28(a0)
+; LP64D-NEXT: flw ft2, 32(a0)
+; LP64D-NEXT: flw ft3, 36(a0)
+; LP64D-NEXT: flw ft4, 40(a0)
+; LP64D-NEXT: flw ft5, 44(a0)
+; LP64D-NEXT: flw ft6, 48(a0)
+; LP64D-NEXT: flw ft7, 52(a0)
+; LP64D-NEXT: flw fa6, 56(a0)
+; LP64D-NEXT: flw fa7, 60(a0)
+; LP64D-NEXT: flw ft8, 64(a0)
+; LP64D-NEXT: flw ft9, 68(a0)
+; LP64D-NEXT: flw ft10, 72(a0)
+; LP64D-NEXT: flw ft11, 76(a0)
+; LP64D-NEXT: flw fs0, 80(a0)
+; LP64D-NEXT: flw fs1, 84(a0)
+; LP64D-NEXT: flw fs2, 88(a0)
+; LP64D-NEXT: flw fs3, 92(a0)
+; LP64D-NEXT: flw fs4, 112(a0)
+; LP64D-NEXT: flw fs5, 116(a0)
+; LP64D-NEXT: flw fs6, 120(a0)
+; LP64D-NEXT: flw fs7, 124(a0)
+; LP64D-NEXT: flw fs8, 96(a0)
+; LP64D-NEXT: flw fs9, 100(a0)
+; LP64D-NEXT: flw fs10, 104(a0)
+; LP64D-NEXT: flw fs11, 108(a0)
+; LP64D-NEXT: fsw fs7, 124(a0)
+; LP64D-NEXT: fsw fs6, 120(a0)
+; LP64D-NEXT: fsw fs5, 116(a0)
+; LP64D-NEXT: fsw fs4, 112(a0)
+; LP64D-NEXT: fsw fs11, 108(a0)
+; LP64D-NEXT: fsw fs10, 104(a0)
+; LP64D-NEXT: fsw fs9, 100(a0)
+; LP64D-NEXT: fsw fs8, 96(a0)
+; LP64D-NEXT: fsw fs3, 92(a0)
+; LP64D-NEXT: fsw fs2, 88(a0)
+; LP64D-NEXT: fsw fs1, 84(a0)
+; LP64D-NEXT: fsw fs0, 80(a0)
+; LP64D-NEXT: fsw ft11, 76(a0)
+; LP64D-NEXT: fsw ft10, 72(a0)
+; LP64D-NEXT: fsw ft9, 68(a0)
+; LP64D-NEXT: fsw ft8, 64(a0)
+; LP64D-NEXT: fsw fa7, 60(a0)
+; LP64D-NEXT: fsw fa6, 56(a0)
+; LP64D-NEXT: fsw ft7, 52(a0)
+; LP64D-NEXT: fsw ft6, 48(a0)
+; LP64D-NEXT: fsw ft5, 44(a0)
+; LP64D-NEXT: fsw ft4, 40(a0)
+; LP64D-NEXT: fsw ft3, 36(a0)
+; LP64D-NEXT: fsw ft2, 32(a0)
+; LP64D-NEXT: fsw ft1, 28(a0)
+; LP64D-NEXT: fsw ft0, 24(a0)
+; LP64D-NEXT: fsw fa0, 20(a0)
+; LP64D-NEXT: fsw fa1, 16(a0)
+; LP64D-NEXT: fsw fa2, 12(a0)
+; LP64D-NEXT: fsw fa3, 8(a0)
+; LP64D-NEXT: fsw fa4, 4(a0)
+; LP64D-NEXT: fsw fa5, 0(a0)
; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
@@ -706,571 +706,563 @@ define void @caller() nounwind {
; ILP32-NEXT: addi sp, sp, -144
; ILP32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill
-; ILP32-NEXT: sw s1, 132(sp) # 4-byte Folded Spill
; ILP32-NEXT: lui s0, %hi(var)
-; ILP32-NEXT: flw fa5, %lo(var)(s0)
+; ILP32-NEXT: addi s0, s0, %lo(var)
+; ILP32-NEXT: flw fa5, 0(s0)
+; ILP32-NEXT: fsw fa5, 132(sp) # 4-byte Folded Spill
+; ILP32-NEXT: flw fa5, 4(s0)
; ILP32-NEXT: fsw fa5, 128(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, %lo(var+4)(s0)
+; ILP32-NEXT: flw fa5, 8(s0)
; ILP32-NEXT: fsw fa5, 124(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, %lo(var+8)(s0)
+; ILP32-NEXT: flw fa5, 12(s0)
; ILP32-NEXT: fsw fa5, 120(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, %lo(var+12)(s0)
+; ILP32-NEXT: flw fa5, 16(s0)
; ILP32-NEXT: fsw fa5, 116(sp) # 4-byte Folded Spill
-; ILP32-NEXT: addi s1, s0, %lo(var)
-; ILP32-NEXT: flw fa5, 16(s1)
+; ILP32-NEXT: flw fa5, 20(s0)
; ILP32-NEXT: fsw fa5, 112(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 20(s1)
+; ILP32-NEXT: flw fa5, 24(s0)
; ILP32-NEXT: fsw fa5, 108(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 24(s1)
+; ILP32-NEXT: flw fa5, 28(s0)
; ILP32-NEXT: fsw fa5, 104(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 28(s1)
+; ILP32-NEXT: flw fa5, 32(s0)
; ILP32-NEXT: fsw fa5, 100(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 32(s1)
+; ILP32-NEXT: flw fa5, 36(s0)
; ILP32-NEXT: fsw fa5, 96(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 36(s1)
+; ILP32-NEXT: flw fa5, 40(s0)
; ILP32-NEXT: fsw fa5, 92(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 40(s1)
+; ILP32-NEXT: flw fa5, 44(s0)
; ILP32-NEXT: fsw fa5, 88(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 44(s1)
+; ILP32-NEXT: flw fa5, 48(s0)
; ILP32-NEXT: fsw fa5, 84(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 48(s1)
+; ILP32-NEXT: flw fa5, 52(s0)
; ILP32-NEXT: fsw fa5, 80(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 52(s1)
+; ILP32-NEXT: flw fa5, 56(s0)
; ILP32-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 56(s1)
+; ILP32-NEXT: flw fa5, 60(s0)
; ILP32-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 60(s1)
+; ILP32-NEXT: flw fa5, 64(s0)
; ILP32-NEXT: fsw fa5, 68(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 64(s1)
+; ILP32-NEXT: flw fa5, 68(s0)
; ILP32-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 68(s1)
+; ILP32-NEXT: flw fa5, 72(s0)
; ILP32-NEXT: fsw fa5, 60(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 72(s1)
+; ILP32-NEXT: flw fa5, 76(s0)
; ILP32-NEXT: fsw fa5, 56(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 76(s1)
+; ILP32-NEXT: flw fa5, 80(s0)
; ILP32-NEXT: fsw fa5, 52(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 80(s1)
+; ILP32-NEXT: flw fa5, 84(s0)
; ILP32-NEXT: fsw fa5, 48(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 84(s1)
+; ILP32-NEXT: flw fa5, 88(s0)
; ILP32-NEXT: fsw fa5, 44(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 88(s1)
+; ILP32-NEXT: flw fa5, 92(s0)
; ILP32-NEXT: fsw fa5, 40(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 92(s1)
+; ILP32-NEXT: flw fa5, 96(s0)
; ILP32-NEXT: fsw fa5, 36(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 96(s1)
+; ILP32-NEXT: flw fa5, 100(s0)
; ILP32-NEXT: fsw fa5, 32(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 100(s1)
+; ILP32-NEXT: flw fa5, 104(s0)
; ILP32-NEXT: fsw fa5, 28(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 104(s1)
+; ILP32-NEXT: flw fa5, 108(s0)
; ILP32-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 108(s1)
+; ILP32-NEXT: flw fa5, 112(s0)
; ILP32-NEXT: fsw fa5, 20(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 112(s1)
+; ILP32-NEXT: flw fa5, 116(s0)
; ILP32-NEXT: fsw fa5, 16(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 116(s1)
+; ILP32-NEXT: flw fa5, 120(s0)
; ILP32-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 120(s1)
+; ILP32-NEXT: flw fa5, 124(s0)
; ILP32-NEXT: fsw fa5, 8(sp) # 4-byte Folded Spill
-; ILP32-NEXT: flw fa5, 124(s1)
-; ILP32-NEXT: fsw fa5, 4(sp) # 4-byte Folded Spill
; ILP32-NEXT: call callee
-; ILP32-NEXT: flw fa5, 4(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 124(s1)
; ILP32-NEXT: flw fa5, 8(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 120(s1)
+; ILP32-NEXT: fsw fa5, 124(s0)
; ILP32-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 116(s1)
+; ILP32-NEXT: fsw fa5, 120(s0)
; ILP32-NEXT: flw fa5, 16(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 112(s1)
+; ILP32-NEXT: fsw fa5, 116(s0)
; ILP32-NEXT: flw fa5, 20(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 108(s1)
+; ILP32-NEXT: fsw fa5, 112(s0)
; ILP32-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 104(s1)
+; ILP32-NEXT: fsw fa5, 108(s0)
; ILP32-NEXT: flw fa5, 28(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 100(s1)
+; ILP32-NEXT: fsw fa5, 104(s0)
; ILP32-NEXT: flw fa5, 32(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 96(s1)
+; ILP32-NEXT: fsw fa5, 100(s0)
; ILP32-NEXT: flw fa5, 36(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 92(s1)
+; ILP32-NEXT: fsw fa5, 96(s0)
; ILP32-NEXT: flw fa5, 40(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 88(s1)
+; ILP32-NEXT: fsw fa5, 92(s0)
; ILP32-NEXT: flw fa5, 44(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 84(s1)
+; ILP32-NEXT: fsw fa5, 88(s0)
; ILP32-NEXT: flw fa5, 48(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 80(s1)
+; ILP32-NEXT: fsw fa5, 84(s0)
; ILP32-NEXT: flw fa5, 52(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 76(s1)
+; ILP32-NEXT: fsw fa5, 80(s0)
; ILP32-NEXT: flw fa5, 56(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 72(s1)
+; ILP32-NEXT: fsw fa5, 76(s0)
; ILP32-NEXT: flw fa5, 60(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 68(s1)
+; ILP32-NEXT: fsw fa5, 72(s0)
; ILP32-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 64(s1)
+; ILP32-NEXT: fsw fa5, 68(s0)
; ILP32-NEXT: flw fa5, 68(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 60(s1)
+; ILP32-NEXT: fsw fa5, 64(s0)
; ILP32-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 56(s1)
+; ILP32-NEXT: fsw fa5, 60(s0)
; ILP32-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 52(s1)
+; ILP32-NEXT: fsw fa5, 56(s0)
; ILP32-NEXT: flw fa5, 80(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 48(s1)
+; ILP32-NEXT: fsw fa5, 52(s0)
; ILP32-NEXT: flw fa5, 84(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 44(s1)
+; ILP32-NEXT: fsw fa5, 48(s0)
; ILP32-NEXT: flw fa5, 88(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 40(s1)
+; ILP32-NEXT: fsw fa5, 44(s0)
; ILP32-NEXT: flw fa5, 92(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 36(s1)
+; ILP32-NEXT: fsw fa5, 40(s0)
; ILP32-NEXT: flw fa5, 96(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 32(s1)
+; ILP32-NEXT: fsw fa5, 36(s0)
; ILP32-NEXT: flw fa5, 100(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 28(s1)
+; ILP32-NEXT: fsw fa5, 32(s0)
; ILP32-NEXT: flw fa5, 104(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 24(s1)
+; ILP32-NEXT: fsw fa5, 28(s0)
; ILP32-NEXT: flw fa5, 108(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 20(s1)
+; ILP32-NEXT: fsw fa5, 24(s0)
; ILP32-NEXT: flw fa5, 112(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, 16(s1)
+; ILP32-NEXT: fsw fa5, 20(s0)
; ILP32-NEXT: flw fa5, 116(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, %lo(var+12)(s0)
+; ILP32-NEXT: fsw fa5, 16(s0)
; ILP32-NEXT: flw fa5, 120(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, %lo(var+8)(s0)
+; ILP32-NEXT: fsw fa5, 12(s0)
; ILP32-NEXT: flw fa5, 124(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, %lo(var+4)(s0)
+; ILP32-NEXT: fsw fa5, 8(s0)
; ILP32-NEXT: flw fa5, 128(sp) # 4-byte Folded Reload
-; ILP32-NEXT: fsw fa5, %lo(var)(s0)
+; ILP32-NEXT: fsw fa5, 4(s0)
+; ILP32-NEXT: flw fa5, 132(sp) # 4-byte Folded Reload
+; ILP32-NEXT: fsw fa5, 0(s0)
; ILP32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
-; ILP32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
; ILP32-NEXT: addi sp, sp, 144
; ILP32-NEXT: ret
;
; ILP32E-LABEL: caller:
; ILP32E: # %bb.0:
-; ILP32E-NEXT: addi sp, sp, -140
-; ILP32E-NEXT: sw ra, 136(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: sw s0, 132(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: sw s1, 128(sp) # 4-byte Folded Spill
+; ILP32E-NEXT: addi sp, sp, -136
+; ILP32E-NEXT: sw ra, 132(sp) # 4-byte Folded Spill
+; ILP32E-NEXT: sw s0, 128(sp) # 4-byte Folded Spill
; ILP32E-NEXT: lui s0, %hi(var)
-; ILP32E-NEXT: flw fa5, %lo(var)(s0)
+; ILP32E-NEXT: addi s0, s0, %lo(var)
+; ILP32E-NEXT: flw fa5, 0(s0)
; ILP32E-NEXT: fsw fa5, 124(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, %lo(var+4)(s0)
+; ILP32E-NEXT: flw fa5, 4(s0)
; ILP32E-NEXT: fsw fa5, 120(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, %lo(var+8)(s0)
+; ILP32E-NEXT: flw fa5, 8(s0)
; ILP32E-NEXT: fsw fa5, 116(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, %lo(var+12)(s0)
+; ILP32E-NEXT: flw fa5, 12(s0)
; ILP32E-NEXT: fsw fa5, 112(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: addi s1, s0, %lo(var)
-; ILP32E-NEXT: flw fa5, 16(s1)
+; ILP32E-NEXT: flw fa5, 16(s0)
; ILP32E-NEXT: fsw fa5, 108(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 20(s1)
+; ILP32E-NEXT: flw fa5, 20(s0)
; ILP32E-NEXT: fsw fa5, 104(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 24(s1)
+; ILP32E-NEXT: flw fa5, 24(s0)
; ILP32E-NEXT: fsw fa5, 100(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 28(s1)
+; ILP32E-NEXT: flw fa5, 28(s0)
; ILP32E-NEXT: fsw fa5, 96(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 32(s1)
+; ILP32E-NEXT: flw fa5, 32(s0)
; ILP32E-NEXT: fsw fa5, 92(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 36(s1)
+; ILP32E-NEXT: flw fa5, 36(s0)
; ILP32E-NEXT: fsw fa5, 88(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 40(s1)
+; ILP32E-NEXT: flw fa5, 40(s0)
; ILP32E-NEXT: fsw fa5, 84(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 44(s1)
+; ILP32E-NEXT: flw fa5, 44(s0)
; ILP32E-NEXT: fsw fa5, 80(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 48(s1)
+; ILP32E-NEXT: flw fa5, 48(s0)
; ILP32E-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 52(s1)
+; ILP32E-NEXT: flw fa5, 52(s0)
; ILP32E-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 56(s1)
+; ILP32E-NEXT: flw fa5, 56(s0)
; ILP32E-NEXT: fsw fa5, 68(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 60(s1)
+; ILP32E-NEXT: flw fa5, 60(s0)
; ILP32E-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 64(s1)
+; ILP32E-NEXT: flw fa5, 64(s0)
; ILP32E-NEXT: fsw fa5, 60(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 68(s1)
+; ILP32E-NEXT: flw fa5, 68(s0)
; ILP32E-NEXT: fsw fa5, 56(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 72(s1)
+; ILP32E-NEXT: flw fa5, 72(s0)
; ILP32E-NEXT: fsw fa5, 52(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 76(s1)
+; ILP32E-NEXT: flw fa5, 76(s0)
; ILP32E-NEXT: fsw fa5, 48(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 80(s1)
+; ILP32E-NEXT: flw fa5, 80(s0)
; ILP32E-NEXT: fsw fa5, 44(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 84(s1)
+; ILP32E-NEXT: flw fa5, 84(s0)
; ILP32E-NEXT: fsw fa5, 40(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 88(s1)
+; ILP32E-NEXT: flw fa5, 88(s0)
; ILP32E-NEXT: fsw fa5, 36(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 92(s1)
+; ILP32E-NEXT: flw fa5, 92(s0)
; ILP32E-NEXT: fsw fa5, 32(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 96(s1)
+; ILP32E-NEXT: flw fa5, 96(s0)
; ILP32E-NEXT: fsw fa5, 28(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 100(s1)
+; ILP32E-NEXT: flw fa5, 100(s0)
; ILP32E-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 104(s1)
+; ILP32E-NEXT: flw fa5, 104(s0)
; ILP32E-NEXT: fsw fa5, 20(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 108(s1)
+; ILP32E-NEXT: flw fa5, 108(s0)
; ILP32E-NEXT: fsw fa5, 16(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 112(s1)
+; ILP32E-NEXT: flw fa5, 112(s0)
; ILP32E-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 116(s1)
+; ILP32E-NEXT: flw fa5, 116(s0)
; ILP32E-NEXT: fsw fa5, 8(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 120(s1)
+; ILP32E-NEXT: flw fa5, 120(s0)
; ILP32E-NEXT: fsw fa5, 4(sp) # 4-byte Folded Spill
-; ILP32E-NEXT: flw fa5, 124(s1)
+; ILP32E-NEXT: flw fa5, 124(s0)
; ILP32E-NEXT: fsw fa5, 0(sp) # 4-byte Folded Spill
; ILP32E-NEXT: call callee
; ILP32E-NEXT: flw fa5, 0(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 124(s1)
+; ILP32E-NEXT: fsw fa5, 124(s0)
; ILP32E-NEXT: flw fa5, 4(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 120(s1)
+; ILP32E-NEXT: fsw fa5, 120(s0)
; ILP32E-NEXT: flw fa5, 8(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 116(s1)
+; ILP32E-NEXT: fsw fa5, 116(s0)
; ILP32E-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 112(s1)
+; ILP32E-NEXT: fsw fa5, 112(s0)
; ILP32E-NEXT: flw fa5, 16(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 108(s1)
+; ILP32E-NEXT: fsw fa5, 108(s0)
; ILP32E-NEXT: flw fa5, 20(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 104(s1)
+; ILP32E-NEXT: fsw fa5, 104(s0)
; ILP32E-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 100(s1)
+; ILP32E-NEXT: fsw fa5, 100(s0)
; ILP32E-NEXT: flw fa5, 28(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 96(s1)
+; ILP32E-NEXT: fsw fa5, 96(s0)
; ILP32E-NEXT: flw fa5, 32(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 92(s1)
+; ILP32E-NEXT: fsw fa5, 92(s0)
; ILP32E-NEXT: flw fa5, 36(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 88(s1)
+; ILP32E-NEXT: fsw fa5, 88(s0)
; ILP32E-NEXT: flw fa5, 40(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 84(s1)
+; ILP32E-NEXT: fsw fa5, 84(s0)
; ILP32E-NEXT: flw fa5, 44(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 80(s1)
+; ILP32E-NEXT: fsw fa5, 80(s0)
; ILP32E-NEXT: flw fa5, 48(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 76(s1)
+; ILP32E-NEXT: fsw fa5, 76(s0)
; ILP32E-NEXT: flw fa5, 52(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 72(s1)
+; ILP32E-NEXT: fsw fa5, 72(s0)
; ILP32E-NEXT: flw fa5, 56(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 68(s1)
+; ILP32E-NEXT: fsw fa5, 68(s0)
; ILP32E-NEXT: flw fa5, 60(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 64(s1)
+; ILP32E-NEXT: fsw fa5, 64(s0)
; ILP32E-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 60(s1)
+; ILP32E-NEXT: fsw fa5, 60(s0)
; ILP32E-NEXT: flw fa5, 68(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 56(s1)
+; ILP32E-NEXT: fsw fa5, 56(s0)
; ILP32E-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 52(s1)
+; ILP32E-NEXT: fsw fa5, 52(s0)
; ILP32E-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 48(s1)
+; ILP32E-NEXT: fsw fa5, 48(s0)
; ILP32E-NEXT: flw fa5, 80(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 44(s1)
+; ILP32E-NEXT: fsw fa5, 44(s0)
; ILP32E-NEXT: flw fa5, 84(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 40(s1)
+; ILP32E-NEXT: fsw fa5, 40(s0)
; ILP32E-NEXT: flw fa5, 88(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 36(s1)
+; ILP32E-NEXT: fsw fa5, 36(s0)
; ILP32E-NEXT: flw fa5, 92(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 32(s1)
+; ILP32E-NEXT: fsw fa5, 32(s0)
; ILP32E-NEXT: flw fa5, 96(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 28(s1)
+; ILP32E-NEXT: fsw fa5, 28(s0)
; ILP32E-NEXT: flw fa5, 100(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 24(s1)
+; ILP32E-NEXT: fsw fa5, 24(s0)
; ILP32E-NEXT: flw fa5, 104(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 20(s1)
+; ILP32E-NEXT: fsw fa5, 20(s0)
; ILP32E-NEXT: flw fa5, 108(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, 16(s1)
+; ILP32E-NEXT: fsw fa5, 16(s0)
; ILP32E-NEXT: flw fa5, 112(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, %lo(var+12)(s0)
+; ILP32E-NEXT: fsw fa5, 12(s0)
; ILP32E-NEXT: flw fa5, 116(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, %lo(var+8)(s0)
+; ILP32E-NEXT: fsw fa5, 8(s0)
; ILP32E-NEXT: flw fa5, 120(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, %lo(var+4)(s0)
+; ILP32E-NEXT: fsw fa5, 4(s0)
; ILP32E-NEXT: flw fa5, 124(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: fsw fa5, %lo(var)(s0)
-; ILP32E-NEXT: lw ra, 136(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: lw s0, 132(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: lw s1, 128(sp) # 4-byte Folded Reload
-; ILP32E-NEXT: addi sp, sp, 140
+; ILP32E-NEXT: fsw fa5, 0(s0)
+; ILP32E-NEXT: lw ra, 132(sp) # 4-byte Folded Reload
+; ILP32E-NEXT: lw s0, 128(sp) # 4-byte Folded Reload
+; ILP32E-NEXT: addi sp, sp, 136
; ILP32E-NEXT: ret
;
; LP64-LABEL: caller:
; LP64: # %bb.0:
-; LP64-NEXT: addi sp, sp, -160
-; LP64-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
-; LP64-NEXT: sd s0, 144(sp) # 8-byte Folded Spill
-; LP64-NEXT: sd s1, 136(sp) # 8-byte Folded Spill
+; LP64-NEXT: addi sp, sp, -144
+; LP64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
+; LP64-NEXT: sd s0, 128(sp) # 8-byte Folded Spill
; LP64-NEXT: lui s0, %hi(var)
-; LP64-NEXT: flw fa5, %lo(var)(s0)
-; LP64-NEXT: fsw fa5, 132(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, %lo(var+4)(s0)
-; LP64-NEXT: fsw fa5, 128(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, %lo(var+8)(s0)
+; LP64-NEXT: addi s0, s0, %lo(var)
+; LP64-NEXT: flw fa5, 0(s0)
; LP64-NEXT: fsw fa5, 124(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, %lo(var+12)(s0)
+; LP64-NEXT: flw fa5, 4(s0)
; LP64-NEXT: fsw fa5, 120(sp) # 4-byte Folded Spill
-; LP64-NEXT: addi s1, s0, %lo(var)
-; LP64-NEXT: flw fa5, 16(s1)
+; LP64-NEXT: flw fa5, 8(s0)
; LP64-NEXT: fsw fa5, 116(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 20(s1)
+; LP64-NEXT: flw fa5, 12(s0)
; LP64-NEXT: fsw fa5, 112(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 24(s1)
+; LP64-NEXT: flw fa5, 16(s0)
; LP64-NEXT: fsw fa5, 108(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 28(s1)
+; LP64-NEXT: flw fa5, 20(s0)
; LP64-NEXT: fsw fa5, 104(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 32(s1)
+; LP64-NEXT: flw fa5, 24(s0)
; LP64-NEXT: fsw fa5, 100(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 36(s1)
+; LP64-NEXT: flw fa5, 28(s0)
; LP64-NEXT: fsw fa5, 96(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 40(s1)
+; LP64-NEXT: flw fa5, 32(s0)
; LP64-NEXT: fsw fa5, 92(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 44(s1)
+; LP64-NEXT: flw fa5, 36(s0)
; LP64-NEXT: fsw fa5, 88(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 48(s1)
+; LP64-NEXT: flw fa5, 40(s0)
; LP64-NEXT: fsw fa5, 84(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 52(s1)
+; LP64-NEXT: flw fa5, 44(s0)
; LP64-NEXT: fsw fa5, 80(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 56(s1)
+; LP64-NEXT: flw fa5, 48(s0)
; LP64-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 60(s1)
+; LP64-NEXT: flw fa5, 52(s0)
; LP64-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 64(s1)
+; LP64-NEXT: flw fa5, 56(s0)
; LP64-NEXT: fsw fa5, 68(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 68(s1)
+; LP64-NEXT: flw fa5, 60(s0)
; LP64-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 72(s1)
+; LP64-NEXT: flw fa5, 64(s0)
; LP64-NEXT: fsw fa5, 60(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 76(s1)
+; LP64-NEXT: flw fa5, 68(s0)
; LP64-NEXT: fsw fa5, 56(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 80(s1)
+; LP64-NEXT: flw fa5, 72(s0)
; LP64-NEXT: fsw fa5, 52(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 84(s1)
+; LP64-NEXT: flw fa5, 76(s0)
; LP64-NEXT: fsw fa5, 48(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 88(s1)
+; LP64-NEXT: flw fa5, 80(s0)
; LP64-NEXT: fsw fa5, 44(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 92(s1)
+; LP64-NEXT: flw fa5, 84(s0)
; LP64-NEXT: fsw fa5, 40(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 96(s1)
+; LP64-NEXT: flw fa5, 88(s0)
; LP64-NEXT: fsw fa5, 36(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 100(s1)
+; LP64-NEXT: flw fa5, 92(s0)
; LP64-NEXT: fsw fa5, 32(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 104(s1)
+; LP64-NEXT: flw fa5, 96(s0)
; LP64-NEXT: fsw fa5, 28(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 108(s1)
+; LP64-NEXT: flw fa5, 100(s0)
; LP64-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 112(s1)
+; LP64-NEXT: flw fa5, 104(s0)
; LP64-NEXT: fsw fa5, 20(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 116(s1)
+; LP64-NEXT: flw fa5, 108(s0)
; LP64-NEXT: fsw fa5, 16(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 120(s1)
+; LP64-NEXT: flw fa5, 112(s0)
; LP64-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill
-; LP64-NEXT: flw fa5, 124(s1)
+; LP64-NEXT: flw fa5, 116(s0)
; LP64-NEXT: fsw fa5, 8(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa5, 120(s0)
+; LP64-NEXT: fsw fa5, 4(sp) # 4-byte Folded Spill
+; LP64-NEXT: flw fa5, 124(s0)
+; LP64-NEXT: fsw fa5, 0(sp) # 4-byte Folded Spill
; LP64-NEXT: call callee
+; LP64-NEXT: flw fa5, 0(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa5, 124(s0)
+; LP64-NEXT: flw fa5, 4(sp) # 4-byte Folded Reload
+; LP64-NEXT: fsw fa5, 120(s0)
; LP64-NEXT: flw fa5, 8(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 124(s1)
+; LP64-NEXT: fsw fa5, 116(s0)
; LP64-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 120(s1)
+; LP64-NEXT: fsw fa5, 112(s0)
; LP64-NEXT: flw fa5, 16(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 116(s1)
+; LP64-NEXT: fsw fa5, 108(s0)
; LP64-NEXT: flw fa5, 20(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 112(s1)
+; LP64-NEXT: fsw fa5, 104(s0)
; LP64-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 108(s1)
+; LP64-NEXT: fsw fa5, 100(s0)
; LP64-NEXT: flw fa5, 28(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 104(s1)
+; LP64-NEXT: fsw fa5, 96(s0)
; LP64-NEXT: flw fa5, 32(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 100(s1)
+; LP64-NEXT: fsw fa5, 92(s0)
; LP64-NEXT: flw fa5, 36(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 96(s1)
+; LP64-NEXT: fsw fa5, 88(s0)
; LP64-NEXT: flw fa5, 40(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 92(s1)
+; LP64-NEXT: fsw fa5, 84(s0)
; LP64-NEXT: flw fa5, 44(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 88(s1)
+; LP64-NEXT: fsw fa5, 80(s0)
; LP64-NEXT: flw fa5, 48(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 84(s1)
+; LP64-NEXT: fsw fa5, 76(s0)
; LP64-NEXT: flw fa5, 52(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 80(s1)
+; LP64-NEXT: fsw fa5, 72(s0)
; LP64-NEXT: flw fa5, 56(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 76(s1)
+; LP64-NEXT: fsw fa5, 68(s0)
; LP64-NEXT: flw fa5, 60(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 72(s1)
+; LP64-NEXT: fsw fa5, 64(s0)
; LP64-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 68(s1)
+; LP64-NEXT: fsw fa5, 60(s0)
; LP64-NEXT: flw fa5, 68(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 64(s1)
+; LP64-NEXT: fsw fa5, 56(s0)
; LP64-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 60(s1)
+; LP64-NEXT: fsw fa5, 52(s0)
; LP64-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 56(s1)
+; LP64-NEXT: fsw fa5, 48(s0)
; LP64-NEXT: flw fa5, 80(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 52(s1)
+; LP64-NEXT: fsw fa5, 44(s0)
; LP64-NEXT: flw fa5, 84(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 48(s1)
+; LP64-NEXT: fsw fa5, 40(s0)
; LP64-NEXT: flw fa5, 88(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 44(s1)
+; LP64-NEXT: fsw fa5, 36(s0)
; LP64-NEXT: flw fa5, 92(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 40(s1)
+; LP64-NEXT: fsw fa5, 32(s0)
; LP64-NEXT: flw fa5, 96(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 36(s1)
+; LP64-NEXT: fsw fa5, 28(s0)
; LP64-NEXT: flw fa5, 100(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 32(s1)
+; LP64-NEXT: fsw fa5, 24(s0)
; LP64-NEXT: flw fa5, 104(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 28(s1)
+; LP64-NEXT: fsw fa5, 20(s0)
; LP64-NEXT: flw fa5, 108(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 24(s1)
+; LP64-NEXT: fsw fa5, 16(s0)
; LP64-NEXT: flw fa5, 112(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 20(s1)
+; LP64-NEXT: fsw fa5, 12(s0)
; LP64-NEXT: flw fa5, 116(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, 16(s1)
+; LP64-NEXT: fsw fa5, 8(s0)
; LP64-NEXT: flw fa5, 120(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, %lo(var+12)(s0)
+; LP64-NEXT: fsw fa5, 4(s0)
; LP64-NEXT: flw fa5, 124(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, %lo(var+8)(s0)
-; LP64-NEXT: flw fa5, 128(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, %lo(var+4)(s0)
-; LP64-NEXT: flw fa5, 132(sp) # 4-byte Folded Reload
-; LP64-NEXT: fsw fa5, %lo(var)(s0)
-; LP64-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
-; LP64-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
-; LP64-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
-; LP64-NEXT: addi sp, sp, 160
+; LP64-NEXT: fsw fa5, 0(s0)
+; LP64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
+; LP64-NEXT: ld s0, 128(sp) # 8-byte Folded Reload
+; LP64-NEXT: addi sp, sp, 144
; LP64-NEXT: ret
;
; LP64E-LABEL: caller:
; LP64E: # %bb.0:
-; LP64E-NEXT: addi sp, sp, -152
-; LP64E-NEXT: sd ra, 144(sp) # 8-byte Folded Spill
-; LP64E-NEXT: sd s0, 136(sp) # 8-byte Folded Spill
-; LP64E-NEXT: sd s1, 128(sp) # 8-byte Folded Spill
+; LP64E-NEXT: addi sp, sp, -144
+; LP64E-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
+; LP64E-NEXT: sd s0, 128(sp) # 8-byte Folded Spill
; LP64E-NEXT: lui s0, %hi(var)
-; LP64E-NEXT: flw fa5, %lo(var)(s0)
+; LP64E-NEXT: addi s0, s0, %lo(var)
+; LP64E-NEXT: flw fa5, 0(s0)
; LP64E-NEXT: fsw fa5, 124(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, %lo(var+4)(s0)
+; LP64E-NEXT: flw fa5, 4(s0)
; LP64E-NEXT: fsw fa5, 120(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, %lo(var+8)(s0)
+; LP64E-NEXT: flw fa5, 8(s0)
; LP64E-NEXT: fsw fa5, 116(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, %lo(var+12)(s0)
+; LP64E-NEXT: flw fa5, 12(s0)
; LP64E-NEXT: fsw fa5, 112(sp) # 4-byte Folded Spill
-; LP64E-NEXT: addi s1, s0, %lo(var)
-; LP64E-NEXT: flw fa5, 16(s1)
+; LP64E-NEXT: flw fa5, 16(s0)
; LP64E-NEXT: fsw fa5, 108(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 20(s1)
+; LP64E-NEXT: flw fa5, 20(s0)
; LP64E-NEXT: fsw fa5, 104(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 24(s1)
+; LP64E-NEXT: flw fa5, 24(s0)
; LP64E-NEXT: fsw fa5, 100(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 28(s1)
+; LP64E-NEXT: flw fa5, 28(s0)
; LP64E-NEXT: fsw fa5, 96(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 32(s1)
+; LP64E-NEXT: flw fa5, 32(s0)
; LP64E-NEXT: fsw fa5, 92(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 36(s1)
+; LP64E-NEXT: flw fa5, 36(s0)
; LP64E-NEXT: fsw fa5, 88(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 40(s1)
+; LP64E-NEXT: flw fa5, 40(s0)
; LP64E-NEXT: fsw fa5, 84(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 44(s1)
+; LP64E-NEXT: flw fa5, 44(s0)
; LP64E-NEXT: fsw fa5, 80(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 48(s1)
+; LP64E-NEXT: flw fa5, 48(s0)
; LP64E-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 52(s1)
+; LP64E-NEXT: flw fa5, 52(s0)
; LP64E-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 56(s1)
+; LP64E-NEXT: flw fa5, 56(s0)
; LP64E-NEXT: fsw fa5, 68(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 60(s1)
+; LP64E-NEXT: flw fa5, 60(s0)
; LP64E-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 64(s1)
+; LP64E-NEXT: flw fa5, 64(s0)
; LP64E-NEXT: fsw fa5, 60(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 68(s1)
+; LP64E-NEXT: flw fa5, 68(s0)
; LP64E-NEXT: fsw fa5, 56(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 72(s1)
+; LP64E-NEXT: flw fa5, 72(s0)
; LP64E-NEXT: fsw fa5, 52(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 76(s1)
+; LP64E-NEXT: flw fa5, 76(s0)
; LP64E-NEXT: fsw fa5, 48(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 80(s1)
+; LP64E-NEXT: flw fa5, 80(s0)
; LP64E-NEXT: fsw fa5, 44(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 84(s1)
+; LP64E-NEXT: flw fa5, 84(s0)
; LP64E-NEXT: fsw fa5, 40(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 88(s1)
+; LP64E-NEXT: flw fa5, 88(s0)
; LP64E-NEXT: fsw fa5, 36(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 92(s1)
+; LP64E-NEXT: flw fa5, 92(s0)
; LP64E-NEXT: fsw fa5, 32(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 96(s1)
+; LP64E-NEXT: flw fa5, 96(s0)
; LP64E-NEXT: fsw fa5, 28(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 100(s1)
+; LP64E-NEXT: flw fa5, 100(s0)
; LP64E-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 104(s1)
+; LP64E-NEXT: flw fa5, 104(s0)
; LP64E-NEXT: fsw fa5, 20(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 108(s1)
+; LP64E-NEXT: flw fa5, 108(s0)
; LP64E-NEXT: fsw fa5, 16(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 112(s1)
+; LP64E-NEXT: flw fa5, 112(s0)
; LP64E-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 116(s1)
+; LP64E-NEXT: flw fa5, 116(s0)
; LP64E-NEXT: fsw fa5, 8(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 120(s1)
+; LP64E-NEXT: flw fa5, 120(s0)
; LP64E-NEXT: fsw fa5, 4(sp) # 4-byte Folded Spill
-; LP64E-NEXT: flw fa5, 124(s1)
+; LP64E-NEXT: flw fa5, 124(s0)
; LP64E-NEXT: fsw fa5, 0(sp) # 4-byte Folded Spill
; LP64E-NEXT: call callee
; LP64E-NEXT: flw fa5, 0(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 124(s1)
+; LP64E-NEXT: fsw fa5, 124(s0)
; LP64E-NEXT: flw fa5, 4(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 120(s1)
+; LP64E-NEXT: fsw fa5, 120(s0)
; LP64E-NEXT: flw fa5, 8(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 116(s1)
+; LP64E-NEXT: fsw fa5, 116(s0)
; LP64E-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 112(s1)
+; LP64E-NEXT: fsw fa5, 112(s0)
; LP64E-NEXT: flw fa5, 16(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 108(s1)
+; LP64E-NEXT: fsw fa5, 108(s0)
; LP64E-NEXT: flw fa5, 20(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 104(s1)
+; LP64E-NEXT: fsw fa5, 104(s0)
; LP64E-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 100(s1)
+; LP64E-NEXT: fsw fa5, 100(s0)
; LP64E-NEXT: flw fa5, 28(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 96(s1)
+; LP64E-NEXT: fsw fa5, 96(s0)
; LP64E-NEXT: flw fa5, 32(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 92(s1)
+; LP64E-NEXT: fsw fa5, 92(s0)
; LP64E-NEXT: flw fa5, 36(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 88(s1)
+; LP64E-NEXT: fsw fa5, 88(s0)
; LP64E-NEXT: flw fa5, 40(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 84(s1)
+; LP64E-NEXT: fsw fa5, 84(s0)
; LP64E-NEXT: flw fa5, 44(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 80(s1)
+; LP64E-NEXT: fsw fa5, 80(s0)
; LP64E-NEXT: flw fa5, 48(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 76(s1)
+; LP64E-NEXT: fsw fa5, 76(s0)
; LP64E-NEXT: flw fa5, 52(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 72(s1)
+; LP64E-NEXT: fsw fa5, 72(s0)
; LP64E-NEXT: flw fa5, 56(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 68(s1)
+; LP64E-NEXT: fsw fa5, 68(s0)
; LP64E-NEXT: flw fa5, 60(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 64(s1)
+; LP64E-NEXT: fsw fa5, 64(s0)
; LP64E-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 60(s1)
+; LP64E-NEXT: fsw fa5, 60(s0)
; LP64E-NEXT: flw fa5, 68(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 56(s1)
+; LP64E-NEXT: fsw fa5, 56(s0)
; LP64E-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 52(s1)
+; LP64E-NEXT: fsw fa5, 52(s0)
; LP64E-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 48(s1)
+; LP64E-NEXT: fsw fa5, 48(s0)
; LP64E-NEXT: flw fa5, 80(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 44(s1)
+; LP64E-NEXT: fsw fa5, 44(s0)
; LP64E-NEXT: flw fa5, 84(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 40(s1)
+; LP64E-NEXT: fsw fa5, 40(s0)
; LP64E-NEXT: flw fa5, 88(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 36(s1)
+; LP64E-NEXT: fsw fa5, 36(s0)
; LP64E-NEXT: flw fa5, 92(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 32(s1)
+; LP64E-NEXT: fsw fa5, 32(s0)
; LP64E-NEXT: flw fa5, 96(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 28(s1)
+; LP64E-NEXT: fsw fa5, 28(s0)
; LP64E-NEXT: flw fa5, 100(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 24(s1)
+; LP64E-NEXT: fsw fa5, 24(s0)
; LP64E-NEXT: flw fa5, 104(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 20(s1)
+; LP64E-NEXT: fsw fa5, 20(s0)
; LP64E-NEXT: flw fa5, 108(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, 16(s1)
+; LP64E-NEXT: fsw fa5, 16(s0)
; LP64E-NEXT: flw fa5, 112(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, %lo(var+12)(s0)
+; LP64E-NEXT: fsw fa5, 12(s0)
; LP64E-NEXT: flw fa5, 116(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, %lo(var+8)(s0)
+; LP64E-NEXT: fsw fa5, 8(s0)
; LP64E-NEXT: flw fa5, 120(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, %lo(var+4)(s0)
+; LP64E-NEXT: fsw fa5, 4(s0)
; LP64E-NEXT: flw fa5, 124(sp) # 4-byte Folded Reload
-; LP64E-NEXT: fsw fa5, %lo(var)(s0)
-; LP64E-NEXT: ld ra, 144(sp) # 8-byte Folded Reload
-; LP64E-NEXT: ld s0, 136(sp) # 8-byte Folded Reload
-; LP64E-NEXT: ld s1, 128(sp) # 8-byte Folded Reload
-; LP64E-NEXT: addi sp, sp, 152
+; LP64E-NEXT: fsw fa5, 0(s0)
+; LP64E-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
+; LP64E-NEXT: ld s0, 128(sp) # 8-byte Folded Reload
+; LP64E-NEXT: addi sp, sp, 144
; LP64E-NEXT: ret
;
; ILP32F-LABEL: caller:
@@ -1278,285 +1270,281 @@ define void @caller() nounwind {
; ILP32F-NEXT: addi sp, sp, -144
; ILP32F-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
; ILP32F-NEXT: sw s0, 136(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: sw s1, 132(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs0, 128(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs1, 124(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs2, 120(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs3, 116(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs4, 112(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs5, 108(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs6, 104(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs7, 100(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs8, 96(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs9, 92(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs10, 88(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: fsw fs11, 84(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs0, 132(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs1, 128(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs2, 124(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs3, 120(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs4, 116(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs5, 112(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs6, 108(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs7, 104(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs8, 100(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs9, 96(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs10, 92(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: fsw fs11, 88(sp) # 4-byte Folded Spill
; ILP32F-NEXT: lui s0, %hi(var)
-; ILP32F-NEXT: flw fa5, %lo(var)(s0)
+; ILP32F-NEXT: addi s0, s0, %lo(var)
+; ILP32F-NEXT: flw fa5, 0(s0)
+; ILP32F-NEXT: fsw fa5, 84(sp) # 4-byte Folded Spill
+; ILP32F-NEXT: flw fa5, 4(s0)
; ILP32F-NEXT: fsw fa5, 80(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, %lo(var+4)(s0)
+; ILP32F-NEXT: flw fa5, 8(s0)
; ILP32F-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, %lo(var+8)(s0)
+; ILP32F-NEXT: flw fa5, 12(s0)
; ILP32F-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, %lo(var+12)(s0)
+; ILP32F-NEXT: flw fa5, 16(s0)
; ILP32F-NEXT: fsw fa5, 68(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: addi s1, s0, %lo(var)
-; ILP32F-NEXT: flw fa5, 16(s1)
+; ILP32F-NEXT: flw fa5, 20(s0)
; ILP32F-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 20(s1)
+; ILP32F-NEXT: flw fa5, 24(s0)
; ILP32F-NEXT: fsw fa5, 60(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 24(s1)
+; ILP32F-NEXT: flw fa5, 28(s0)
; ILP32F-NEXT: fsw fa5, 56(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 28(s1)
+; ILP32F-NEXT: flw fa5, 32(s0)
; ILP32F-NEXT: fsw fa5, 52(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 32(s1)
+; ILP32F-NEXT: flw fa5, 36(s0)
; ILP32F-NEXT: fsw fa5, 48(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 36(s1)
+; ILP32F-NEXT: flw fa5, 40(s0)
; ILP32F-NEXT: fsw fa5, 44(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 40(s1)
+; ILP32F-NEXT: flw fa5, 44(s0)
; ILP32F-NEXT: fsw fa5, 40(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 44(s1)
+; ILP32F-NEXT: flw fa5, 48(s0)
; ILP32F-NEXT: fsw fa5, 36(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 48(s1)
+; ILP32F-NEXT: flw fa5, 52(s0)
; ILP32F-NEXT: fsw fa5, 32(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 52(s1)
+; ILP32F-NEXT: flw fa5, 56(s0)
; ILP32F-NEXT: fsw fa5, 28(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 56(s1)
+; ILP32F-NEXT: flw fa5, 60(s0)
; ILP32F-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 60(s1)
+; ILP32F-NEXT: flw fa5, 64(s0)
; ILP32F-NEXT: fsw fa5, 20(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 64(s1)
+; ILP32F-NEXT: flw fa5, 68(s0)
; ILP32F-NEXT: fsw fa5, 16(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 68(s1)
+; ILP32F-NEXT: flw fa5, 72(s0)
; ILP32F-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 72(s1)
+; ILP32F-NEXT: flw fa5, 76(s0)
; ILP32F-NEXT: fsw fa5, 8(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fa5, 76(s1)
-; ILP32F-NEXT: fsw fa5, 4(sp) # 4-byte Folded Spill
-; ILP32F-NEXT: flw fs8, 80(s1)
-; ILP32F-NEXT: flw fs9, 84(s1)
-; ILP32F-NEXT: flw fs10, 88(s1)
-; ILP32F-NEXT: flw fs11, 92(s1)
-; ILP32F-NEXT: flw fs0, 96(s1)
-; ILP32F-NEXT: flw fs1, 100(s1)
-; ILP32F-NEXT: flw fs2, 104(s1)
-; ILP32F-NEXT: flw fs3, 108(s1)
-; ILP32F-NEXT: flw fs4, 112(s1)
-; ILP32F-NEXT: flw fs5, 116(s1)
-; ILP32F-NEXT: flw fs6, 120(s1)
-; ILP32F-NEXT: flw fs7, 124(s1)
+; ILP32F-NEXT: flw fs8, 80(s0)
+; ILP32F-NEXT: flw fs9, 84(s0)
+; ILP32F-NEXT: flw fs10, 88(s0)
+; ILP32F-NEXT: flw fs11, 92(s0)
+; ILP32F-NEXT: flw fs0, 96(s0)
+; ILP32F-NEXT: flw fs1, 100(s0)
+; ILP32F-NEXT: flw fs2, 104(s0)
+; ILP32F-NEXT: flw fs3, 108(s0)
+; ILP32F-NEXT: flw fs4, 112(s0)
+; ILP32F-NEXT: flw fs5, 116(s0)
+; ILP32F-NEXT: flw fs6, 120(s0)
+; ILP32F-NEXT: flw fs7, 124(s0)
; ILP32F-NEXT: call callee
-; ILP32F-NEXT: fsw fs7, 124(s1)
-; ILP32F-NEXT: fsw fs6, 120(s1)
-; ILP32F-NEXT: fsw fs5, 116(s1)
-; ILP32F-NEXT: fsw fs4, 112(s1)
-; ILP32F-NEXT: fsw fs3, 108(s1)
-; ILP32F-NEXT: fsw fs2, 104(s1)
-; ILP32F-NEXT: fsw fs1, 100(s1)
-; ILP32F-NEXT: fsw fs0, 96(s1)
-; ILP32F-NEXT: fsw fs11, 92(s1)
-; ILP32F-NEXT: fsw fs10, 88(s1)
-; ILP32F-NEXT: fsw fs9, 84(s1)
-; ILP32F-NEXT: fsw fs8, 80(s1)
-; ILP32F-NEXT: flw fa5, 4(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 76(s1)
+; ILP32F-NEXT: fsw fs7, 124(s0)
+; ILP32F-NEXT: fsw fs6, 120(s0)
+; ILP32F-NEXT: fsw fs5, 116(s0)
+; ILP32F-NEXT: fsw fs4, 112(s0)
+; ILP32F-NEXT: fsw fs3, 108(s0)
+; ILP32F-NEXT: fsw fs2, 104(s0)
+; ILP32F-NEXT: fsw fs1, 100(s0)
+; ILP32F-NEXT: fsw fs0, 96(s0)
+; ILP32F-NEXT: fsw fs11, 92(s0)
+; ILP32F-NEXT: fsw fs10, 88(s0)
+; ILP32F-NEXT: fsw fs9, 84(s0)
+; ILP32F-NEXT: fsw fs8, 80(s0)
; ILP32F-NEXT: flw fa5, 8(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 72(s1)
+; ILP32F-NEXT: fsw fa5, 76(s0)
; ILP32F-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 68(s1)
+; ILP32F-NEXT: fsw fa5, 72(s0)
; ILP32F-NEXT: flw fa5, 16(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 64(s1)
+; ILP32F-NEXT: fsw fa5, 68(s0)
; ILP32F-NEXT: flw fa5, 20(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 60(s1)
+; ILP32F-NEXT: fsw fa5, 64(s0)
; ILP32F-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 56(s1)
+; ILP32F-NEXT: fsw fa5, 60(s0)
; ILP32F-NEXT: flw fa5, 28(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 52(s1)
+; ILP32F-NEXT: fsw fa5, 56(s0)
; ILP32F-NEXT: flw fa5, 32(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 48(s1)
+; ILP32F-NEXT: fsw fa5, 52(s0)
; ILP32F-NEXT: flw fa5, 36(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 44(s1)
+; ILP32F-NEXT: fsw fa5, 48(s0)
; ILP32F-NEXT: flw fa5, 40(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 40(s1)
+; ILP32F-NEXT: fsw fa5, 44(s0)
; ILP32F-NEXT: flw fa5, 44(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 36(s1)
+; ILP32F-NEXT: fsw fa5, 40(s0)
; ILP32F-NEXT: flw fa5, 48(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 32(s1)
+; ILP32F-NEXT: fsw fa5, 36(s0)
; ILP32F-NEXT: flw fa5, 52(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 28(s1)
+; ILP32F-NEXT: fsw fa5, 32(s0)
; ILP32F-NEXT: flw fa5, 56(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 24(s1)
+; ILP32F-NEXT: fsw fa5, 28(s0)
; ILP32F-NEXT: flw fa5, 60(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 20(s1)
+; ILP32F-NEXT: fsw fa5, 24(s0)
; ILP32F-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, 16(s1)
+; ILP32F-NEXT: fsw fa5, 20(s0)
; ILP32F-NEXT: flw fa5, 68(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, %lo(var+12)(s0)
+; ILP32F-NEXT: fsw fa5, 16(s0)
; ILP32F-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, %lo(var+8)(s0)
+; ILP32F-NEXT: fsw fa5, 12(s0)
; ILP32F-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, %lo(var+4)(s0)
+; ILP32F-NEXT: fsw fa5, 8(s0)
; ILP32F-NEXT: flw fa5, 80(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: fsw fa5, %lo(var)(s0)
+; ILP32F-NEXT: fsw fa5, 4(s0)
+; ILP32F-NEXT: flw fa5, 84(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: fsw fa5, 0(s0)
; ILP32F-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; ILP32F-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs0, 128(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs1, 124(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs2, 120(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs3, 116(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs4, 112(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs5, 108(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs6, 104(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs7, 100(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs8, 96(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs9, 92(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs10, 88(sp) # 4-byte Folded Reload
-; ILP32F-NEXT: flw fs11, 84(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs0, 132(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs1, 128(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs2, 124(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs3, 120(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs4, 116(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs5, 112(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs6, 108(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs7, 104(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs8, 100(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs9, 96(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs10, 92(sp) # 4-byte Folded Reload
+; ILP32F-NEXT: flw fs11, 88(sp) # 4-byte Folded Reload
; ILP32F-NEXT: addi sp, sp, 144
; ILP32F-NEXT: ret
;
; LP64F-LABEL: caller:
; LP64F: # %bb.0:
-; LP64F-NEXT: addi sp, sp, -160
-; LP64F-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
-; LP64F-NEXT: sd s0, 144(sp) # 8-byte Folded Spill
-; LP64F-NEXT: sd s1, 136(sp) # 8-byte Folded Spill
-; LP64F-NEXT: fsw fs0, 132(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs1, 128(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs2, 124(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs3, 120(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs4, 116(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs5, 112(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs6, 108(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs7, 104(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs8, 100(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs9, 96(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs10, 92(sp) # 4-byte Folded Spill
-; LP64F-NEXT: fsw fs11, 88(sp) # 4-byte Folded Spill
+; LP64F-NEXT: addi sp, sp, -144
+; LP64F-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
+; LP64F-NEXT: sd s0, 128(sp) # 8-byte Folded Spill
+; LP64F-NEXT: fsw fs0, 124(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs1, 120(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs2, 116(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs3, 112(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs4, 108(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs5, 104(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs6, 100(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs7, 96(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs8, 92(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs9, 88(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs10, 84(sp) # 4-byte Folded Spill
+; LP64F-NEXT: fsw fs11, 80(sp) # 4-byte Folded Spill
; LP64F-NEXT: lui s0, %hi(var)
-; LP64F-NEXT: flw fa5, %lo(var)(s0)
-; LP64F-NEXT: fsw fa5, 84(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, %lo(var+4)(s0)
-; LP64F-NEXT: fsw fa5, 80(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, %lo(var+8)(s0)
+; LP64F-NEXT: addi s0, s0, %lo(var)
+; LP64F-NEXT: flw fa5, 0(s0)
; LP64F-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, %lo(var+12)(s0)
+; LP64F-NEXT: flw fa5, 4(s0)
; LP64F-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
-; LP64F-NEXT: addi s1, s0, %lo(var)
-; LP64F-NEXT: flw fa5, 16(s1)
+; LP64F-NEXT: flw fa5, 8(s0)
; LP64F-NEXT: fsw fa5, 68(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 20(s1)
+; LP64F-NEXT: flw fa5, 12(s0)
; LP64F-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 24(s1)
+; LP64F-NEXT: flw fa5, 16(s0)
; LP64F-NEXT: fsw fa5, 60(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 28(s1)
+; LP64F-NEXT: flw fa5, 20(s0)
; LP64F-NEXT: fsw fa5, 56(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 32(s1)
+; LP64F-NEXT: flw fa5, 24(s0)
; LP64F-NEXT: fsw fa5, 52(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 36(s1)
+; LP64F-NEXT: flw fa5, 28(s0)
; LP64F-NEXT: fsw fa5, 48(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 40(s1)
+; LP64F-NEXT: flw fa5, 32(s0)
; LP64F-NEXT: fsw fa5, 44(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 44(s1)
+; LP64F-NEXT: flw fa5, 36(s0)
; LP64F-NEXT: fsw fa5, 40(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 48(s1)
+; LP64F-NEXT: flw fa5, 40(s0)
; LP64F-NEXT: fsw fa5, 36(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 52(s1)
+; LP64F-NEXT: flw fa5, 44(s0)
; LP64F-NEXT: fsw fa5, 32(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 56(s1)
+; LP64F-NEXT: flw fa5, 48(s0)
; LP64F-NEXT: fsw fa5, 28(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 60(s1)
+; LP64F-NEXT: flw fa5, 52(s0)
; LP64F-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 64(s1)
+; LP64F-NEXT: flw fa5, 56(s0)
; LP64F-NEXT: fsw fa5, 20(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 68(s1)
+; LP64F-NEXT: flw fa5, 60(s0)
; LP64F-NEXT: fsw fa5, 16(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 72(s1)
+; LP64F-NEXT: flw fa5, 64(s0)
; LP64F-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fa5, 76(s1)
+; LP64F-NEXT: flw fa5, 68(s0)
; LP64F-NEXT: fsw fa5, 8(sp) # 4-byte Folded Spill
-; LP64F-NEXT: flw fs8, 80(s1)
-; LP64F-NEXT: flw fs9, 84(s1)
-; LP64F-NEXT: flw fs10, 88(s1)
-; LP64F-NEXT: flw fs11, 92(s1)
-; LP64F-NEXT: flw fs0, 96(s1)
-; LP64F-NEXT: flw fs1, 100(s1)
-; LP64F-NEXT: flw fs2, 104(s1)
-; LP64F-NEXT: flw fs3, 108(s1)
-; LP64F-NEXT: flw fs4, 112(s1)
-; LP64F-NEXT: flw fs5, 116(s1)
-; LP64F-NEXT: flw fs6, 120(s1)
-; LP64F-NEXT: flw fs7, 124(s1)
+; LP64F-NEXT: flw fa5, 72(s0)
+; LP64F-NEXT: fsw fa5, 4(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fa5, 76(s0)
+; LP64F-NEXT: fsw fa5, 0(sp) # 4-byte Folded Spill
+; LP64F-NEXT: flw fs8, 80(s0)
+; LP64F-NEXT: flw fs9, 84(s0)
+; LP64F-NEXT: flw fs10, 88(s0)
+; LP64F-NEXT: flw fs11, 92(s0)
+; LP64F-NEXT: flw fs0, 96(s0)
+; LP64F-NEXT: flw fs1, 100(s0)
+; LP64F-NEXT: flw fs2, 104(s0)
+; LP64F-NEXT: flw fs3, 108(s0)
+; LP64F-NEXT: flw fs4, 112(s0)
+; LP64F-NEXT: flw fs5, 116(s0)
+; LP64F-NEXT: flw fs6, 120(s0)
+; LP64F-NEXT: flw fs7, 124(s0)
; LP64F-NEXT: call callee
-; LP64F-NEXT: fsw fs7, 124(s1)
-; LP64F-NEXT: fsw fs6, 120(s1)
-; LP64F-NEXT: fsw fs5, 116(s1)
-; LP64F-NEXT: fsw fs4, 112(s1)
-; LP64F-NEXT: fsw fs3, 108(s1)
-; LP64F-NEXT: fsw fs2, 104(s1)
-; LP64F-NEXT: fsw fs1, 100(s1)
-; LP64F-NEXT: fsw fs0, 96(s1)
-; LP64F-NEXT: fsw fs11, 92(s1)
-; LP64F-NEXT: fsw fs10, 88(s1)
-; LP64F-NEXT: fsw fs9, 84(s1)
-; LP64F-NEXT: fsw fs8, 80(s1)
+; LP64F-NEXT: fsw fs7, 124(s0)
+; LP64F-NEXT: fsw fs6, 120(s0)
+; LP64F-NEXT: fsw fs5, 116(s0)
+; LP64F-NEXT: fsw fs4, 112(s0)
+; LP64F-NEXT: fsw fs3, 108(s0)
+; LP64F-NEXT: fsw fs2, 104(s0)
+; LP64F-NEXT: fsw fs1, 100(s0)
+; LP64F-NEXT: fsw fs0, 96(s0)
+; LP64F-NEXT: fsw fs11, 92(s0)
+; LP64F-NEXT: fsw fs10, 88(s0)
+; LP64F-NEXT: fsw fs9, 84(s0)
+; LP64F-NEXT: fsw fs8, 80(s0)
+; LP64F-NEXT: flw fa5, 0(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa5, 76(s0)
+; LP64F-NEXT: flw fa5, 4(sp) # 4-byte Folded Reload
+; LP64F-NEXT: fsw fa5, 72(s0)
; LP64F-NEXT: flw fa5, 8(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 76(s1)
+; LP64F-NEXT: fsw fa5, 68(s0)
; LP64F-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 72(s1)
+; LP64F-NEXT: fsw fa5, 64(s0)
; LP64F-NEXT: flw fa5, 16(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 68(s1)
+; LP64F-NEXT: fsw fa5, 60(s0)
; LP64F-NEXT: flw fa5, 20(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 64(s1)
+; LP64F-NEXT: fsw fa5, 56(s0)
; LP64F-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 60(s1)
+; LP64F-NEXT: fsw fa5, 52(s0)
; LP64F-NEXT: flw fa5, 28(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 56(s1)
+; LP64F-NEXT: fsw fa5, 48(s0)
; LP64F-NEXT: flw fa5, 32(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 52(s1)
+; LP64F-NEXT: fsw fa5, 44(s0)
; LP64F-NEXT: flw fa5, 36(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 48(s1)
+; LP64F-NEXT: fsw fa5, 40(s0)
; LP64F-NEXT: flw fa5, 40(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 44(s1)
+; LP64F-NEXT: fsw fa5, 36(s0)
; LP64F-NEXT: flw fa5, 44(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 40(s1)
+; LP64F-NEXT: fsw fa5, 32(s0)
; LP64F-NEXT: flw fa5, 48(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 36(s1)
+; LP64F-NEXT: fsw fa5, 28(s0)
; LP64F-NEXT: flw fa5, 52(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 32(s1)
+; LP64F-NEXT: fsw fa5, 24(s0)
; LP64F-NEXT: flw fa5, 56(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 28(s1)
+; LP64F-NEXT: fsw fa5, 20(s0)
; LP64F-NEXT: flw fa5, 60(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 24(s1)
+; LP64F-NEXT: fsw fa5, 16(s0)
; LP64F-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 20(s1)
+; LP64F-NEXT: fsw fa5, 12(s0)
; LP64F-NEXT: flw fa5, 68(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, 16(s1)
+; LP64F-NEXT: fsw fa5, 8(s0)
; LP64F-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, %lo(var+12)(s0)
+; LP64F-NEXT: fsw fa5, 4(s0)
; LP64F-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, %lo(var+8)(s0)
-; LP64F-NEXT: flw fa5, 80(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, %lo(var+4)(s0)
-; LP64F-NEXT: flw fa5, 84(sp) # 4-byte Folded Reload
-; LP64F-NEXT: fsw fa5, %lo(var)(s0)
-; LP64F-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
-; LP64F-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
-; LP64F-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
-; LP64F-NEXT: flw fs0, 132(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs1, 128(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs2, 124(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs3, 120(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs4, 116(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs5, 112(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs6, 108(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs7, 104(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs8, 100(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs9, 96(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs10, 92(sp) # 4-byte Folded Reload
-; LP64F-NEXT: flw fs11, 88(sp) # 4-byte Folded Reload
-; LP64F-NEXT: addi sp, sp, 160
+; LP64F-NEXT: fsw fa5, 0(s0)
+; LP64F-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
+; LP64F-NEXT: ld s0, 128(sp) # 8-byte Folded Reload
+; LP64F-NEXT: flw fs0, 124(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs1, 120(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs2, 116(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs3, 112(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs4, 108(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs5, 104(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs6, 100(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs7, 96(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs8, 92(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs9, 88(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs10, 84(sp) # 4-byte Folded Reload
+; LP64F-NEXT: flw fs11, 80(sp) # 4-byte Folded Reload
+; LP64F-NEXT: addi sp, sp, 144
; LP64F-NEXT: ret
;
; ILP32D-LABEL: caller:
@@ -1564,285 +1552,281 @@ define void @caller() nounwind {
; ILP32D-NEXT: addi sp, sp, -192
; ILP32D-NEXT: sw ra, 188(sp) # 4-byte Folded Spill
; ILP32D-NEXT: sw s0, 184(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: sw s1, 180(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: fsd fs0, 168(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs1, 160(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs2, 152(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs3, 144(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs4, 136(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs5, 128(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs6, 120(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs7, 112(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs8, 104(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs9, 96(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs10, 88(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs11, 80(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs0, 176(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs1, 168(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs2, 160(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs3, 152(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs4, 144(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs5, 136(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs6, 128(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs7, 120(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs8, 112(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs9, 104(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs10, 96(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs11, 88(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui s0, %hi(var)
-; ILP32D-NEXT: flw fa5, %lo(var)(s0)
+; ILP32D-NEXT: addi s0, s0, %lo(var)
+; ILP32D-NEXT: flw fa5, 0(s0)
+; ILP32D-NEXT: fsw fa5, 84(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa5, 4(s0)
+; ILP32D-NEXT: fsw fa5, 80(sp) # 4-byte Folded Spill
+; ILP32D-NEXT: flw fa5, 8(s0)
; ILP32D-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, %lo(var+4)(s0)
+; ILP32D-NEXT: flw fa5, 12(s0)
; ILP32D-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, %lo(var+8)(s0)
+; ILP32D-NEXT: flw fa5, 16(s0)
; ILP32D-NEXT: fsw fa5, 68(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, %lo(var+12)(s0)
+; ILP32D-NEXT: flw fa5, 20(s0)
; ILP32D-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: addi s1, s0, %lo(var)
-; ILP32D-NEXT: flw fa5, 16(s1)
+; ILP32D-NEXT: flw fa5, 24(s0)
; ILP32D-NEXT: fsw fa5, 60(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 20(s1)
+; ILP32D-NEXT: flw fa5, 28(s0)
; ILP32D-NEXT: fsw fa5, 56(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 24(s1)
+; ILP32D-NEXT: flw fa5, 32(s0)
; ILP32D-NEXT: fsw fa5, 52(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 28(s1)
+; ILP32D-NEXT: flw fa5, 36(s0)
; ILP32D-NEXT: fsw fa5, 48(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 32(s1)
+; ILP32D-NEXT: flw fa5, 40(s0)
; ILP32D-NEXT: fsw fa5, 44(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 36(s1)
+; ILP32D-NEXT: flw fa5, 44(s0)
; ILP32D-NEXT: fsw fa5, 40(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 40(s1)
+; ILP32D-NEXT: flw fa5, 48(s0)
; ILP32D-NEXT: fsw fa5, 36(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 44(s1)
+; ILP32D-NEXT: flw fa5, 52(s0)
; ILP32D-NEXT: fsw fa5, 32(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 48(s1)
+; ILP32D-NEXT: flw fa5, 56(s0)
; ILP32D-NEXT: fsw fa5, 28(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 52(s1)
+; ILP32D-NEXT: flw fa5, 60(s0)
; ILP32D-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 56(s1)
+; ILP32D-NEXT: flw fa5, 64(s0)
; ILP32D-NEXT: fsw fa5, 20(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 60(s1)
+; ILP32D-NEXT: flw fa5, 68(s0)
; ILP32D-NEXT: fsw fa5, 16(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 64(s1)
+; ILP32D-NEXT: flw fa5, 72(s0)
; ILP32D-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 68(s1)
+; ILP32D-NEXT: flw fa5, 76(s0)
; ILP32D-NEXT: fsw fa5, 8(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 72(s1)
-; ILP32D-NEXT: fsw fa5, 4(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fa5, 76(s1)
-; ILP32D-NEXT: fsw fa5, 0(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: flw fs8, 80(s1)
-; ILP32D-NEXT: flw fs9, 84(s1)
-; ILP32D-NEXT: flw fs10, 88(s1)
-; ILP32D-NEXT: flw fs11, 92(s1)
-; ILP32D-NEXT: flw fs0, 96(s1)
-; ILP32D-NEXT: flw fs1, 100(s1)
-; ILP32D-NEXT: flw fs2, 104(s1)
-; ILP32D-NEXT: flw fs3, 108(s1)
-; ILP32D-NEXT: flw fs4, 112(s1)
-; ILP32D-NEXT: flw fs5, 116(s1)
-; ILP32D-NEXT: flw fs6, 120(s1)
-; ILP32D-NEXT: flw fs7, 124(s1)
+; ILP32D-NEXT: flw fs8, 80(s0)
+; ILP32D-NEXT: flw fs9, 84(s0)
+; ILP32D-NEXT: flw fs10, 88(s0)
+; ILP32D-NEXT: flw fs11, 92(s0)
+; ILP32D-NEXT: flw fs0, 96(s0)
+; ILP32D-NEXT: flw fs1, 100(s0)
+; ILP32D-NEXT: flw fs2, 104(s0)
+; ILP32D-NEXT: flw fs3, 108(s0)
+; ILP32D-NEXT: flw fs4, 112(s0)
+; ILP32D-NEXT: flw fs5, 116(s0)
+; ILP32D-NEXT: flw fs6, 120(s0)
+; ILP32D-NEXT: flw fs7, 124(s0)
; ILP32D-NEXT: call callee
-; ILP32D-NEXT: fsw fs7, 124(s1)
-; ILP32D-NEXT: fsw fs6, 120(s1)
-; ILP32D-NEXT: fsw fs5, 116(s1)
-; ILP32D-NEXT: fsw fs4, 112(s1)
-; ILP32D-NEXT: fsw fs3, 108(s1)
-; ILP32D-NEXT: fsw fs2, 104(s1)
-; ILP32D-NEXT: fsw fs1, 100(s1)
-; ILP32D-NEXT: fsw fs0, 96(s1)
-; ILP32D-NEXT: fsw fs11, 92(s1)
-; ILP32D-NEXT: fsw fs10, 88(s1)
-; ILP32D-NEXT: fsw fs9, 84(s1)
-; ILP32D-NEXT: fsw fs8, 80(s1)
-; ILP32D-NEXT: flw fa5, 0(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 76(s1)
-; ILP32D-NEXT: flw fa5, 4(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 72(s1)
+; ILP32D-NEXT: fsw fs7, 124(s0)
+; ILP32D-NEXT: fsw fs6, 120(s0)
+; ILP32D-NEXT: fsw fs5, 116(s0)
+; ILP32D-NEXT: fsw fs4, 112(s0)
+; ILP32D-NEXT: fsw fs3, 108(s0)
+; ILP32D-NEXT: fsw fs2, 104(s0)
+; ILP32D-NEXT: fsw fs1, 100(s0)
+; ILP32D-NEXT: fsw fs0, 96(s0)
+; ILP32D-NEXT: fsw fs11, 92(s0)
+; ILP32D-NEXT: fsw fs10, 88(s0)
+; ILP32D-NEXT: fsw fs9, 84(s0)
+; ILP32D-NEXT: fsw fs8, 80(s0)
; ILP32D-NEXT: flw fa5, 8(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 68(s1)
+; ILP32D-NEXT: fsw fa5, 76(s0)
; ILP32D-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 64(s1)
+; ILP32D-NEXT: fsw fa5, 72(s0)
; ILP32D-NEXT: flw fa5, 16(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 60(s1)
+; ILP32D-NEXT: fsw fa5, 68(s0)
; ILP32D-NEXT: flw fa5, 20(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 56(s1)
+; ILP32D-NEXT: fsw fa5, 64(s0)
; ILP32D-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 52(s1)
+; ILP32D-NEXT: fsw fa5, 60(s0)
; ILP32D-NEXT: flw fa5, 28(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 48(s1)
+; ILP32D-NEXT: fsw fa5, 56(s0)
; ILP32D-NEXT: flw fa5, 32(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 44(s1)
+; ILP32D-NEXT: fsw fa5, 52(s0)
; ILP32D-NEXT: flw fa5, 36(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 40(s1)
+; ILP32D-NEXT: fsw fa5, 48(s0)
; ILP32D-NEXT: flw fa5, 40(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 36(s1)
+; ILP32D-NEXT: fsw fa5, 44(s0)
; ILP32D-NEXT: flw fa5, 44(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 32(s1)
+; ILP32D-NEXT: fsw fa5, 40(s0)
; ILP32D-NEXT: flw fa5, 48(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 28(s1)
+; ILP32D-NEXT: fsw fa5, 36(s0)
; ILP32D-NEXT: flw fa5, 52(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 24(s1)
+; ILP32D-NEXT: fsw fa5, 32(s0)
; ILP32D-NEXT: flw fa5, 56(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 20(s1)
+; ILP32D-NEXT: fsw fa5, 28(s0)
; ILP32D-NEXT: flw fa5, 60(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, 16(s1)
+; ILP32D-NEXT: fsw fa5, 24(s0)
; ILP32D-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, %lo(var+12)(s0)
+; ILP32D-NEXT: fsw fa5, 20(s0)
; ILP32D-NEXT: flw fa5, 68(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, %lo(var+8)(s0)
+; ILP32D-NEXT: fsw fa5, 16(s0)
; ILP32D-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, %lo(var+4)(s0)
+; ILP32D-NEXT: fsw fa5, 12(s0)
; ILP32D-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fsw fa5, %lo(var)(s0)
+; ILP32D-NEXT: fsw fa5, 8(s0)
+; ILP32D-NEXT: flw fa5, 80(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa5, 4(s0)
+; ILP32D-NEXT: flw fa5, 84(sp) # 4-byte Folded Reload
+; ILP32D-NEXT: fsw fa5, 0(s0)
; ILP32D-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s0, 184(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: lw s1, 180(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fld fs0, 168(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs1, 160(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs2, 152(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs3, 144(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs4, 136(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs5, 128(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs6, 120(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs7, 112(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs8, 104(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs9, 96(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs10, 88(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs11, 80(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs0, 176(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs1, 168(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs2, 160(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs3, 152(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs4, 144(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs5, 136(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs6, 128(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs7, 120(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs8, 112(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs9, 104(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs10, 96(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs11, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: addi sp, sp, 192
; ILP32D-NEXT: ret
;
; LP64D-LABEL: caller:
; LP64D: # %bb.0:
-; LP64D-NEXT: addi sp, sp, -208
-; LP64D-NEXT: sd ra, 200(sp) # 8-byte Folded Spill
-; LP64D-NEXT: sd s0, 192(sp) # 8-byte Folded Spill
-; LP64D-NEXT: sd s1, 184(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs0, 176(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs1, 168(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs2, 160(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs3, 152(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs4, 144(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs5, 136(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs6, 128(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs7, 120(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs8, 112(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs9, 104(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs10, 96(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs11, 88(sp) # 8-byte Folded Spill
+; LP64D-NEXT: addi sp, sp, -192
+; LP64D-NEXT: sd ra, 184(sp) # 8-byte Folded Spill
+; LP64D-NEXT: sd s0, 176(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs0, 168(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs1, 160(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs2, 152(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs3, 144(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs4, 136(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs5, 128(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs6, 120(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs7, 112(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs8, 104(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs9, 96(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs10, 88(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs11, 80(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui s0, %hi(var)
-; LP64D-NEXT: flw fa5, %lo(var)(s0)
-; LP64D-NEXT: fsw fa5, 84(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, %lo(var+4)(s0)
-; LP64D-NEXT: fsw fa5, 80(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, %lo(var+8)(s0)
+; LP64D-NEXT: addi s0, s0, %lo(var)
+; LP64D-NEXT: flw fa5, 0(s0)
; LP64D-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, %lo(var+12)(s0)
+; LP64D-NEXT: flw fa5, 4(s0)
; LP64D-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill
-; LP64D-NEXT: addi s1, s0, %lo(var)
-; LP64D-NEXT: flw fa5, 16(s1)
+; LP64D-NEXT: flw fa5, 8(s0)
; LP64D-NEXT: fsw fa5, 68(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 20(s1)
+; LP64D-NEXT: flw fa5, 12(s0)
; LP64D-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 24(s1)
+; LP64D-NEXT: flw fa5, 16(s0)
; LP64D-NEXT: fsw fa5, 60(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 28(s1)
+; LP64D-NEXT: flw fa5, 20(s0)
; LP64D-NEXT: fsw fa5, 56(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 32(s1)
+; LP64D-NEXT: flw fa5, 24(s0)
; LP64D-NEXT: fsw fa5, 52(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 36(s1)
+; LP64D-NEXT: flw fa5, 28(s0)
; LP64D-NEXT: fsw fa5, 48(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 40(s1)
+; LP64D-NEXT: flw fa5, 32(s0)
; LP64D-NEXT: fsw fa5, 44(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 44(s1)
+; LP64D-NEXT: flw fa5, 36(s0)
; LP64D-NEXT: fsw fa5, 40(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 48(s1)
+; LP64D-NEXT: flw fa5, 40(s0)
; LP64D-NEXT: fsw fa5, 36(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 52(s1)
+; LP64D-NEXT: flw fa5, 44(s0)
; LP64D-NEXT: fsw fa5, 32(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 56(s1)
+; LP64D-NEXT: flw fa5, 48(s0)
; LP64D-NEXT: fsw fa5, 28(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 60(s1)
+; LP64D-NEXT: flw fa5, 52(s0)
; LP64D-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 64(s1)
+; LP64D-NEXT: flw fa5, 56(s0)
; LP64D-NEXT: fsw fa5, 20(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 68(s1)
+; LP64D-NEXT: flw fa5, 60(s0)
; LP64D-NEXT: fsw fa5, 16(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 72(s1)
+; LP64D-NEXT: flw fa5, 64(s0)
; LP64D-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fa5, 76(s1)
+; LP64D-NEXT: flw fa5, 68(s0)
; LP64D-NEXT: fsw fa5, 8(sp) # 4-byte Folded Spill
-; LP64D-NEXT: flw fs8, 80(s1)
-; LP64D-NEXT: flw fs9, 84(s1)
-; LP64D-NEXT: flw fs10, 88(s1)
-; LP64D-NEXT: flw fs11, 92(s1)
-; LP64D-NEXT: flw fs0, 96(s1)
-; LP64D-NEXT: flw fs1, 100(s1)
-; LP64D-NEXT: flw fs2, 104(s1)
-; LP64D-NEXT: flw fs3, 108(s1)
-; LP64D-NEXT: flw fs4, 112(s1)
-; LP64D-NEXT: flw fs5, 116(s1)
-; LP64D-NEXT: flw fs6, 120(s1)
-; LP64D-NEXT: flw fs7, 124(s1)
+; LP64D-NEXT: flw fa5, 72(s0)
+; LP64D-NEXT: fsw fa5, 4(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fa5, 76(s0)
+; LP64D-NEXT: fsw fa5, 0(sp) # 4-byte Folded Spill
+; LP64D-NEXT: flw fs8, 80(s0)
+; LP64D-NEXT: flw fs9, 84(s0)
+; LP64D-NEXT: flw fs10, 88(s0)
+; LP64D-NEXT: flw fs11, 92(s0)
+; LP64D-NEXT: flw fs0, 96(s0)
+; LP64D-NEXT: flw fs1, 100(s0)
+; LP64D-NEXT: flw fs2, 104(s0)
+; LP64D-NEXT: flw fs3, 108(s0)
+; LP64D-NEXT: flw fs4, 112(s0)
+; LP64D-NEXT: flw fs5, 116(s0)
+; LP64D-NEXT: flw fs6, 120(s0)
+; LP64D-NEXT: flw fs7, 124(s0)
; LP64D-NEXT: call callee
-; LP64D-NEXT: fsw fs7, 124(s1)
-; LP64D-NEXT: fsw fs6, 120(s1)
-; LP64D-NEXT: fsw fs5, 116(s1)
-; LP64D-NEXT: fsw fs4, 112(s1)
-; LP64D-NEXT: fsw fs3, 108(s1)
-; LP64D-NEXT: fsw fs2, 104(s1)
-; LP64D-NEXT: fsw fs1, 100(s1)
-; LP64D-NEXT: fsw fs0, 96(s1)
-; LP64D-NEXT: fsw fs11, 92(s1)
-; LP64D-NEXT: fsw fs10, 88(s1)
-; LP64D-NEXT: fsw fs9, 84(s1)
-; LP64D-NEXT: fsw fs8, 80(s1)
+; LP64D-NEXT: fsw fs7, 124(s0)
+; LP64D-NEXT: fsw fs6, 120(s0)
+; LP64D-NEXT: fsw fs5, 116(s0)
+; LP64D-NEXT: fsw fs4, 112(s0)
+; LP64D-NEXT: fsw fs3, 108(s0)
+; LP64D-NEXT: fsw fs2, 104(s0)
+; LP64D-NEXT: fsw fs1, 100(s0)
+; LP64D-NEXT: fsw fs0, 96(s0)
+; LP64D-NEXT: fsw fs11, 92(s0)
+; LP64D-NEXT: fsw fs10, 88(s0)
+; LP64D-NEXT: fsw fs9, 84(s0)
+; LP64D-NEXT: fsw fs8, 80(s0)
+; LP64D-NEXT: flw fa5, 0(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa5, 76(s0)
+; LP64D-NEXT: flw fa5, 4(sp) # 4-byte Folded Reload
+; LP64D-NEXT: fsw fa5, 72(s0)
; LP64D-NEXT: flw fa5, 8(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 76(s1)
+; LP64D-NEXT: fsw fa5, 68(s0)
; LP64D-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 72(s1)
+; LP64D-NEXT: fsw fa5, 64(s0)
; LP64D-NEXT: flw fa5, 16(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 68(s1)
+; LP64D-NEXT: fsw fa5, 60(s0)
; LP64D-NEXT: flw fa5, 20(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 64(s1)
+; LP64D-NEXT: fsw fa5, 56(s0)
; LP64D-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 60(s1)
+; LP64D-NEXT: fsw fa5, 52(s0)
; LP64D-NEXT: flw fa5, 28(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 56(s1)
+; LP64D-NEXT: fsw fa5, 48(s0)
; LP64D-NEXT: flw fa5, 32(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 52(s1)
+; LP64D-NEXT: fsw fa5, 44(s0)
; LP64D-NEXT: flw fa5, 36(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 48(s1)
+; LP64D-NEXT: fsw fa5, 40(s0)
; LP64D-NEXT: flw fa5, 40(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 44(s1)
+; LP64D-NEXT: fsw fa5, 36(s0)
; LP64D-NEXT: flw fa5, 44(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 40(s1)
+; LP64D-NEXT: fsw fa5, 32(s0)
; LP64D-NEXT: flw fa5, 48(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 36(s1)
+; LP64D-NEXT: fsw fa5, 28(s0)
; LP64D-NEXT: flw fa5, 52(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 32(s1)
+; LP64D-NEXT: fsw fa5, 24(s0)
; LP64D-NEXT: flw fa5, 56(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 28(s1)
+; LP64D-NEXT: fsw fa5, 20(s0)
; LP64D-NEXT: flw fa5, 60(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 24(s1)
+; LP64D-NEXT: fsw fa5, 16(s0)
; LP64D-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 20(s1)
+; LP64D-NEXT: fsw fa5, 12(s0)
; LP64D-NEXT: flw fa5, 68(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, 16(s1)
+; LP64D-NEXT: fsw fa5, 8(s0)
; LP64D-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, %lo(var+12)(s0)
+; LP64D-NEXT: fsw fa5, 4(s0)
; LP64D-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, %lo(var+8)(s0)
-; LP64D-NEXT: flw fa5, 80(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, %lo(var+4)(s0)
-; LP64D-NEXT: flw fa5, 84(sp) # 4-byte Folded Reload
-; LP64D-NEXT: fsw fa5, %lo(var)(s0)
-; LP64D-NEXT: ld ra, 200(sp) # 8-byte Folded Reload
-; LP64D-NEXT: ld s0, 192(sp) # 8-byte Folded Reload
-; LP64D-NEXT: ld s1, 184(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs0, 176(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs1, 168(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs2, 160(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs3, 152(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs4, 144(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs5, 136(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs6, 128(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs7, 120(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs8, 112(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs9, 104(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs10, 96(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs11, 88(sp) # 8-byte Folded Reload
-; LP64D-NEXT: addi sp, sp, 208
+; LP64D-NEXT: fsw fa5, 0(s0)
+; LP64D-NEXT: ld ra, 184(sp) # 8-byte Folded Reload
+; LP64D-NEXT: ld s0, 176(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs0, 168(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs1, 160(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs2, 152(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs3, 144(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs4, 136(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs5, 128(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs6, 120(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs7, 112(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs8, 104(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs9, 96(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs10, 88(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs11, 80(sp) # 8-byte Folded Reload
+; LP64D-NEXT: addi sp, sp, 192
; LP64D-NEXT: ret
%val = load [32 x float], ptr @var
call void @callee()
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
index 0501c700f57df..5820b29f73c6d 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
@@ -22,211 +22,211 @@ define void @callee() nounwind {
; ILP32-LABEL: callee:
; ILP32: # %bb.0:
; ILP32-NEXT: lui a0, %hi(var)
-; ILP32-NEXT: fld fa5, %lo(var)(a0)
-; ILP32-NEXT: fld fa4, %lo(var+8)(a0)
-; ILP32-NEXT: addi a1, a0, %lo(var)
-; ILP32-NEXT: fld fa3, 16(a1)
-; ILP32-NEXT: fld fa2, 24(a1)
-; ILP32-NEXT: fld fa1, 32(a1)
-; ILP32-NEXT: fld fa0, 40(a1)
-; ILP32-NEXT: fld ft0, 48(a1)
-; ILP32-NEXT: fld ft1, 56(a1)
-; ILP32-NEXT: fld ft2, 64(a1)
-; ILP32-NEXT: fld ft3, 72(a1)
-; ILP32-NEXT: fld ft4, 80(a1)
-; ILP32-NEXT: fld ft5, 88(a1)
-; ILP32-NEXT: fld ft6, 96(a1)
-; ILP32-NEXT: fld ft7, 104(a1)
-; ILP32-NEXT: fld fa6, 112(a1)
-; ILP32-NEXT: fld fa7, 120(a1)
-; ILP32-NEXT: fld ft8, 128(a1)
-; ILP32-NEXT: fld ft9, 136(a1)
-; ILP32-NEXT: fld ft10, 144(a1)
-; ILP32-NEXT: fld ft11, 152(a1)
-; ILP32-NEXT: fld fs0, 160(a1)
-; ILP32-NEXT: fld fs1, 168(a1)
-; ILP32-NEXT: fld fs2, 208(a1)
-; ILP32-NEXT: fld fs3, 216(a1)
-; ILP32-NEXT: fld fs4, 224(a1)
-; ILP32-NEXT: fld fs5, 232(a1)
-; ILP32-NEXT: fld fs6, 240(a1)
-; ILP32-NEXT: fld fs7, 248(a1)
-; ILP32-NEXT: fld fs8, 176(a1)
-; ILP32-NEXT: fld fs9, 184(a1)
-; ILP32-NEXT: fld fs10, 192(a1)
-; ILP32-NEXT: fld fs11, 200(a1)
-; ILP32-NEXT: fsd fs7, 248(a1)
-; ILP32-NEXT: fsd fs6, 240(a1)
-; ILP32-NEXT: fsd fs5, 232(a1)
-; ILP32-NEXT: fsd fs4, 224(a1)
-; ILP32-NEXT: fsd fs3, 216(a1)
-; ILP32-NEXT: fsd fs2, 208(a1)
-; ILP32-NEXT: fsd fs11, 200(a1)
-; ILP32-NEXT: fsd fs10, 192(a1)
-; ILP32-NEXT: fsd fs9, 184(a1)
-; ILP32-NEXT: fsd fs8, 176(a1)
-; ILP32-NEXT: fsd fs1, 168(a1)
-; ILP32-NEXT: fsd fs0, 160(a1)
-; ILP32-NEXT: fsd ft11, 152(a1)
-; ILP32-NEXT: fsd ft10, 144(a1)
-; ILP32-NEXT: fsd ft9, 136(a1)
-; ILP32-NEXT: fsd ft8, 128(a1)
-; ILP32-NEXT: fsd fa7, 120(a1)
-; ILP32-NEXT: fsd fa6, 112(a1)
-; ILP32-NEXT: fsd ft7, 104(a1)
-; ILP32-NEXT: fsd ft6, 96(a1)
-; ILP32-NEXT: fsd ft5, 88(a1)
-; ILP32-NEXT: fsd ft4, 80(a1)
-; ILP32-NEXT: fsd ft3, 72(a1)
-; ILP32-NEXT: fsd ft2, 64(a1)
-; ILP32-NEXT: fsd ft1, 56(a1)
-; ILP32-NEXT: fsd ft0, 48(a1)
-; ILP32-NEXT: fsd fa0, 40(a1)
-; ILP32-NEXT: fsd fa1, 32(a1)
-; ILP32-NEXT: fsd fa2, 24(a1)
-; ILP32-NEXT: fsd fa3, 16(a1)
-; ILP32-NEXT: fsd fa4, %lo(var+8)(a0)
-; ILP32-NEXT: fsd fa5, %lo(var)(a0)
+; ILP32-NEXT: addi a0, a0, %lo(var)
+; ILP32-NEXT: fld fa5, 0(a0)
+; ILP32-NEXT: fld fa4, 8(a0)
+; ILP32-NEXT: fld fa3, 16(a0)
+; ILP32-NEXT: fld fa2, 24(a0)
+; ILP32-NEXT: fld fa1, 32(a0)
+; ILP32-NEXT: fld fa0, 40(a0)
+; ILP32-NEXT: fld ft0, 48(a0)
+; ILP32-NEXT: fld ft1, 56(a0)
+; ILP32-NEXT: fld ft2, 64(a0)
+; ILP32-NEXT: fld ft3, 72(a0)
+; ILP32-NEXT: fld ft4, 80(a0)
+; ILP32-NEXT: fld ft5, 88(a0)
+; ILP32-NEXT: fld ft6, 96(a0)
+; ILP32-NEXT: fld ft7, 104(a0)
+; ILP32-NEXT: fld fa6, 112(a0)
+; ILP32-NEXT: fld fa7, 120(a0)
+; ILP32-NEXT: fld ft8, 128(a0)
+; ILP32-NEXT: fld ft9, 136(a0)
+; ILP32-NEXT: fld ft10, 144(a0)
+; ILP32-NEXT: fld ft11, 152(a0)
+; ILP32-NEXT: fld fs0, 160(a0)
+; ILP32-NEXT: fld fs1, 168(a0)
+; ILP32-NEXT: fld fs2, 176(a0)
+; ILP32-NEXT: fld fs3, 184(a0)
+; ILP32-NEXT: fld fs4, 224(a0)
+; ILP32-NEXT: fld fs5, 232(a0)
+; ILP32-NEXT: fld fs6, 240(a0)
+; ILP32-NEXT: fld fs7, 248(a0)
+; ILP32-NEXT: fld fs8, 192(a0)
+; ILP32-NEXT: fld fs9, 200(a0)
+; ILP32-NEXT: fld fs10, 208(a0)
+; ILP32-NEXT: fld fs11, 216(a0)
+; ILP32-NEXT: fsd fs7, 248(a0)
+; ILP32-NEXT: fsd fs6, 240(a0)
+; ILP32-NEXT: fsd fs5, 232(a0)
+; ILP32-NEXT: fsd fs4, 224(a0)
+; ILP32-NEXT: fsd fs11, 216(a0)
+; ILP32-NEXT: fsd fs10, 208(a0)
+; ILP32-NEXT: fsd fs9, 200(a0)
+; ILP32-NEXT: fsd fs8, 192(a0)
+; ILP32-NEXT: fsd fs3, 184(a0)
+; ILP32-NEXT: fsd fs2, 176(a0)
+; ILP32-NEXT: fsd fs1, 168(a0)
+; ILP32-NEXT: fsd fs0, 160(a0)
+; ILP32-NEXT: fsd ft11, 152(a0)
+; ILP32-NEXT: fsd ft10, 144(a0)
+; ILP32-NEXT: fsd ft9, 136(a0)
+; ILP32-NEXT: fsd ft8, 128(a0)
+; ILP32-NEXT: fsd fa7, 120(a0)
+; ILP32-NEXT: fsd fa6, 112(a0)
+; ILP32-NEXT: fsd ft7, 104(a0)
+; ILP32-NEXT: fsd ft6, 96(a0)
+; ILP32-NEXT: fsd ft5, 88(a0)
+; ILP32-NEXT: fsd ft4, 80(a0)
+; ILP32-NEXT: fsd ft3, 72(a0)
+; ILP32-NEXT: fsd ft2, 64(a0)
+; ILP32-NEXT: fsd ft1, 56(a0)
+; ILP32-NEXT: fsd ft0, 48(a0)
+; ILP32-NEXT: fsd fa0, 40(a0)
+; ILP32-NEXT: fsd fa1, 32(a0)
+; ILP32-NEXT: fsd fa2, 24(a0)
+; ILP32-NEXT: fsd fa3, 16(a0)
+; ILP32-NEXT: fsd fa4, 8(a0)
+; ILP32-NEXT: fsd fa5, 0(a0)
; ILP32-NEXT: ret
;
; LP64-LABEL: callee:
; LP64: # %bb.0:
; LP64-NEXT: lui a0, %hi(var)
-; LP64-NEXT: fld fa5, %lo(var)(a0)
-; LP64-NEXT: fld fa4, %lo(var+8)(a0)
-; LP64-NEXT: addi a1, a0, %lo(var)
-; LP64-NEXT: fld fa3, 16(a1)
-; LP64-NEXT: fld fa2, 24(a1)
-; LP64-NEXT: fld fa1, 32(a1)
-; LP64-NEXT: fld fa0, 40(a1)
-; LP64-NEXT: fld ft0, 48(a1)
-; LP64-NEXT: fld ft1, 56(a1)
-; LP64-NEXT: fld ft2, 64(a1)
-; LP64-NEXT: fld ft3, 72(a1)
-; LP64-NEXT: fld ft4, 80(a1)
-; LP64-NEXT: fld ft5, 88(a1)
-; LP64-NEXT: fld ft6, 96(a1)
-; LP64-NEXT: fld ft7, 104(a1)
-; LP64-NEXT: fld fa6, 112(a1)
-; LP64-NEXT: fld fa7, 120(a1)
-; LP64-NEXT: fld ft8, 128(a1)
-; LP64-NEXT: fld ft9, 136(a1)
-; LP64-NEXT: fld ft10, 144(a1)
-; LP64-NEXT: fld ft11, 152(a1)
-; LP64-NEXT: fld fs0, 160(a1)
-; LP64-NEXT: fld fs1, 168(a1)
-; LP64-NEXT: fld fs2, 208(a1)
-; LP64-NEXT: fld fs3, 216(a1)
-; LP64-NEXT: fld fs4, 224(a1)
-; LP64-NEXT: fld fs5, 232(a1)
-; LP64-NEXT: fld fs6, 240(a1)
-; LP64-NEXT: fld fs7, 248(a1)
-; LP64-NEXT: fld fs8, 176(a1)
-; LP64-NEXT: fld fs9, 184(a1)
-; LP64-NEXT: fld fs10, 192(a1)
-; LP64-NEXT: fld fs11, 200(a1)
-; LP64-NEXT: fsd fs7, 248(a1)
-; LP64-NEXT: fsd fs6, 240(a1)
-; LP64-NEXT: fsd fs5, 232(a1)
-; LP64-NEXT: fsd fs4, 224(a1)
-; LP64-NEXT: fsd fs3, 216(a1)
-; LP64-NEXT: fsd fs2, 208(a1)
-; LP64-NEXT: fsd fs11, 200(a1)
-; LP64-NEXT: fsd fs10, 192(a1)
-; LP64-NEXT: fsd fs9, 184(a1)
-; LP64-NEXT: fsd fs8, 176(a1)
-; LP64-NEXT: fsd fs1, 168(a1)
-; LP64-NEXT: fsd fs0, 160(a1)
-; LP64-NEXT: fsd ft11, 152(a1)
-; LP64-NEXT: fsd ft10, 144(a1)
-; LP64-NEXT: fsd ft9, 136(a1)
-; LP64-NEXT: fsd ft8, 128(a1)
-; LP64-NEXT: fsd fa7, 120(a1)
-; LP64-NEXT: fsd fa6, 112(a1)
-; LP64-NEXT: fsd ft7, 104(a1)
-; LP64-NEXT: fsd ft6, 96(a1)
-; LP64-NEXT: fsd ft5, 88(a1)
-; LP64-NEXT: fsd ft4, 80(a1)
-; LP64-NEXT: fsd ft3, 72(a1)
-; LP64-NEXT: fsd ft2, 64(a1)
-; LP64-NEXT: fsd ft1, 56(a1)
-; LP64-NEXT: fsd ft0, 48(a1)
-; LP64-NEXT: fsd fa0, 40(a1)
-; LP64-NEXT: fsd fa1, 32(a1)
-; LP64-NEXT: fsd fa2, 24(a1)
-; LP64-NEXT: fsd fa3, 16(a1)
-; LP64-NEXT: fsd fa4, %lo(var+8)(a0)
-; LP64-NEXT: fsd fa5, %lo(var)(a0)
+; LP64-NEXT: addi a0, a0, %lo(var)
+; LP64-NEXT: fld fa5, 0(a0)
+; LP64-NEXT: fld fa4, 8(a0)
+; LP64-NEXT: fld fa3, 16(a0)
+; LP64-NEXT: fld fa2, 24(a0)
+; LP64-NEXT: fld fa1, 32(a0)
+; LP64-NEXT: fld fa0, 40(a0)
+; LP64-NEXT: fld ft0, 48(a0)
+; LP64-NEXT: fld ft1, 56(a0)
+; LP64-NEXT: fld ft2, 64(a0)
+; LP64-NEXT: fld ft3, 72(a0)
+; LP64-NEXT: fld ft4, 80(a0)
+; LP64-NEXT: fld ft5, 88(a0)
+; LP64-NEXT: fld ft6, 96(a0)
+; LP64-NEXT: fld ft7, 104(a0)
+; LP64-NEXT: fld fa6, 112(a0)
+; LP64-NEXT: fld fa7, 120(a0)
+; LP64-NEXT: fld ft8, 128(a0)
+; LP64-NEXT: fld ft9, 136(a0)
+; LP64-NEXT: fld ft10, 144(a0)
+; LP64-NEXT: fld ft11, 152(a0)
+; LP64-NEXT: fld fs0, 160(a0)
+; LP64-NEXT: fld fs1, 168(a0)
+; LP64-NEXT: fld fs2, 176(a0)
+; LP64-NEXT: fld fs3, 184(a0)
+; LP64-NEXT: fld fs4, 224(a0)
+; LP64-NEXT: fld fs5, 232(a0)
+; LP64-NEXT: fld fs6, 240(a0)
+; LP64-NEXT: fld fs7, 248(a0)
+; LP64-NEXT: fld fs8, 192(a0)
+; LP64-NEXT: fld fs9, 200(a0)
+; LP64-NEXT: fld fs10, 208(a0)
+; LP64-NEXT: fld fs11, 216(a0)
+; LP64-NEXT: fsd fs7, 248(a0)
+; LP64-NEXT: fsd fs6, 240(a0)
+; LP64-NEXT: fsd fs5, 232(a0)
+; LP64-NEXT: fsd fs4, 224(a0)
+; LP64-NEXT: fsd fs11, 216(a0)
+; LP64-NEXT: fsd fs10, 208(a0)
+; LP64-NEXT: fsd fs9, 200(a0)
+; LP64-NEXT: fsd fs8, 192(a0)
+; LP64-NEXT: fsd fs3, 184(a0)
+; LP64-NEXT: fsd fs2, 176(a0)
+; LP64-NEXT: fsd fs1, 168(a0)
+; LP64-NEXT: fsd fs0, 160(a0)
+; LP64-NEXT: fsd ft11, 152(a0)
+; LP64-NEXT: fsd ft10, 144(a0)
+; LP64-NEXT: fsd ft9, 136(a0)
+; LP64-NEXT: fsd ft8, 128(a0)
+; LP64-NEXT: fsd fa7, 120(a0)
+; LP64-NEXT: fsd fa6, 112(a0)
+; LP64-NEXT: fsd ft7, 104(a0)
+; LP64-NEXT: fsd ft6, 96(a0)
+; LP64-NEXT: fsd ft5, 88(a0)
+; LP64-NEXT: fsd ft4, 80(a0)
+; LP64-NEXT: fsd ft3, 72(a0)
+; LP64-NEXT: fsd ft2, 64(a0)
+; LP64-NEXT: fsd ft1, 56(a0)
+; LP64-NEXT: fsd ft0, 48(a0)
+; LP64-NEXT: fsd fa0, 40(a0)
+; LP64-NEXT: fsd fa1, 32(a0)
+; LP64-NEXT: fsd fa2, 24(a0)
+; LP64-NEXT: fsd fa3, 16(a0)
+; LP64-NEXT: fsd fa4, 8(a0)
+; LP64-NEXT: fsd fa5, 0(a0)
; LP64-NEXT: ret
;
; LP64E-LABEL: callee:
; LP64E: # %bb.0:
; LP64E-NEXT: lui a0, %hi(var)
-; LP64E-NEXT: fld fa5, %lo(var)(a0)
-; LP64E-NEXT: fld fa4, %lo(var+8)(a0)
-; LP64E-NEXT: addi a1, a0, %lo(var)
-; LP64E-NEXT: fld fa3, 16(a1)
-; LP64E-NEXT: fld fa2, 24(a1)
-; LP64E-NEXT: fld fa1, 32(a1)
-; LP64E-NEXT: fld fa0, 40(a1)
-; LP64E-NEXT: fld ft0, 48(a1)
-; LP64E-NEXT: fld ft1, 56(a1)
-; LP64E-NEXT: fld ft2, 64(a1)
-; LP64E-NEXT: fld ft3, 72(a1)
-; LP64E-NEXT: fld ft4, 80(a1)
-; LP64E-NEXT: fld ft5, 88(a1)
-; LP64E-NEXT: fld ft6, 96(a1)
-; LP64E-NEXT: fld ft7, 104(a1)
-; LP64E-NEXT: fld fa6, 112(a1)
-; LP64E-NEXT: fld fa7, 120(a1)
-; LP64E-NEXT: fld ft8, 128(a1)
-; LP64E-NEXT: fld ft9, 136(a1)
-; LP64E-NEXT: fld ft10, 144(a1)
-; LP64E-NEXT: fld ft11, 152(a1)
-; LP64E-NEXT: fld fs0, 160(a1)
-; LP64E-NEXT: fld fs1, 168(a1)
-; LP64E-NEXT: fld fs2, 208(a1)
-; LP64E-NEXT: fld fs3, 216(a1)
-; LP64E-NEXT: fld fs4, 224(a1)
-; LP64E-NEXT: fld fs5, 232(a1)
-; LP64E-NEXT: fld fs6, 240(a1)
-; LP64E-NEXT: fld fs7, 248(a1)
-; LP64E-NEXT: fld fs8, 176(a1)
-; LP64E-NEXT: fld fs9, 184(a1)
-; LP64E-NEXT: fld fs10, 192(a1)
-; LP64E-NEXT: fld fs11, 200(a1)
-; LP64E-NEXT: fsd fs7, 248(a1)
-; LP64E-NEXT: fsd fs6, 240(a1)
-; LP64E-NEXT: fsd fs5, 232(a1)
-; LP64E-NEXT: fsd fs4, 224(a1)
-; LP64E-NEXT: fsd fs3, 216(a1)
-; LP64E-NEXT: fsd fs2, 208(a1)
-; LP64E-NEXT: fsd fs11, 200(a1)
-; LP64E-NEXT: fsd fs10, 192(a1)
-; LP64E-NEXT: fsd fs9, 184(a1)
-; LP64E-NEXT: fsd fs8, 176(a1)
-; LP64E-NEXT: fsd fs1, 168(a1)
-; LP64E-NEXT: fsd fs0, 160(a1)
-; LP64E-NEXT: fsd ft11, 152(a1)
-; LP64E-NEXT: fsd ft10, 144(a1)
-; LP64E-NEXT: fsd ft9, 136(a1)
-; LP64E-NEXT: fsd ft8, 128(a1)
-; LP64E-NEXT: fsd fa7, 120(a1)
-; LP64E-NEXT: fsd fa6, 112(a1)
-; LP64E-NEXT: fsd ft7, 104(a1)
-; LP64E-NEXT: fsd ft6, 96(a1)
-; LP64E-NEXT: fsd ft5, 88(a1)
-; LP64E-NEXT: fsd ft4, 80(a1)
-; LP64E-NEXT: fsd ft3, 72(a1)
-; LP64E-NEXT: fsd ft2, 64(a1)
-; LP64E-NEXT: fsd ft1, 56(a1)
-; LP64E-NEXT: fsd ft0, 48(a1)
-; LP64E-NEXT: fsd fa0, 40(a1)
-; LP64E-NEXT: fsd fa1, 32(a1)
-; LP64E-NEXT: fsd fa2, 24(a1)
-; LP64E-NEXT: fsd fa3, 16(a1)
-; LP64E-NEXT: fsd fa4, %lo(var+8)(a0)
-; LP64E-NEXT: fsd fa5, %lo(var)(a0)
+; LP64E-NEXT: addi a0, a0, %lo(var)
+; LP64E-NEXT: fld fa5, 0(a0)
+; LP64E-NEXT: fld fa4, 8(a0)
+; LP64E-NEXT: fld fa3, 16(a0)
+; LP64E-NEXT: fld fa2, 24(a0)
+; LP64E-NEXT: fld fa1, 32(a0)
+; LP64E-NEXT: fld fa0, 40(a0)
+; LP64E-NEXT: fld ft0, 48(a0)
+; LP64E-NEXT: fld ft1, 56(a0)
+; LP64E-NEXT: fld ft2, 64(a0)
+; LP64E-NEXT: fld ft3, 72(a0)
+; LP64E-NEXT: fld ft4, 80(a0)
+; LP64E-NEXT: fld ft5, 88(a0)
+; LP64E-NEXT: fld ft6, 96(a0)
+; LP64E-NEXT: fld ft7, 104(a0)
+; LP64E-NEXT: fld fa6, 112(a0)
+; LP64E-NEXT: fld fa7, 120(a0)
+; LP64E-NEXT: fld ft8, 128(a0)
+; LP64E-NEXT: fld ft9, 136(a0)
+; LP64E-NEXT: fld ft10, 144(a0)
+; LP64E-NEXT: fld ft11, 152(a0)
+; LP64E-NEXT: fld fs0, 160(a0)
+; LP64E-NEXT: fld fs1, 168(a0)
+; LP64E-NEXT: fld fs2, 176(a0)
+; LP64E-NEXT: fld fs3, 184(a0)
+; LP64E-NEXT: fld fs4, 224(a0)
+; LP64E-NEXT: fld fs5, 232(a0)
+; LP64E-NEXT: fld fs6, 240(a0)
+; LP64E-NEXT: fld fs7, 248(a0)
+; LP64E-NEXT: fld fs8, 192(a0)
+; LP64E-NEXT: fld fs9, 200(a0)
+; LP64E-NEXT: fld fs10, 208(a0)
+; LP64E-NEXT: fld fs11, 216(a0)
+; LP64E-NEXT: fsd fs7, 248(a0)
+; LP64E-NEXT: fsd fs6, 240(a0)
+; LP64E-NEXT: fsd fs5, 232(a0)
+; LP64E-NEXT: fsd fs4, 224(a0)
+; LP64E-NEXT: fsd fs11, 216(a0)
+; LP64E-NEXT: fsd fs10, 208(a0)
+; LP64E-NEXT: fsd fs9, 200(a0)
+; LP64E-NEXT: fsd fs8, 192(a0)
+; LP64E-NEXT: fsd fs3, 184(a0)
+; LP64E-NEXT: fsd fs2, 176(a0)
+; LP64E-NEXT: fsd fs1, 168(a0)
+; LP64E-NEXT: fsd fs0, 160(a0)
+; LP64E-NEXT: fsd ft11, 152(a0)
+; LP64E-NEXT: fsd ft10, 144(a0)
+; LP64E-NEXT: fsd ft9, 136(a0)
+; LP64E-NEXT: fsd ft8, 128(a0)
+; LP64E-NEXT: fsd fa7, 120(a0)
+; LP64E-NEXT: fsd fa6, 112(a0)
+; LP64E-NEXT: fsd ft7, 104(a0)
+; LP64E-NEXT: fsd ft6, 96(a0)
+; LP64E-NEXT: fsd ft5, 88(a0)
+; LP64E-NEXT: fsd ft4, 80(a0)
+; LP64E-NEXT: fsd ft3, 72(a0)
+; LP64E-NEXT: fsd ft2, 64(a0)
+; LP64E-NEXT: fsd ft1, 56(a0)
+; LP64E-NEXT: fsd ft0, 48(a0)
+; LP64E-NEXT: fsd fa0, 40(a0)
+; LP64E-NEXT: fsd fa1, 32(a0)
+; LP64E-NEXT: fsd fa2, 24(a0)
+; LP64E-NEXT: fsd fa3, 16(a0)
+; LP64E-NEXT: fsd fa4, 8(a0)
+; LP64E-NEXT: fsd fa5, 0(a0)
; LP64E-NEXT: ret
;
; ILP32D-LABEL: callee:
@@ -245,71 +245,71 @@ define void @callee() nounwind {
; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui a0, %hi(var)
-; ILP32D-NEXT: fld fa5, %lo(var)(a0)
-; ILP32D-NEXT: fld fa4, %lo(var+8)(a0)
-; ILP32D-NEXT: addi a1, a0, %lo(var)
-; ILP32D-NEXT: fld fa3, 16(a1)
-; ILP32D-NEXT: fld fa2, 24(a1)
-; ILP32D-NEXT: fld fa1, 32(a1)
-; ILP32D-NEXT: fld fa0, 40(a1)
-; ILP32D-NEXT: fld ft0, 48(a1)
-; ILP32D-NEXT: fld ft1, 56(a1)
-; ILP32D-NEXT: fld ft2, 64(a1)
-; ILP32D-NEXT: fld ft3, 72(a1)
-; ILP32D-NEXT: fld ft4, 80(a1)
-; ILP32D-NEXT: fld ft5, 88(a1)
-; ILP32D-NEXT: fld ft6, 96(a1)
-; ILP32D-NEXT: fld ft7, 104(a1)
-; ILP32D-NEXT: fld fa6, 112(a1)
-; ILP32D-NEXT: fld fa7, 120(a1)
-; ILP32D-NEXT: fld ft8, 128(a1)
-; ILP32D-NEXT: fld ft9, 136(a1)
-; ILP32D-NEXT: fld ft10, 144(a1)
-; ILP32D-NEXT: fld ft11, 152(a1)
-; ILP32D-NEXT: fld fs0, 160(a1)
-; ILP32D-NEXT: fld fs1, 168(a1)
-; ILP32D-NEXT: fld fs2, 208(a1)
-; ILP32D-NEXT: fld fs3, 216(a1)
-; ILP32D-NEXT: fld fs4, 224(a1)
-; ILP32D-NEXT: fld fs5, 232(a1)
-; ILP32D-NEXT: fld fs6, 240(a1)
-; ILP32D-NEXT: fld fs7, 248(a1)
-; ILP32D-NEXT: fld fs8, 176(a1)
-; ILP32D-NEXT: fld fs9, 184(a1)
-; ILP32D-NEXT: fld fs10, 192(a1)
-; ILP32D-NEXT: fld fs11, 200(a1)
-; ILP32D-NEXT: fsd fs7, 248(a1)
-; ILP32D-NEXT: fsd fs6, 240(a1)
-; ILP32D-NEXT: fsd fs5, 232(a1)
-; ILP32D-NEXT: fsd fs4, 224(a1)
-; ILP32D-NEXT: fsd fs3, 216(a1)
-; ILP32D-NEXT: fsd fs2, 208(a1)
-; ILP32D-NEXT: fsd fs11, 200(a1)
-; ILP32D-NEXT: fsd fs10, 192(a1)
-; ILP32D-NEXT: fsd fs9, 184(a1)
-; ILP32D-NEXT: fsd fs8, 176(a1)
-; ILP32D-NEXT: fsd fs1, 168(a1)
-; ILP32D-NEXT: fsd fs0, 160(a1)
-; ILP32D-NEXT: fsd ft11, 152(a1)
-; ILP32D-NEXT: fsd ft10, 144(a1)
-; ILP32D-NEXT: fsd ft9, 136(a1)
-; ILP32D-NEXT: fsd ft8, 128(a1)
-; ILP32D-NEXT: fsd fa7, 120(a1)
-; ILP32D-NEXT: fsd fa6, 112(a1)
-; ILP32D-NEXT: fsd ft7, 104(a1)
-; ILP32D-NEXT: fsd ft6, 96(a1)
-; ILP32D-NEXT: fsd ft5, 88(a1)
-; ILP32D-NEXT: fsd ft4, 80(a1)
-; ILP32D-NEXT: fsd ft3, 72(a1)
-; ILP32D-NEXT: fsd ft2, 64(a1)
-; ILP32D-NEXT: fsd ft1, 56(a1)
-; ILP32D-NEXT: fsd ft0, 48(a1)
-; ILP32D-NEXT: fsd fa0, 40(a1)
-; ILP32D-NEXT: fsd fa1, 32(a1)
-; ILP32D-NEXT: fsd fa2, 24(a1)
-; ILP32D-NEXT: fsd fa3, 16(a1)
-; ILP32D-NEXT: fsd fa4, %lo(var+8)(a0)
-; ILP32D-NEXT: fsd fa5, %lo(var)(a0)
+; ILP32D-NEXT: addi a0, a0, %lo(var)
+; ILP32D-NEXT: fld fa5, 0(a0)
+; ILP32D-NEXT: fld fa4, 8(a0)
+; ILP32D-NEXT: fld fa3, 16(a0)
+; ILP32D-NEXT: fld fa2, 24(a0)
+; ILP32D-NEXT: fld fa1, 32(a0)
+; ILP32D-NEXT: fld fa0, 40(a0)
+; ILP32D-NEXT: fld ft0, 48(a0)
+; ILP32D-NEXT: fld ft1, 56(a0)
+; ILP32D-NEXT: fld ft2, 64(a0)
+; ILP32D-NEXT: fld ft3, 72(a0)
+; ILP32D-NEXT: fld ft4, 80(a0)
+; ILP32D-NEXT: fld ft5, 88(a0)
+; ILP32D-NEXT: fld ft6, 96(a0)
+; ILP32D-NEXT: fld ft7, 104(a0)
+; ILP32D-NEXT: fld fa6, 112(a0)
+; ILP32D-NEXT: fld fa7, 120(a0)
+; ILP32D-NEXT: fld ft8, 128(a0)
+; ILP32D-NEXT: fld ft9, 136(a0)
+; ILP32D-NEXT: fld ft10, 144(a0)
+; ILP32D-NEXT: fld ft11, 152(a0)
+; ILP32D-NEXT: fld fs0, 160(a0)
+; ILP32D-NEXT: fld fs1, 168(a0)
+; ILP32D-NEXT: fld fs2, 176(a0)
+; ILP32D-NEXT: fld fs3, 184(a0)
+; ILP32D-NEXT: fld fs4, 224(a0)
+; ILP32D-NEXT: fld fs5, 232(a0)
+; ILP32D-NEXT: fld fs6, 240(a0)
+; ILP32D-NEXT: fld fs7, 248(a0)
+; ILP32D-NEXT: fld fs8, 192(a0)
+; ILP32D-NEXT: fld fs9, 200(a0)
+; ILP32D-NEXT: fld fs10, 208(a0)
+; ILP32D-NEXT: fld fs11, 216(a0)
+; ILP32D-NEXT: fsd fs7, 248(a0)
+; ILP32D-NEXT: fsd fs6, 240(a0)
+; ILP32D-NEXT: fsd fs5, 232(a0)
+; ILP32D-NEXT: fsd fs4, 224(a0)
+; ILP32D-NEXT: fsd fs11, 216(a0)
+; ILP32D-NEXT: fsd fs10, 208(a0)
+; ILP32D-NEXT: fsd fs9, 200(a0)
+; ILP32D-NEXT: fsd fs8, 192(a0)
+; ILP32D-NEXT: fsd fs3, 184(a0)
+; ILP32D-NEXT: fsd fs2, 176(a0)
+; ILP32D-NEXT: fsd fs1, 168(a0)
+; ILP32D-NEXT: fsd fs0, 160(a0)
+; ILP32D-NEXT: fsd ft11, 152(a0)
+; ILP32D-NEXT: fsd ft10, 144(a0)
+; ILP32D-NEXT: fsd ft9, 136(a0)
+; ILP32D-NEXT: fsd ft8, 128(a0)
+; ILP32D-NEXT: fsd fa7, 120(a0)
+; ILP32D-NEXT: fsd fa6, 112(a0)
+; ILP32D-NEXT: fsd ft7, 104(a0)
+; ILP32D-NEXT: fsd ft6, 96(a0)
+; ILP32D-NEXT: fsd ft5, 88(a0)
+; ILP32D-NEXT: fsd ft4, 80(a0)
+; ILP32D-NEXT: fsd ft3, 72(a0)
+; ILP32D-NEXT: fsd ft2, 64(a0)
+; ILP32D-NEXT: fsd ft1, 56(a0)
+; ILP32D-NEXT: fsd ft0, 48(a0)
+; ILP32D-NEXT: fsd fa0, 40(a0)
+; ILP32D-NEXT: fsd fa1, 32(a0)
+; ILP32D-NEXT: fsd fa2, 24(a0)
+; ILP32D-NEXT: fsd fa3, 16(a0)
+; ILP32D-NEXT: fsd fa4, 8(a0)
+; ILP32D-NEXT: fsd fa5, 0(a0)
; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
@@ -341,71 +341,71 @@ define void @callee() nounwind {
; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui a0, %hi(var)
-; LP64D-NEXT: fld fa5, %lo(var)(a0)
-; LP64D-NEXT: fld fa4, %lo(var+8)(a0)
-; LP64D-NEXT: addi a1, a0, %lo(var)
-; LP64D-NEXT: fld fa3, 16(a1)
-; LP64D-NEXT: fld fa2, 24(a1)
-; LP64D-NEXT: fld fa1, 32(a1)
-; LP64D-NEXT: fld fa0, 40(a1)
-; LP64D-NEXT: fld ft0, 48(a1)
-; LP64D-NEXT: fld ft1, 56(a1)
-; LP64D-NEXT: fld ft2, 64(a1)
-; LP64D-NEXT: fld ft3, 72(a1)
-; LP64D-NEXT: fld ft4, 80(a1)
-; LP64D-NEXT: fld ft5, 88(a1)
-; LP64D-NEXT: fld ft6, 96(a1)
-; LP64D-NEXT: fld ft7, 104(a1)
-; LP64D-NEXT: fld fa6, 112(a1)
-; LP64D-NEXT: fld fa7, 120(a1)
-; LP64D-NEXT: fld ft8, 128(a1)
-; LP64D-NEXT: fld ft9, 136(a1)
-; LP64D-NEXT: fld ft10, 144(a1)
-; LP64D-NEXT: fld ft11, 152(a1)
-; LP64D-NEXT: fld fs0, 160(a1)
-; LP64D-NEXT: fld fs1, 168(a1)
-; LP64D-NEXT: fld fs2, 208(a1)
-; LP64D-NEXT: fld fs3, 216(a1)
-; LP64D-NEXT: fld fs4, 224(a1)
-; LP64D-NEXT: fld fs5, 232(a1)
-; LP64D-NEXT: fld fs6, 240(a1)
-; LP64D-NEXT: fld fs7, 248(a1)
-; LP64D-NEXT: fld fs8, 176(a1)
-; LP64D-NEXT: fld fs9, 184(a1)
-; LP64D-NEXT: fld fs10, 192(a1)
-; LP64D-NEXT: fld fs11, 200(a1)
-; LP64D-NEXT: fsd fs7, 248(a1)
-; LP64D-NEXT: fsd fs6, 240(a1)
-; LP64D-NEXT: fsd fs5, 232(a1)
-; LP64D-NEXT: fsd fs4, 224(a1)
-; LP64D-NEXT: fsd fs3, 216(a1)
-; LP64D-NEXT: fsd fs2, 208(a1)
-; LP64D-NEXT: fsd fs11, 200(a1)
-; LP64D-NEXT: fsd fs10, 192(a1)
-; LP64D-NEXT: fsd fs9, 184(a1)
-; LP64D-NEXT: fsd fs8, 176(a1)
-; LP64D-NEXT: fsd fs1, 168(a1)
-; LP64D-NEXT: fsd fs0, 160(a1)
-; LP64D-NEXT: fsd ft11, 152(a1)
-; LP64D-NEXT: fsd ft10, 144(a1)
-; LP64D-NEXT: fsd ft9, 136(a1)
-; LP64D-NEXT: fsd ft8, 128(a1)
-; LP64D-NEXT: fsd fa7, 120(a1)
-; LP64D-NEXT: fsd fa6, 112(a1)
-; LP64D-NEXT: fsd ft7, 104(a1)
-; LP64D-NEXT: fsd ft6, 96(a1)
-; LP64D-NEXT: fsd ft5, 88(a1)
-; LP64D-NEXT: fsd ft4, 80(a1)
-; LP64D-NEXT: fsd ft3, 72(a1)
-; LP64D-NEXT: fsd ft2, 64(a1)
-; LP64D-NEXT: fsd ft1, 56(a1)
-; LP64D-NEXT: fsd ft0, 48(a1)
-; LP64D-NEXT: fsd fa0, 40(a1)
-; LP64D-NEXT: fsd fa1, 32(a1)
-; LP64D-NEXT: fsd fa2, 24(a1)
-; LP64D-NEXT: fsd fa3, 16(a1)
-; LP64D-NEXT: fsd fa4, %lo(var+8)(a0)
-; LP64D-NEXT: fsd fa5, %lo(var)(a0)
+; LP64D-NEXT: addi a0, a0, %lo(var)
+; LP64D-NEXT: fld fa5, 0(a0)
+; LP64D-NEXT: fld fa4, 8(a0)
+; LP64D-NEXT: fld fa3, 16(a0)
+; LP64D-NEXT: fld fa2, 24(a0)
+; LP64D-NEXT: fld fa1, 32(a0)
+; LP64D-NEXT: fld fa0, 40(a0)
+; LP64D-NEXT: fld ft0, 48(a0)
+; LP64D-NEXT: fld ft1, 56(a0)
+; LP64D-NEXT: fld ft2, 64(a0)
+; LP64D-NEXT: fld ft3, 72(a0)
+; LP64D-NEXT: fld ft4, 80(a0)
+; LP64D-NEXT: fld ft5, 88(a0)
+; LP64D-NEXT: fld ft6, 96(a0)
+; LP64D-NEXT: fld ft7, 104(a0)
+; LP64D-NEXT: fld fa6, 112(a0)
+; LP64D-NEXT: fld fa7, 120(a0)
+; LP64D-NEXT: fld ft8, 128(a0)
+; LP64D-NEXT: fld ft9, 136(a0)
+; LP64D-NEXT: fld ft10, 144(a0)
+; LP64D-NEXT: fld ft11, 152(a0)
+; LP64D-NEXT: fld fs0, 160(a0)
+; LP64D-NEXT: fld fs1, 168(a0)
+; LP64D-NEXT: fld fs2, 176(a0)
+; LP64D-NEXT: fld fs3, 184(a0)
+; LP64D-NEXT: fld fs4, 224(a0)
+; LP64D-NEXT: fld fs5, 232(a0)
+; LP64D-NEXT: fld fs6, 240(a0)
+; LP64D-NEXT: fld fs7, 248(a0)
+; LP64D-NEXT: fld fs8, 192(a0)
+; LP64D-NEXT: fld fs9, 200(a0)
+; LP64D-NEXT: fld fs10, 208(a0)
+; LP64D-NEXT: fld fs11, 216(a0)
+; LP64D-NEXT: fsd fs7, 248(a0)
+; LP64D-NEXT: fsd fs6, 240(a0)
+; LP64D-NEXT: fsd fs5, 232(a0)
+; LP64D-NEXT: fsd fs4, 224(a0)
+; LP64D-NEXT: fsd fs11, 216(a0)
+; LP64D-NEXT: fsd fs10, 208(a0)
+; LP64D-NEXT: fsd fs9, 200(a0)
+; LP64D-NEXT: fsd fs8, 192(a0)
+; LP64D-NEXT: fsd fs3, 184(a0)
+; LP64D-NEXT: fsd fs2, 176(a0)
+; LP64D-NEXT: fsd fs1, 168(a0)
+; LP64D-NEXT: fsd fs0, 160(a0)
+; LP64D-NEXT: fsd ft11, 152(a0)
+; LP64D-NEXT: fsd ft10, 144(a0)
+; LP64D-NEXT: fsd ft9, 136(a0)
+; LP64D-NEXT: fsd ft8, 128(a0)
+; LP64D-NEXT: fsd fa7, 120(a0)
+; LP64D-NEXT: fsd fa6, 112(a0)
+; LP64D-NEXT: fsd ft7, 104(a0)
+; LP64D-NEXT: fsd ft6, 96(a0)
+; LP64D-NEXT: fsd ft5, 88(a0)
+; LP64D-NEXT: fsd ft4, 80(a0)
+; LP64D-NEXT: fsd ft3, 72(a0)
+; LP64D-NEXT: fsd ft2, 64(a0)
+; LP64D-NEXT: fsd ft1, 56(a0)
+; LP64D-NEXT: fsd ft0, 48(a0)
+; LP64D-NEXT: fsd fa0, 40(a0)
+; LP64D-NEXT: fsd fa1, 32(a0)
+; LP64D-NEXT: fsd fa2, 24(a0)
+; LP64D-NEXT: fsd fa3, 16(a0)
+; LP64D-NEXT: fsd fa4, 8(a0)
+; LP64D-NEXT: fsd fa5, 0(a0)
; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
@@ -438,428 +438,422 @@ define void @caller() nounwind {
; ILP32-NEXT: addi sp, sp, -272
; ILP32-NEXT: sw ra, 268(sp) # 4-byte Folded Spill
; ILP32-NEXT: sw s0, 264(sp) # 4-byte Folded Spill
-; ILP32-NEXT: sw s1, 260(sp) # 4-byte Folded Spill
; ILP32-NEXT: lui s0, %hi(var)
-; ILP32-NEXT: fld fa5, %lo(var)(s0)
+; ILP32-NEXT: addi s0, s0, %lo(var)
+; ILP32-NEXT: fld fa5, 0(s0)
+; ILP32-NEXT: fsd fa5, 256(sp) # 8-byte Folded Spill
+; ILP32-NEXT: fld fa5, 8(s0)
; ILP32-NEXT: fsd fa5, 248(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, %lo(var+8)(s0)
+; ILP32-NEXT: fld fa5, 16(s0)
; ILP32-NEXT: fsd fa5, 240(sp) # 8-byte Folded Spill
-; ILP32-NEXT: addi s1, s0, %lo(var)
-; ILP32-NEXT: fld fa5, 16(s1)
+; ILP32-NEXT: fld fa5, 24(s0)
; ILP32-NEXT: fsd fa5, 232(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 24(s1)
+; ILP32-NEXT: fld fa5, 32(s0)
; ILP32-NEXT: fsd fa5, 224(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 32(s1)
+; ILP32-NEXT: fld fa5, 40(s0)
; ILP32-NEXT: fsd fa5, 216(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 40(s1)
+; ILP32-NEXT: fld fa5, 48(s0)
; ILP32-NEXT: fsd fa5, 208(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 48(s1)
+; ILP32-NEXT: fld fa5, 56(s0)
; ILP32-NEXT: fsd fa5, 200(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 56(s1)
+; ILP32-NEXT: fld fa5, 64(s0)
; ILP32-NEXT: fsd fa5, 192(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 64(s1)
+; ILP32-NEXT: fld fa5, 72(s0)
; ILP32-NEXT: fsd fa5, 184(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 72(s1)
+; ILP32-NEXT: fld fa5, 80(s0)
; ILP32-NEXT: fsd fa5, 176(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 80(s1)
+; ILP32-NEXT: fld fa5, 88(s0)
; ILP32-NEXT: fsd fa5, 168(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 88(s1)
+; ILP32-NEXT: fld fa5, 96(s0)
; ILP32-NEXT: fsd fa5, 160(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 96(s1)
+; ILP32-NEXT: fld fa5, 104(s0)
; ILP32-NEXT: fsd fa5, 152(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 104(s1)
+; ILP32-NEXT: fld fa5, 112(s0)
; ILP32-NEXT: fsd fa5, 144(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 112(s1)
+; ILP32-NEXT: fld fa5, 120(s0)
; ILP32-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 120(s1)
+; ILP32-NEXT: fld fa5, 128(s0)
; ILP32-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 128(s1)
+; ILP32-NEXT: fld fa5, 136(s0)
; ILP32-NEXT: fsd fa5, 120(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 136(s1)
+; ILP32-NEXT: fld fa5, 144(s0)
; ILP32-NEXT: fsd fa5, 112(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 144(s1)
+; ILP32-NEXT: fld fa5, 152(s0)
; ILP32-NEXT: fsd fa5, 104(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 152(s1)
+; ILP32-NEXT: fld fa5, 160(s0)
; ILP32-NEXT: fsd fa5, 96(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 160(s1)
+; ILP32-NEXT: fld fa5, 168(s0)
; ILP32-NEXT: fsd fa5, 88(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 168(s1)
+; ILP32-NEXT: fld fa5, 176(s0)
; ILP32-NEXT: fsd fa5, 80(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 176(s1)
+; ILP32-NEXT: fld fa5, 184(s0)
; ILP32-NEXT: fsd fa5, 72(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 184(s1)
+; ILP32-NEXT: fld fa5, 192(s0)
; ILP32-NEXT: fsd fa5, 64(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 192(s1)
+; ILP32-NEXT: fld fa5, 200(s0)
; ILP32-NEXT: fsd fa5, 56(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 200(s1)
+; ILP32-NEXT: fld fa5, 208(s0)
; ILP32-NEXT: fsd fa5, 48(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 208(s1)
+; ILP32-NEXT: fld fa5, 216(s0)
; ILP32-NEXT: fsd fa5, 40(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 216(s1)
+; ILP32-NEXT: fld fa5, 224(s0)
; ILP32-NEXT: fsd fa5, 32(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 224(s1)
+; ILP32-NEXT: fld fa5, 232(s0)
; ILP32-NEXT: fsd fa5, 24(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 232(s1)
+; ILP32-NEXT: fld fa5, 240(s0)
; ILP32-NEXT: fsd fa5, 16(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 240(s1)
+; ILP32-NEXT: fld fa5, 248(s0)
; ILP32-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill
-; ILP32-NEXT: fld fa5, 248(s1)
-; ILP32-NEXT: fsd fa5, 0(sp) # 8-byte Folded Spill
; ILP32-NEXT: call callee
-; ILP32-NEXT: fld fa5, 0(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 248(s1)
; ILP32-NEXT: fld fa5, 8(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 240(s1)
+; ILP32-NEXT: fsd fa5, 248(s0)
; ILP32-NEXT: fld fa5, 16(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 232(s1)
+; ILP32-NEXT: fsd fa5, 240(s0)
; ILP32-NEXT: fld fa5, 24(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 224(s1)
+; ILP32-NEXT: fsd fa5, 232(s0)
; ILP32-NEXT: fld fa5, 32(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 216(s1)
+; ILP32-NEXT: fsd fa5, 224(s0)
; ILP32-NEXT: fld fa5, 40(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 208(s1)
+; ILP32-NEXT: fsd fa5, 216(s0)
; ILP32-NEXT: fld fa5, 48(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 200(s1)
+; ILP32-NEXT: fsd fa5, 208(s0)
; ILP32-NEXT: fld fa5, 56(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 192(s1)
+; ILP32-NEXT: fsd fa5, 200(s0)
; ILP32-NEXT: fld fa5, 64(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 184(s1)
+; ILP32-NEXT: fsd fa5, 192(s0)
; ILP32-NEXT: fld fa5, 72(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 176(s1)
+; ILP32-NEXT: fsd fa5, 184(s0)
; ILP32-NEXT: fld fa5, 80(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 168(s1)
+; ILP32-NEXT: fsd fa5, 176(s0)
; ILP32-NEXT: fld fa5, 88(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 160(s1)
+; ILP32-NEXT: fsd fa5, 168(s0)
; ILP32-NEXT: fld fa5, 96(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 152(s1)
+; ILP32-NEXT: fsd fa5, 160(s0)
; ILP32-NEXT: fld fa5, 104(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 144(s1)
+; ILP32-NEXT: fsd fa5, 152(s0)
; ILP32-NEXT: fld fa5, 112(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 136(s1)
+; ILP32-NEXT: fsd fa5, 144(s0)
; ILP32-NEXT: fld fa5, 120(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 128(s1)
+; ILP32-NEXT: fsd fa5, 136(s0)
; ILP32-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 120(s1)
+; ILP32-NEXT: fsd fa5, 128(s0)
; ILP32-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 112(s1)
+; ILP32-NEXT: fsd fa5, 120(s0)
; ILP32-NEXT: fld fa5, 144(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 104(s1)
+; ILP32-NEXT: fsd fa5, 112(s0)
; ILP32-NEXT: fld fa5, 152(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 96(s1)
+; ILP32-NEXT: fsd fa5, 104(s0)
; ILP32-NEXT: fld fa5, 160(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 88(s1)
+; ILP32-NEXT: fsd fa5, 96(s0)
; ILP32-NEXT: fld fa5, 168(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 80(s1)
+; ILP32-NEXT: fsd fa5, 88(s0)
; ILP32-NEXT: fld fa5, 176(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 72(s1)
+; ILP32-NEXT: fsd fa5, 80(s0)
; ILP32-NEXT: fld fa5, 184(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 64(s1)
+; ILP32-NEXT: fsd fa5, 72(s0)
; ILP32-NEXT: fld fa5, 192(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 56(s1)
+; ILP32-NEXT: fsd fa5, 64(s0)
; ILP32-NEXT: fld fa5, 200(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 48(s1)
+; ILP32-NEXT: fsd fa5, 56(s0)
; ILP32-NEXT: fld fa5, 208(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 40(s1)
+; ILP32-NEXT: fsd fa5, 48(s0)
; ILP32-NEXT: fld fa5, 216(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 32(s1)
+; ILP32-NEXT: fsd fa5, 40(s0)
; ILP32-NEXT: fld fa5, 224(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 24(s1)
+; ILP32-NEXT: fsd fa5, 32(s0)
; ILP32-NEXT: fld fa5, 232(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, 16(s1)
+; ILP32-NEXT: fsd fa5, 24(s0)
; ILP32-NEXT: fld fa5, 240(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, %lo(var+8)(s0)
+; ILP32-NEXT: fsd fa5, 16(s0)
; ILP32-NEXT: fld fa5, 248(sp) # 8-byte Folded Reload
-; ILP32-NEXT: fsd fa5, %lo(var)(s0)
+; ILP32-NEXT: fsd fa5, 8(s0)
+; ILP32-NEXT: fld fa5, 256(sp) # 8-byte Folded Reload
+; ILP32-NEXT: fsd fa5, 0(s0)
; ILP32-NEXT: lw ra, 268(sp) # 4-byte Folded Reload
; ILP32-NEXT: lw s0, 264(sp) # 4-byte Folded Reload
-; ILP32-NEXT: lw s1, 260(sp) # 4-byte Folded Reload
; ILP32-NEXT: addi sp, sp, 272
; ILP32-NEXT: ret
;
; LP64-LABEL: caller:
; LP64: # %bb.0:
-; LP64-NEXT: addi sp, sp, -288
-; LP64-NEXT: sd ra, 280(sp) # 8-byte Folded Spill
-; LP64-NEXT: sd s0, 272(sp) # 8-byte Folded Spill
-; LP64-NEXT: sd s1, 264(sp) # 8-byte Folded Spill
+; LP64-NEXT: addi sp, sp, -272
+; LP64-NEXT: sd ra, 264(sp) # 8-byte Folded Spill
+; LP64-NEXT: sd s0, 256(sp) # 8-byte Folded Spill
; LP64-NEXT: lui s0, %hi(var)
-; LP64-NEXT: fld fa5, %lo(var)(s0)
-; LP64-NEXT: fsd fa5, 256(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, %lo(var+8)(s0)
+; LP64-NEXT: addi s0, s0, %lo(var)
+; LP64-NEXT: fld fa5, 0(s0)
; LP64-NEXT: fsd fa5, 248(sp) # 8-byte Folded Spill
-; LP64-NEXT: addi s1, s0, %lo(var)
-; LP64-NEXT: fld fa5, 16(s1)
+; LP64-NEXT: fld fa5, 8(s0)
; LP64-NEXT: fsd fa5, 240(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 24(s1)
+; LP64-NEXT: fld fa5, 16(s0)
; LP64-NEXT: fsd fa5, 232(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 32(s1)
+; LP64-NEXT: fld fa5, 24(s0)
; LP64-NEXT: fsd fa5, 224(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 40(s1)
+; LP64-NEXT: fld fa5, 32(s0)
; LP64-NEXT: fsd fa5, 216(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 48(s1)
+; LP64-NEXT: fld fa5, 40(s0)
; LP64-NEXT: fsd fa5, 208(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 56(s1)
+; LP64-NEXT: fld fa5, 48(s0)
; LP64-NEXT: fsd fa5, 200(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 64(s1)
+; LP64-NEXT: fld fa5, 56(s0)
; LP64-NEXT: fsd fa5, 192(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 72(s1)
+; LP64-NEXT: fld fa5, 64(s0)
; LP64-NEXT: fsd fa5, 184(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 80(s1)
+; LP64-NEXT: fld fa5, 72(s0)
; LP64-NEXT: fsd fa5, 176(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 88(s1)
+; LP64-NEXT: fld fa5, 80(s0)
; LP64-NEXT: fsd fa5, 168(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 96(s1)
+; LP64-NEXT: fld fa5, 88(s0)
; LP64-NEXT: fsd fa5, 160(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 104(s1)
+; LP64-NEXT: fld fa5, 96(s0)
; LP64-NEXT: fsd fa5, 152(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 112(s1)
+; LP64-NEXT: fld fa5, 104(s0)
; LP64-NEXT: fsd fa5, 144(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 120(s1)
+; LP64-NEXT: fld fa5, 112(s0)
; LP64-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 128(s1)
+; LP64-NEXT: fld fa5, 120(s0)
; LP64-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 136(s1)
+; LP64-NEXT: fld fa5, 128(s0)
; LP64-NEXT: fsd fa5, 120(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 144(s1)
+; LP64-NEXT: fld fa5, 136(s0)
; LP64-NEXT: fsd fa5, 112(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 152(s1)
+; LP64-NEXT: fld fa5, 144(s0)
; LP64-NEXT: fsd fa5, 104(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 160(s1)
+; LP64-NEXT: fld fa5, 152(s0)
; LP64-NEXT: fsd fa5, 96(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 168(s1)
+; LP64-NEXT: fld fa5, 160(s0)
; LP64-NEXT: fsd fa5, 88(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 176(s1)
+; LP64-NEXT: fld fa5, 168(s0)
; LP64-NEXT: fsd fa5, 80(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 184(s1)
+; LP64-NEXT: fld fa5, 176(s0)
; LP64-NEXT: fsd fa5, 72(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 192(s1)
+; LP64-NEXT: fld fa5, 184(s0)
; LP64-NEXT: fsd fa5, 64(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 200(s1)
+; LP64-NEXT: fld fa5, 192(s0)
; LP64-NEXT: fsd fa5, 56(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 208(s1)
+; LP64-NEXT: fld fa5, 200(s0)
; LP64-NEXT: fsd fa5, 48(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 216(s1)
+; LP64-NEXT: fld fa5, 208(s0)
; LP64-NEXT: fsd fa5, 40(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 224(s1)
+; LP64-NEXT: fld fa5, 216(s0)
; LP64-NEXT: fsd fa5, 32(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 232(s1)
+; LP64-NEXT: fld fa5, 224(s0)
; LP64-NEXT: fsd fa5, 24(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 240(s1)
+; LP64-NEXT: fld fa5, 232(s0)
; LP64-NEXT: fsd fa5, 16(sp) # 8-byte Folded Spill
-; LP64-NEXT: fld fa5, 248(s1)
+; LP64-NEXT: fld fa5, 240(s0)
; LP64-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill
+; LP64-NEXT: fld fa5, 248(s0)
+; LP64-NEXT: fsd fa5, 0(sp) # 8-byte Folded Spill
; LP64-NEXT: call callee
+; LP64-NEXT: fld fa5, 0(sp) # 8-byte Folded Reload
+; LP64-NEXT: fsd fa5, 248(s0)
; LP64-NEXT: fld fa5, 8(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 248(s1)
+; LP64-NEXT: fsd fa5, 240(s0)
; LP64-NEXT: fld fa5, 16(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 240(s1)
+; LP64-NEXT: fsd fa5, 232(s0)
; LP64-NEXT: fld fa5, 24(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 232(s1)
+; LP64-NEXT: fsd fa5, 224(s0)
; LP64-NEXT: fld fa5, 32(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 224(s1)
+; LP64-NEXT: fsd fa5, 216(s0)
; LP64-NEXT: fld fa5, 40(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 216(s1)
+; LP64-NEXT: fsd fa5, 208(s0)
; LP64-NEXT: fld fa5, 48(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 208(s1)
+; LP64-NEXT: fsd fa5, 200(s0)
; LP64-NEXT: fld fa5, 56(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 200(s1)
+; LP64-NEXT: fsd fa5, 192(s0)
; LP64-NEXT: fld fa5, 64(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 192(s1)
+; LP64-NEXT: fsd fa5, 184(s0)
; LP64-NEXT: fld fa5, 72(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 184(s1)
+; LP64-NEXT: fsd fa5, 176(s0)
; LP64-NEXT: fld fa5, 80(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 176(s1)
+; LP64-NEXT: fsd fa5, 168(s0)
; LP64-NEXT: fld fa5, 88(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 168(s1)
+; LP64-NEXT: fsd fa5, 160(s0)
; LP64-NEXT: fld fa5, 96(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 160(s1)
+; LP64-NEXT: fsd fa5, 152(s0)
; LP64-NEXT: fld fa5, 104(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 152(s1)
+; LP64-NEXT: fsd fa5, 144(s0)
; LP64-NEXT: fld fa5, 112(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 144(s1)
+; LP64-NEXT: fsd fa5, 136(s0)
; LP64-NEXT: fld fa5, 120(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 136(s1)
+; LP64-NEXT: fsd fa5, 128(s0)
; LP64-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 128(s1)
+; LP64-NEXT: fsd fa5, 120(s0)
; LP64-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 120(s1)
+; LP64-NEXT: fsd fa5, 112(s0)
; LP64-NEXT: fld fa5, 144(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 112(s1)
+; LP64-NEXT: fsd fa5, 104(s0)
; LP64-NEXT: fld fa5, 152(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 104(s1)
+; LP64-NEXT: fsd fa5, 96(s0)
; LP64-NEXT: fld fa5, 160(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 96(s1)
+; LP64-NEXT: fsd fa5, 88(s0)
; LP64-NEXT: fld fa5, 168(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 88(s1)
+; LP64-NEXT: fsd fa5, 80(s0)
; LP64-NEXT: fld fa5, 176(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 80(s1)
+; LP64-NEXT: fsd fa5, 72(s0)
; LP64-NEXT: fld fa5, 184(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 72(s1)
+; LP64-NEXT: fsd fa5, 64(s0)
; LP64-NEXT: fld fa5, 192(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 64(s1)
+; LP64-NEXT: fsd fa5, 56(s0)
; LP64-NEXT: fld fa5, 200(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 56(s1)
+; LP64-NEXT: fsd fa5, 48(s0)
; LP64-NEXT: fld fa5, 208(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 48(s1)
+; LP64-NEXT: fsd fa5, 40(s0)
; LP64-NEXT: fld fa5, 216(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 40(s1)
+; LP64-NEXT: fsd fa5, 32(s0)
; LP64-NEXT: fld fa5, 224(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 32(s1)
+; LP64-NEXT: fsd fa5, 24(s0)
; LP64-NEXT: fld fa5, 232(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 24(s1)
+; LP64-NEXT: fsd fa5, 16(s0)
; LP64-NEXT: fld fa5, 240(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, 16(s1)
+; LP64-NEXT: fsd fa5, 8(s0)
; LP64-NEXT: fld fa5, 248(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, %lo(var+8)(s0)
-; LP64-NEXT: fld fa5, 256(sp) # 8-byte Folded Reload
-; LP64-NEXT: fsd fa5, %lo(var)(s0)
-; LP64-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
-; LP64-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
-; LP64-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
-; LP64-NEXT: addi sp, sp, 288
+; LP64-NEXT: fsd fa5, 0(s0)
+; LP64-NEXT: ld ra, 264(sp) # 8-byte Folded Reload
+; LP64-NEXT: ld s0, 256(sp) # 8-byte Folded Reload
+; LP64-NEXT: addi sp, sp, 272
; LP64-NEXT: ret
;
; LP64E-LABEL: caller:
; LP64E: # %bb.0:
-; LP64E-NEXT: addi sp, sp, -280
-; LP64E-NEXT: sd ra, 272(sp) # 8-byte Folded Spill
-; LP64E-NEXT: sd s0, 264(sp) # 8-byte Folded Spill
-; LP64E-NEXT: sd s1, 256(sp) # 8-byte Folded Spill
+; LP64E-NEXT: addi sp, sp, -272
+; LP64E-NEXT: sd ra, 264(sp) # 8-byte Folded Spill
+; LP64E-NEXT: sd s0, 256(sp) # 8-byte Folded Spill
; LP64E-NEXT: lui s0, %hi(var)
-; LP64E-NEXT: fld fa5, %lo(var)(s0)
+; LP64E-NEXT: addi s0, s0, %lo(var)
+; LP64E-NEXT: fld fa5, 0(s0)
; LP64E-NEXT: fsd fa5, 248(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, %lo(var+8)(s0)
+; LP64E-NEXT: fld fa5, 8(s0)
; LP64E-NEXT: fsd fa5, 240(sp) # 8-byte Folded Spill
-; LP64E-NEXT: addi s1, s0, %lo(var)
-; LP64E-NEXT: fld fa5, 16(s1)
+; LP64E-NEXT: fld fa5, 16(s0)
; LP64E-NEXT: fsd fa5, 232(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 24(s1)
+; LP64E-NEXT: fld fa5, 24(s0)
; LP64E-NEXT: fsd fa5, 224(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 32(s1)
+; LP64E-NEXT: fld fa5, 32(s0)
; LP64E-NEXT: fsd fa5, 216(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 40(s1)
+; LP64E-NEXT: fld fa5, 40(s0)
; LP64E-NEXT: fsd fa5, 208(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 48(s1)
+; LP64E-NEXT: fld fa5, 48(s0)
; LP64E-NEXT: fsd fa5, 200(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 56(s1)
+; LP64E-NEXT: fld fa5, 56(s0)
; LP64E-NEXT: fsd fa5, 192(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 64(s1)
+; LP64E-NEXT: fld fa5, 64(s0)
; LP64E-NEXT: fsd fa5, 184(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 72(s1)
+; LP64E-NEXT: fld fa5, 72(s0)
; LP64E-NEXT: fsd fa5, 176(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 80(s1)
+; LP64E-NEXT: fld fa5, 80(s0)
; LP64E-NEXT: fsd fa5, 168(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 88(s1)
+; LP64E-NEXT: fld fa5, 88(s0)
; LP64E-NEXT: fsd fa5, 160(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 96(s1)
+; LP64E-NEXT: fld fa5, 96(s0)
; LP64E-NEXT: fsd fa5, 152(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 104(s1)
+; LP64E-NEXT: fld fa5, 104(s0)
; LP64E-NEXT: fsd fa5, 144(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 112(s1)
+; LP64E-NEXT: fld fa5, 112(s0)
; LP64E-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 120(s1)
+; LP64E-NEXT: fld fa5, 120(s0)
; LP64E-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 128(s1)
+; LP64E-NEXT: fld fa5, 128(s0)
; LP64E-NEXT: fsd fa5, 120(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 136(s1)
+; LP64E-NEXT: fld fa5, 136(s0)
; LP64E-NEXT: fsd fa5, 112(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 144(s1)
+; LP64E-NEXT: fld fa5, 144(s0)
; LP64E-NEXT: fsd fa5, 104(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 152(s1)
+; LP64E-NEXT: fld fa5, 152(s0)
; LP64E-NEXT: fsd fa5, 96(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 160(s1)
+; LP64E-NEXT: fld fa5, 160(s0)
; LP64E-NEXT: fsd fa5, 88(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 168(s1)
+; LP64E-NEXT: fld fa5, 168(s0)
; LP64E-NEXT: fsd fa5, 80(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 176(s1)
+; LP64E-NEXT: fld fa5, 176(s0)
; LP64E-NEXT: fsd fa5, 72(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 184(s1)
+; LP64E-NEXT: fld fa5, 184(s0)
; LP64E-NEXT: fsd fa5, 64(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 192(s1)
+; LP64E-NEXT: fld fa5, 192(s0)
; LP64E-NEXT: fsd fa5, 56(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 200(s1)
+; LP64E-NEXT: fld fa5, 200(s0)
; LP64E-NEXT: fsd fa5, 48(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 208(s1)
+; LP64E-NEXT: fld fa5, 208(s0)
; LP64E-NEXT: fsd fa5, 40(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 216(s1)
+; LP64E-NEXT: fld fa5, 216(s0)
; LP64E-NEXT: fsd fa5, 32(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 224(s1)
+; LP64E-NEXT: fld fa5, 224(s0)
; LP64E-NEXT: fsd fa5, 24(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 232(s1)
+; LP64E-NEXT: fld fa5, 232(s0)
; LP64E-NEXT: fsd fa5, 16(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 240(s1)
+; LP64E-NEXT: fld fa5, 240(s0)
; LP64E-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill
-; LP64E-NEXT: fld fa5, 248(s1)
+; LP64E-NEXT: fld fa5, 248(s0)
; LP64E-NEXT: fsd fa5, 0(sp) # 8-byte Folded Spill
; LP64E-NEXT: call callee
; LP64E-NEXT: fld fa5, 0(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 248(s1)
+; LP64E-NEXT: fsd fa5, 248(s0)
; LP64E-NEXT: fld fa5, 8(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 240(s1)
+; LP64E-NEXT: fsd fa5, 240(s0)
; LP64E-NEXT: fld fa5, 16(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 232(s1)
+; LP64E-NEXT: fsd fa5, 232(s0)
; LP64E-NEXT: fld fa5, 24(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 224(s1)
+; LP64E-NEXT: fsd fa5, 224(s0)
; LP64E-NEXT: fld fa5, 32(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 216(s1)
+; LP64E-NEXT: fsd fa5, 216(s0)
; LP64E-NEXT: fld fa5, 40(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 208(s1)
+; LP64E-NEXT: fsd fa5, 208(s0)
; LP64E-NEXT: fld fa5, 48(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 200(s1)
+; LP64E-NEXT: fsd fa5, 200(s0)
; LP64E-NEXT: fld fa5, 56(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 192(s1)
+; LP64E-NEXT: fsd fa5, 192(s0)
; LP64E-NEXT: fld fa5, 64(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 184(s1)
+; LP64E-NEXT: fsd fa5, 184(s0)
; LP64E-NEXT: fld fa5, 72(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 176(s1)
+; LP64E-NEXT: fsd fa5, 176(s0)
; LP64E-NEXT: fld fa5, 80(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 168(s1)
+; LP64E-NEXT: fsd fa5, 168(s0)
; LP64E-NEXT: fld fa5, 88(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 160(s1)
+; LP64E-NEXT: fsd fa5, 160(s0)
; LP64E-NEXT: fld fa5, 96(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 152(s1)
+; LP64E-NEXT: fsd fa5, 152(s0)
; LP64E-NEXT: fld fa5, 104(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 144(s1)
+; LP64E-NEXT: fsd fa5, 144(s0)
; LP64E-NEXT: fld fa5, 112(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 136(s1)
+; LP64E-NEXT: fsd fa5, 136(s0)
; LP64E-NEXT: fld fa5, 120(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 128(s1)
+; LP64E-NEXT: fsd fa5, 128(s0)
; LP64E-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 120(s1)
+; LP64E-NEXT: fsd fa5, 120(s0)
; LP64E-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 112(s1)
+; LP64E-NEXT: fsd fa5, 112(s0)
; LP64E-NEXT: fld fa5, 144(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 104(s1)
+; LP64E-NEXT: fsd fa5, 104(s0)
; LP64E-NEXT: fld fa5, 152(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 96(s1)
+; LP64E-NEXT: fsd fa5, 96(s0)
; LP64E-NEXT: fld fa5, 160(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 88(s1)
+; LP64E-NEXT: fsd fa5, 88(s0)
; LP64E-NEXT: fld fa5, 168(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 80(s1)
+; LP64E-NEXT: fsd fa5, 80(s0)
; LP64E-NEXT: fld fa5, 176(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 72(s1)
+; LP64E-NEXT: fsd fa5, 72(s0)
; LP64E-NEXT: fld fa5, 184(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 64(s1)
+; LP64E-NEXT: fsd fa5, 64(s0)
; LP64E-NEXT: fld fa5, 192(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 56(s1)
+; LP64E-NEXT: fsd fa5, 56(s0)
; LP64E-NEXT: fld fa5, 200(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 48(s1)
+; LP64E-NEXT: fsd fa5, 48(s0)
; LP64E-NEXT: fld fa5, 208(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 40(s1)
+; LP64E-NEXT: fsd fa5, 40(s0)
; LP64E-NEXT: fld fa5, 216(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 32(s1)
+; LP64E-NEXT: fsd fa5, 32(s0)
; LP64E-NEXT: fld fa5, 224(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 24(s1)
+; LP64E-NEXT: fsd fa5, 24(s0)
; LP64E-NEXT: fld fa5, 232(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, 16(s1)
+; LP64E-NEXT: fsd fa5, 16(s0)
; LP64E-NEXT: fld fa5, 240(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, %lo(var+8)(s0)
+; LP64E-NEXT: fsd fa5, 8(s0)
; LP64E-NEXT: fld fa5, 248(sp) # 8-byte Folded Reload
-; LP64E-NEXT: fsd fa5, %lo(var)(s0)
-; LP64E-NEXT: ld ra, 272(sp) # 8-byte Folded Reload
-; LP64E-NEXT: ld s0, 264(sp) # 8-byte Folded Reload
-; LP64E-NEXT: ld s1, 256(sp) # 8-byte Folded Reload
-; LP64E-NEXT: addi sp, sp, 280
+; LP64E-NEXT: fsd fa5, 0(s0)
+; LP64E-NEXT: ld ra, 264(sp) # 8-byte Folded Reload
+; LP64E-NEXT: ld s0, 256(sp) # 8-byte Folded Reload
+; LP64E-NEXT: addi sp, sp, 272
; LP64E-NEXT: ret
;
; ILP32D-LABEL: caller:
@@ -867,285 +861,281 @@ define void @caller() nounwind {
; ILP32D-NEXT: addi sp, sp, -272
; ILP32D-NEXT: sw ra, 268(sp) # 4-byte Folded Spill
; ILP32D-NEXT: sw s0, 264(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: sw s1, 260(sp) # 4-byte Folded Spill
-; ILP32D-NEXT: fsd fs0, 248(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs1, 240(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs2, 232(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs3, 224(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs4, 216(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs5, 208(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs6, 200(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs7, 192(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs8, 184(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs9, 176(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs10, 168(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fsd fs11, 160(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs0, 256(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs1, 248(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs2, 240(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs3, 232(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs4, 224(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs5, 216(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs6, 208(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs7, 200(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs8, 192(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs9, 184(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs10, 176(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fsd fs11, 168(sp) # 8-byte Folded Spill
; ILP32D-NEXT: lui s0, %hi(var)
-; ILP32D-NEXT: fld fa5, %lo(var)(s0)
+; ILP32D-NEXT: addi s0, s0, %lo(var)
+; ILP32D-NEXT: fld fa5, 0(s0)
+; ILP32D-NEXT: fsd fa5, 160(sp) # 8-byte Folded Spill
+; ILP32D-NEXT: fld fa5, 8(s0)
; ILP32D-NEXT: fsd fa5, 152(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, %lo(var+8)(s0)
+; ILP32D-NEXT: fld fa5, 16(s0)
; ILP32D-NEXT: fsd fa5, 144(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: addi s1, s0, %lo(var)
-; ILP32D-NEXT: fld fa5, 16(s1)
+; ILP32D-NEXT: fld fa5, 24(s0)
; ILP32D-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 24(s1)
+; ILP32D-NEXT: fld fa5, 32(s0)
; ILP32D-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 32(s1)
+; ILP32D-NEXT: fld fa5, 40(s0)
; ILP32D-NEXT: fsd fa5, 120(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 40(s1)
+; ILP32D-NEXT: fld fa5, 48(s0)
; ILP32D-NEXT: fsd fa5, 112(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 48(s1)
+; ILP32D-NEXT: fld fa5, 56(s0)
; ILP32D-NEXT: fsd fa5, 104(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 56(s1)
+; ILP32D-NEXT: fld fa5, 64(s0)
; ILP32D-NEXT: fsd fa5, 96(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 64(s1)
+; ILP32D-NEXT: fld fa5, 72(s0)
; ILP32D-NEXT: fsd fa5, 88(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 72(s1)
+; ILP32D-NEXT: fld fa5, 80(s0)
; ILP32D-NEXT: fsd fa5, 80(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 80(s1)
+; ILP32D-NEXT: fld fa5, 88(s0)
; ILP32D-NEXT: fsd fa5, 72(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 88(s1)
+; ILP32D-NEXT: fld fa5, 96(s0)
; ILP32D-NEXT: fsd fa5, 64(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 96(s1)
+; ILP32D-NEXT: fld fa5, 104(s0)
; ILP32D-NEXT: fsd fa5, 56(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 104(s1)
+; ILP32D-NEXT: fld fa5, 112(s0)
; ILP32D-NEXT: fsd fa5, 48(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 112(s1)
+; ILP32D-NEXT: fld fa5, 120(s0)
; ILP32D-NEXT: fsd fa5, 40(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 120(s1)
+; ILP32D-NEXT: fld fa5, 128(s0)
; ILP32D-NEXT: fsd fa5, 32(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 128(s1)
+; ILP32D-NEXT: fld fa5, 136(s0)
; ILP32D-NEXT: fsd fa5, 24(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 136(s1)
+; ILP32D-NEXT: fld fa5, 144(s0)
; ILP32D-NEXT: fsd fa5, 16(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 144(s1)
+; ILP32D-NEXT: fld fa5, 152(s0)
; ILP32D-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fa5, 152(s1)
-; ILP32D-NEXT: fsd fa5, 0(sp) # 8-byte Folded Spill
-; ILP32D-NEXT: fld fs8, 160(s1)
-; ILP32D-NEXT: fld fs9, 168(s1)
-; ILP32D-NEXT: fld fs10, 176(s1)
-; ILP32D-NEXT: fld fs11, 184(s1)
-; ILP32D-NEXT: fld fs0, 192(s1)
-; ILP32D-NEXT: fld fs1, 200(s1)
-; ILP32D-NEXT: fld fs2, 208(s1)
-; ILP32D-NEXT: fld fs3, 216(s1)
-; ILP32D-NEXT: fld fs4, 224(s1)
-; ILP32D-NEXT: fld fs5, 232(s1)
-; ILP32D-NEXT: fld fs6, 240(s1)
-; ILP32D-NEXT: fld fs7, 248(s1)
+; ILP32D-NEXT: fld fs8, 160(s0)
+; ILP32D-NEXT: fld fs9, 168(s0)
+; ILP32D-NEXT: fld fs10, 176(s0)
+; ILP32D-NEXT: fld fs11, 184(s0)
+; ILP32D-NEXT: fld fs0, 192(s0)
+; ILP32D-NEXT: fld fs1, 200(s0)
+; ILP32D-NEXT: fld fs2, 208(s0)
+; ILP32D-NEXT: fld fs3, 216(s0)
+; ILP32D-NEXT: fld fs4, 224(s0)
+; ILP32D-NEXT: fld fs5, 232(s0)
+; ILP32D-NEXT: fld fs6, 240(s0)
+; ILP32D-NEXT: fld fs7, 248(s0)
; ILP32D-NEXT: call callee
-; ILP32D-NEXT: fsd fs7, 248(s1)
-; ILP32D-NEXT: fsd fs6, 240(s1)
-; ILP32D-NEXT: fsd fs5, 232(s1)
-; ILP32D-NEXT: fsd fs4, 224(s1)
-; ILP32D-NEXT: fsd fs3, 216(s1)
-; ILP32D-NEXT: fsd fs2, 208(s1)
-; ILP32D-NEXT: fsd fs1, 200(s1)
-; ILP32D-NEXT: fsd fs0, 192(s1)
-; ILP32D-NEXT: fsd fs11, 184(s1)
-; ILP32D-NEXT: fsd fs10, 176(s1)
-; ILP32D-NEXT: fsd fs9, 168(s1)
-; ILP32D-NEXT: fsd fs8, 160(s1)
-; ILP32D-NEXT: fld fa5, 0(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 152(s1)
+; ILP32D-NEXT: fsd fs7, 248(s0)
+; ILP32D-NEXT: fsd fs6, 240(s0)
+; ILP32D-NEXT: fsd fs5, 232(s0)
+; ILP32D-NEXT: fsd fs4, 224(s0)
+; ILP32D-NEXT: fsd fs3, 216(s0)
+; ILP32D-NEXT: fsd fs2, 208(s0)
+; ILP32D-NEXT: fsd fs1, 200(s0)
+; ILP32D-NEXT: fsd fs0, 192(s0)
+; ILP32D-NEXT: fsd fs11, 184(s0)
+; ILP32D-NEXT: fsd fs10, 176(s0)
+; ILP32D-NEXT: fsd fs9, 168(s0)
+; ILP32D-NEXT: fsd fs8, 160(s0)
; ILP32D-NEXT: fld fa5, 8(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 144(s1)
+; ILP32D-NEXT: fsd fa5, 152(s0)
; ILP32D-NEXT: fld fa5, 16(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 136(s1)
+; ILP32D-NEXT: fsd fa5, 144(s0)
; ILP32D-NEXT: fld fa5, 24(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 128(s1)
+; ILP32D-NEXT: fsd fa5, 136(s0)
; ILP32D-NEXT: fld fa5, 32(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 120(s1)
+; ILP32D-NEXT: fsd fa5, 128(s0)
; ILP32D-NEXT: fld fa5, 40(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 112(s1)
+; ILP32D-NEXT: fsd fa5, 120(s0)
; ILP32D-NEXT: fld fa5, 48(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 104(s1)
+; ILP32D-NEXT: fsd fa5, 112(s0)
; ILP32D-NEXT: fld fa5, 56(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 96(s1)
+; ILP32D-NEXT: fsd fa5, 104(s0)
; ILP32D-NEXT: fld fa5, 64(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 88(s1)
+; ILP32D-NEXT: fsd fa5, 96(s0)
; ILP32D-NEXT: fld fa5, 72(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 80(s1)
+; ILP32D-NEXT: fsd fa5, 88(s0)
; ILP32D-NEXT: fld fa5, 80(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 72(s1)
+; ILP32D-NEXT: fsd fa5, 80(s0)
; ILP32D-NEXT: fld fa5, 88(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 64(s1)
+; ILP32D-NEXT: fsd fa5, 72(s0)
; ILP32D-NEXT: fld fa5, 96(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 56(s1)
+; ILP32D-NEXT: fsd fa5, 64(s0)
; ILP32D-NEXT: fld fa5, 104(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 48(s1)
+; ILP32D-NEXT: fsd fa5, 56(s0)
; ILP32D-NEXT: fld fa5, 112(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 40(s1)
+; ILP32D-NEXT: fsd fa5, 48(s0)
; ILP32D-NEXT: fld fa5, 120(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 32(s1)
+; ILP32D-NEXT: fsd fa5, 40(s0)
; ILP32D-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 24(s1)
+; ILP32D-NEXT: fsd fa5, 32(s0)
; ILP32D-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, 16(s1)
+; ILP32D-NEXT: fsd fa5, 24(s0)
; ILP32D-NEXT: fld fa5, 144(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, %lo(var+8)(s0)
+; ILP32D-NEXT: fsd fa5, 16(s0)
; ILP32D-NEXT: fld fa5, 152(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fsd fa5, %lo(var)(s0)
+; ILP32D-NEXT: fsd fa5, 8(s0)
+; ILP32D-NEXT: fld fa5, 160(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fsd fa5, 0(s0)
; ILP32D-NEXT: lw ra, 268(sp) # 4-byte Folded Reload
; ILP32D-NEXT: lw s0, 264(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: lw s1, 260(sp) # 4-byte Folded Reload
-; ILP32D-NEXT: fld fs0, 248(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs1, 240(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs2, 232(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs3, 224(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs4, 216(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs5, 208(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs6, 200(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs7, 192(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs8, 184(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs9, 176(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs10, 168(sp) # 8-byte Folded Reload
-; ILP32D-NEXT: fld fs11, 160(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs0, 256(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs1, 248(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs2, 240(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs3, 232(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs4, 224(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs5, 216(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs6, 208(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs7, 200(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs8, 192(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs9, 184(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs10, 176(sp) # 8-byte Folded Reload
+; ILP32D-NEXT: fld fs11, 168(sp) # 8-byte Folded Reload
; ILP32D-NEXT: addi sp, sp, 272
; ILP32D-NEXT: ret
;
; LP64D-LABEL: caller:
; LP64D: # %bb.0:
-; LP64D-NEXT: addi sp, sp, -288
-; LP64D-NEXT: sd ra, 280(sp) # 8-byte Folded Spill
-; LP64D-NEXT: sd s0, 272(sp) # 8-byte Folded Spill
-; LP64D-NEXT: sd s1, 264(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs0, 256(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs1, 248(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs2, 240(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs3, 232(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs4, 224(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs5, 216(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs6, 208(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs7, 200(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs8, 192(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs9, 184(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs10, 176(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fsd fs11, 168(sp) # 8-byte Folded Spill
+; LP64D-NEXT: addi sp, sp, -272
+; LP64D-NEXT: sd ra, 264(sp) # 8-byte Folded Spill
+; LP64D-NEXT: sd s0, 256(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs0, 248(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs1, 240(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs2, 232(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs3, 224(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs4, 216(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs5, 208(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs6, 200(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs7, 192(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs8, 184(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs9, 176(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs10, 168(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fsd fs11, 160(sp) # 8-byte Folded Spill
; LP64D-NEXT: lui s0, %hi(var)
-; LP64D-NEXT: fld fa5, %lo(var)(s0)
-; LP64D-NEXT: fsd fa5, 160(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, %lo(var+8)(s0)
+; LP64D-NEXT: addi s0, s0, %lo(var)
+; LP64D-NEXT: fld fa5, 0(s0)
; LP64D-NEXT: fsd fa5, 152(sp) # 8-byte Folded Spill
-; LP64D-NEXT: addi s1, s0, %lo(var)
-; LP64D-NEXT: fld fa5, 16(s1)
+; LP64D-NEXT: fld fa5, 8(s0)
; LP64D-NEXT: fsd fa5, 144(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 24(s1)
+; LP64D-NEXT: fld fa5, 16(s0)
; LP64D-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 32(s1)
+; LP64D-NEXT: fld fa5, 24(s0)
; LP64D-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 40(s1)
+; LP64D-NEXT: fld fa5, 32(s0)
; LP64D-NEXT: fsd fa5, 120(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 48(s1)
+; LP64D-NEXT: fld fa5, 40(s0)
; LP64D-NEXT: fsd fa5, 112(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 56(s1)
+; LP64D-NEXT: fld fa5, 48(s0)
; LP64D-NEXT: fsd fa5, 104(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 64(s1)
+; LP64D-NEXT: fld fa5, 56(s0)
; LP64D-NEXT: fsd fa5, 96(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 72(s1)
+; LP64D-NEXT: fld fa5, 64(s0)
; LP64D-NEXT: fsd fa5, 88(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 80(s1)
+; LP64D-NEXT: fld fa5, 72(s0)
; LP64D-NEXT: fsd fa5, 80(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 88(s1)
+; LP64D-NEXT: fld fa5, 80(s0)
; LP64D-NEXT: fsd fa5, 72(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 96(s1)
+; LP64D-NEXT: fld fa5, 88(s0)
; LP64D-NEXT: fsd fa5, 64(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 104(s1)
+; LP64D-NEXT: fld fa5, 96(s0)
; LP64D-NEXT: fsd fa5, 56(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 112(s1)
+; LP64D-NEXT: fld fa5, 104(s0)
; LP64D-NEXT: fsd fa5, 48(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 120(s1)
+; LP64D-NEXT: fld fa5, 112(s0)
; LP64D-NEXT: fsd fa5, 40(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 128(s1)
+; LP64D-NEXT: fld fa5, 120(s0)
; LP64D-NEXT: fsd fa5, 32(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 136(s1)
+; LP64D-NEXT: fld fa5, 128(s0)
; LP64D-NEXT: fsd fa5, 24(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 144(s1)
+; LP64D-NEXT: fld fa5, 136(s0)
; LP64D-NEXT: fsd fa5, 16(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fa5, 152(s1)
+; LP64D-NEXT: fld fa5, 144(s0)
; LP64D-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill
-; LP64D-NEXT: fld fs8, 160(s1)
-; LP64D-NEXT: fld fs9, 168(s1)
-; LP64D-NEXT: fld fs10, 176(s1)
-; LP64D-NEXT: fld fs11, 184(s1)
-; LP64D-NEXT: fld fs0, 192(s1)
-; LP64D-NEXT: fld fs1, 200(s1)
-; LP64D-NEXT: fld fs2, 208(s1)
-; LP64D-NEXT: fld fs3, 216(s1)
-; LP64D-NEXT: fld fs4, 224(s1)
-; LP64D-NEXT: fld fs5, 232(s1)
-; LP64D-NEXT: fld fs6, 240(s1)
-; LP64D-NEXT: fld fs7, 248(s1)
+; LP64D-NEXT: fld fa5, 152(s0)
+; LP64D-NEXT: fsd fa5, 0(sp) # 8-byte Folded Spill
+; LP64D-NEXT: fld fs8, 160(s0)
+; LP64D-NEXT: fld fs9, 168(s0)
+; LP64D-NEXT: fld fs10, 176(s0)
+; LP64D-NEXT: fld fs11, 184(s0)
+; LP64D-NEXT: fld fs0, 192(s0)
+; LP64D-NEXT: fld fs1, 200(s0)
+; LP64D-NEXT: fld fs2, 208(s0)
+; LP64D-NEXT: fld fs3, 216(s0)
+; LP64D-NEXT: fld fs4, 224(s0)
+; LP64D-NEXT: fld fs5, 232(s0)
+; LP64D-NEXT: fld fs6, 240(s0)
+; LP64D-NEXT: fld fs7, 248(s0)
; LP64D-NEXT: call callee
-; LP64D-NEXT: fsd fs7, 248(s1)
-; LP64D-NEXT: fsd fs6, 240(s1)
-; LP64D-NEXT: fsd fs5, 232(s1)
-; LP64D-NEXT: fsd fs4, 224(s1)
-; LP64D-NEXT: fsd fs3, 216(s1)
-; LP64D-NEXT: fsd fs2, 208(s1)
-; LP64D-NEXT: fsd fs1, 200(s1)
-; LP64D-NEXT: fsd fs0, 192(s1)
-; LP64D-NEXT: fsd fs11, 184(s1)
-; LP64D-NEXT: fsd fs10, 176(s1)
-; LP64D-NEXT: fsd fs9, 168(s1)
-; LP64D-NEXT: fsd fs8, 160(s1)
+; LP64D-NEXT: fsd fs7, 248(s0)
+; LP64D-NEXT: fsd fs6, 240(s0)
+; LP64D-NEXT: fsd fs5, 232(s0)
+; LP64D-NEXT: fsd fs4, 224(s0)
+; LP64D-NEXT: fsd fs3, 216(s0)
+; LP64D-NEXT: fsd fs2, 208(s0)
+; LP64D-NEXT: fsd fs1, 200(s0)
+; LP64D-NEXT: fsd fs0, 192(s0)
+; LP64D-NEXT: fsd fs11, 184(s0)
+; LP64D-NEXT: fsd fs10, 176(s0)
+; LP64D-NEXT: fsd fs9, 168(s0)
+; LP64D-NEXT: fsd fs8, 160(s0)
+; LP64D-NEXT: fld fa5, 0(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fsd fa5, 152(s0)
; LP64D-NEXT: fld fa5, 8(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 152(s1)
+; LP64D-NEXT: fsd fa5, 144(s0)
; LP64D-NEXT: fld fa5, 16(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 144(s1)
+; LP64D-NEXT: fsd fa5, 136(s0)
; LP64D-NEXT: fld fa5, 24(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 136(s1)
+; LP64D-NEXT: fsd fa5, 128(s0)
; LP64D-NEXT: fld fa5, 32(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 128(s1)
+; LP64D-NEXT: fsd fa5, 120(s0)
; LP64D-NEXT: fld fa5, 40(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 120(s1)
+; LP64D-NEXT: fsd fa5, 112(s0)
; LP64D-NEXT: fld fa5, 48(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 112(s1)
+; LP64D-NEXT: fsd fa5, 104(s0)
; LP64D-NEXT: fld fa5, 56(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 104(s1)
+; LP64D-NEXT: fsd fa5, 96(s0)
; LP64D-NEXT: fld fa5, 64(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 96(s1)
+; LP64D-NEXT: fsd fa5, 88(s0)
; LP64D-NEXT: fld fa5, 72(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 88(s1)
+; LP64D-NEXT: fsd fa5, 80(s0)
; LP64D-NEXT: fld fa5, 80(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 80(s1)
+; LP64D-NEXT: fsd fa5, 72(s0)
; LP64D-NEXT: fld fa5, 88(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 72(s1)
+; LP64D-NEXT: fsd fa5, 64(s0)
; LP64D-NEXT: fld fa5, 96(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 64(s1)
+; LP64D-NEXT: fsd fa5, 56(s0)
; LP64D-NEXT: fld fa5, 104(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 56(s1)
+; LP64D-NEXT: fsd fa5, 48(s0)
; LP64D-NEXT: fld fa5, 112(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 48(s1)
+; LP64D-NEXT: fsd fa5, 40(s0)
; LP64D-NEXT: fld fa5, 120(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 40(s1)
+; LP64D-NEXT: fsd fa5, 32(s0)
; LP64D-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 32(s1)
+; LP64D-NEXT: fsd fa5, 24(s0)
; LP64D-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 24(s1)
+; LP64D-NEXT: fsd fa5, 16(s0)
; LP64D-NEXT: fld fa5, 144(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, 16(s1)
+; LP64D-NEXT: fsd fa5, 8(s0)
; LP64D-NEXT: fld fa5, 152(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, %lo(var+8)(s0)
-; LP64D-NEXT: fld fa5, 160(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fsd fa5, %lo(var)(s0)
-; LP64D-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
-; LP64D-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
-; LP64D-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs0, 256(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs1, 248(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs2, 240(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs3, 232(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs4, 224(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs5, 216(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs6, 208(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs7, 200(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs8, 192(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs9, 184(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs10, 176(sp) # 8-byte Folded Reload
-; LP64D-NEXT: fld fs11, 168(sp) # 8-byte Folded Reload
-; LP64D-NEXT: addi sp, sp, 288
+; LP64D-NEXT: fsd fa5, 0(s0)
+; LP64D-NEXT: ld ra, 264(sp) # 8-byte Folded Reload
+; LP64D-NEXT: ld s0, 256(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs0, 248(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs1, 240(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs2, 232(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs3, 224(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs4, 216(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs5, 208(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs6, 200(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs7, 192(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs8, 184(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs9, 176(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs10, 168(sp) # 8-byte Folded Reload
+; LP64D-NEXT: fld fs11, 160(sp) # 8-byte Folded Reload
+; LP64D-NEXT: addi sp, sp, 272
; LP64D-NEXT: ret
%val = load [32 x double], ptr @var
call void @callee()
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
index 874cf897470e7..8db4c715c41ce 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
@@ -68,84 +68,82 @@ define void @callee() {
; RV32I-NEXT: .cfi_offset s9, -44
; RV32I-NEXT: .cfi_offset s10, -48
; RV32I-NEXT: .cfi_offset s11, -52
-; RV32I-NEXT: lui a7, %hi(var)
-; RV32I-NEXT: lw a0, %lo(var)(a7)
-; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var+4)(a7)
-; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var+8)(a7)
-; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var+12)(a7)
-; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi a5, a7, %lo(var)
-; RV32I-NEXT: lw a0, 16(a5)
-; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 20(a5)
-; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t0, 24(a5)
-; RV32I-NEXT: lw t1, 28(a5)
-; RV32I-NEXT: lw t2, 32(a5)
-; RV32I-NEXT: lw t3, 36(a5)
-; RV32I-NEXT: lw t4, 40(a5)
-; RV32I-NEXT: lw t5, 44(a5)
-; RV32I-NEXT: lw t6, 48(a5)
-; RV32I-NEXT: lw s0, 52(a5)
-; RV32I-NEXT: lw s1, 56(a5)
-; RV32I-NEXT: lw s2, 60(a5)
-; RV32I-NEXT: lw s3, 64(a5)
-; RV32I-NEXT: lw s4, 68(a5)
-; RV32I-NEXT: lw s5, 72(a5)
-; RV32I-NEXT: lw s6, 76(a5)
-; RV32I-NEXT: lw s7, 80(a5)
-; RV32I-NEXT: lw s8, 84(a5)
-; RV32I-NEXT: lw s9, 88(a5)
-; RV32I-NEXT: lw s10, 92(a5)
-; RV32I-NEXT: lw s11, 112(a5)
-; RV32I-NEXT: lw ra, 116(a5)
-; RV32I-NEXT: lw a3, 120(a5)
-; RV32I-NEXT: lw a0, 124(a5)
-; RV32I-NEXT: lw a6, 96(a5)
-; RV32I-NEXT: lw a4, 100(a5)
-; RV32I-NEXT: lw a2, 104(a5)
-; RV32I-NEXT: lw a1, 108(a5)
-; RV32I-NEXT: sw a0, 124(a5)
-; RV32I-NEXT: sw a3, 120(a5)
-; RV32I-NEXT: sw ra, 116(a5)
-; RV32I-NEXT: sw s11, 112(a5)
-; RV32I-NEXT: sw a1, 108(a5)
-; RV32I-NEXT: sw a2, 104(a5)
-; RV32I-NEXT: sw a4, 100(a5)
-; RV32I-NEXT: sw a6, 96(a5)
-; RV32I-NEXT: sw s10, 92(a5)
-; RV32I-NEXT: sw s9, 88(a5)
-; RV32I-NEXT: sw s8, 84(a5)
-; RV32I-NEXT: sw s7, 80(a5)
-; RV32I-NEXT: sw s6, 76(a5)
-; RV32I-NEXT: sw s5, 72(a5)
-; RV32I-NEXT: sw s4, 68(a5)
-; RV32I-NEXT: sw s3, 64(a5)
-; RV32I-NEXT: sw s2, 60(a5)
-; RV32I-NEXT: sw s1, 56(a5)
-; RV32I-NEXT: sw s0, 52(a5)
-; RV32I-NEXT: sw t6, 48(a5)
-; RV32I-NEXT: sw t5, 44(a5)
-; RV32I-NEXT: sw t4, 40(a5)
-; RV32I-NEXT: sw t3, 36(a5)
-; RV32I-NEXT: sw t2, 32(a5)
-; RV32I-NEXT: sw t1, 28(a5)
-; RV32I-NEXT: sw t0, 24(a5)
-; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 20(a5)
-; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 16(a5)
-; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var+12)(a7)
-; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var+8)(a7)
-; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var+4)(a7)
-; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var)(a7)
+; RV32I-NEXT: lui a0, %hi(var)
+; RV32I-NEXT: addi a0, a0, %lo(var)
+; RV32I-NEXT: lw a1, 0(a0)
+; RV32I-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 4(a0)
+; RV32I-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 8(a0)
+; RV32I-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 12(a0)
+; RV32I-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 16(a0)
+; RV32I-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a6, 20(a0)
+; RV32I-NEXT: lw a7, 24(a0)
+; RV32I-NEXT: lw t0, 28(a0)
+; RV32I-NEXT: lw t1, 32(a0)
+; RV32I-NEXT: lw t2, 36(a0)
+; RV32I-NEXT: lw t3, 40(a0)
+; RV32I-NEXT: lw t4, 44(a0)
+; RV32I-NEXT: lw t5, 48(a0)
+; RV32I-NEXT: lw t6, 52(a0)
+; RV32I-NEXT: lw s0, 56(a0)
+; RV32I-NEXT: lw s1, 60(a0)
+; RV32I-NEXT: lw s2, 64(a0)
+; RV32I-NEXT: lw s3, 68(a0)
+; RV32I-NEXT: lw s4, 72(a0)
+; RV32I-NEXT: lw s5, 76(a0)
+; RV32I-NEXT: lw s6, 80(a0)
+; RV32I-NEXT: lw s7, 84(a0)
+; RV32I-NEXT: lw s8, 88(a0)
+; RV32I-NEXT: lw s9, 92(a0)
+; RV32I-NEXT: lw s10, 112(a0)
+; RV32I-NEXT: lw s11, 116(a0)
+; RV32I-NEXT: lw ra, 120(a0)
+; RV32I-NEXT: lw a1, 124(a0)
+; RV32I-NEXT: lw a5, 96(a0)
+; RV32I-NEXT: lw a4, 100(a0)
+; RV32I-NEXT: lw a3, 104(a0)
+; RV32I-NEXT: lw a2, 108(a0)
+; RV32I-NEXT: sw a1, 124(a0)
+; RV32I-NEXT: sw ra, 120(a0)
+; RV32I-NEXT: sw s11, 116(a0)
+; RV32I-NEXT: sw s10, 112(a0)
+; RV32I-NEXT: sw a2, 108(a0)
+; RV32I-NEXT: sw a3, 104(a0)
+; RV32I-NEXT: sw a4, 100(a0)
+; RV32I-NEXT: sw a5, 96(a0)
+; RV32I-NEXT: sw s9, 92(a0)
+; RV32I-NEXT: sw s8, 88(a0)
+; RV32I-NEXT: sw s7, 84(a0)
+; RV32I-NEXT: sw s6, 80(a0)
+; RV32I-NEXT: sw s5, 76(a0)
+; RV32I-NEXT: sw s4, 72(a0)
+; RV32I-NEXT: sw s3, 68(a0)
+; RV32I-NEXT: sw s2, 64(a0)
+; RV32I-NEXT: sw s1, 60(a0)
+; RV32I-NEXT: sw s0, 56(a0)
+; RV32I-NEXT: sw t6, 52(a0)
+; RV32I-NEXT: sw t5, 48(a0)
+; RV32I-NEXT: sw t4, 44(a0)
+; RV32I-NEXT: sw t3, 40(a0)
+; RV32I-NEXT: sw t2, 36(a0)
+; RV32I-NEXT: sw t1, 32(a0)
+; RV32I-NEXT: sw t0, 28(a0)
+; RV32I-NEXT: sw a7, 24(a0)
+; RV32I-NEXT: sw a6, 20(a0)
+; RV32I-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 16(a0)
+; RV32I-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 12(a0)
+; RV32I-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 8(a0)
+; RV32I-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 68(sp) # 4-byte Folded Reload
@@ -178,99 +176,97 @@ define void @callee() {
;
; RV32I-ILP32E-LABEL: callee:
; RV32I-ILP32E: # %bb.0:
-; RV32I-ILP32E-NEXT: addi sp, sp, -36
-; RV32I-ILP32E-NEXT: .cfi_def_cfa_offset 36
-; RV32I-ILP32E-NEXT: sw ra, 32(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: sw s1, 24(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: addi sp, sp, -32
+; RV32I-ILP32E-NEXT: .cfi_def_cfa_offset 32
+; RV32I-ILP32E-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-ILP32E-NEXT: .cfi_offset ra, -4
; RV32I-ILP32E-NEXT: .cfi_offset s0, -8
; RV32I-ILP32E-NEXT: .cfi_offset s1, -12
-; RV32I-ILP32E-NEXT: lui a7, %hi(var)
-; RV32I-ILP32E-NEXT: lw a0, %lo(var)(a7)
-; RV32I-ILP32E-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, %lo(var+4)(a7)
-; RV32I-ILP32E-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, %lo(var+8)(a7)
-; RV32I-ILP32E-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, %lo(var+12)(a7)
-; RV32I-ILP32E-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: addi a5, a7, %lo(var)
-; RV32I-ILP32E-NEXT: lw a0, 16(a5)
-; RV32I-ILP32E-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 20(a5)
-; RV32I-ILP32E-NEXT: sw a0, 0(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw t0, 24(a5)
-; RV32I-ILP32E-NEXT: lw t1, 28(a5)
-; RV32I-ILP32E-NEXT: lw t2, 32(a5)
-; RV32I-ILP32E-NEXT: lw t3, 36(a5)
-; RV32I-ILP32E-NEXT: lw t4, 40(a5)
-; RV32I-ILP32E-NEXT: lw t5, 44(a5)
-; RV32I-ILP32E-NEXT: lw t6, 48(a5)
-; RV32I-ILP32E-NEXT: lw s2, 52(a5)
-; RV32I-ILP32E-NEXT: lw s3, 56(a5)
-; RV32I-ILP32E-NEXT: lw s4, 60(a5)
-; RV32I-ILP32E-NEXT: lw s5, 64(a5)
-; RV32I-ILP32E-NEXT: lw s6, 68(a5)
-; RV32I-ILP32E-NEXT: lw s7, 72(a5)
-; RV32I-ILP32E-NEXT: lw s8, 76(a5)
-; RV32I-ILP32E-NEXT: lw s9, 80(a5)
-; RV32I-ILP32E-NEXT: lw s10, 84(a5)
-; RV32I-ILP32E-NEXT: lw s11, 88(a5)
-; RV32I-ILP32E-NEXT: lw s0, 92(a5)
-; RV32I-ILP32E-NEXT: lw s1, 112(a5)
-; RV32I-ILP32E-NEXT: lw ra, 116(a5)
-; RV32I-ILP32E-NEXT: lw a3, 120(a5)
-; RV32I-ILP32E-NEXT: lw a0, 124(a5)
-; RV32I-ILP32E-NEXT: lw a6, 96(a5)
-; RV32I-ILP32E-NEXT: lw a4, 100(a5)
-; RV32I-ILP32E-NEXT: lw a2, 104(a5)
-; RV32I-ILP32E-NEXT: lw a1, 108(a5)
-; RV32I-ILP32E-NEXT: sw a0, 124(a5)
-; RV32I-ILP32E-NEXT: sw a3, 120(a5)
-; RV32I-ILP32E-NEXT: sw ra, 116(a5)
-; RV32I-ILP32E-NEXT: sw s1, 112(a5)
-; RV32I-ILP32E-NEXT: sw a1, 108(a5)
-; RV32I-ILP32E-NEXT: sw a2, 104(a5)
-; RV32I-ILP32E-NEXT: sw a4, 100(a5)
-; RV32I-ILP32E-NEXT: sw a6, 96(a5)
-; RV32I-ILP32E-NEXT: sw s0, 92(a5)
-; RV32I-ILP32E-NEXT: sw s11, 88(a5)
-; RV32I-ILP32E-NEXT: sw s10, 84(a5)
-; RV32I-ILP32E-NEXT: sw s9, 80(a5)
-; RV32I-ILP32E-NEXT: sw s8, 76(a5)
-; RV32I-ILP32E-NEXT: sw s7, 72(a5)
-; RV32I-ILP32E-NEXT: sw s6, 68(a5)
-; RV32I-ILP32E-NEXT: sw s5, 64(a5)
-; RV32I-ILP32E-NEXT: sw s4, 60(a5)
-; RV32I-ILP32E-NEXT: sw s3, 56(a5)
-; RV32I-ILP32E-NEXT: sw s2, 52(a5)
-; RV32I-ILP32E-NEXT: sw t6, 48(a5)
-; RV32I-ILP32E-NEXT: sw t5, 44(a5)
-; RV32I-ILP32E-NEXT: sw t4, 40(a5)
-; RV32I-ILP32E-NEXT: sw t3, 36(a5)
-; RV32I-ILP32E-NEXT: sw t2, 32(a5)
-; RV32I-ILP32E-NEXT: sw t1, 28(a5)
-; RV32I-ILP32E-NEXT: sw t0, 24(a5)
-; RV32I-ILP32E-NEXT: lw a0, 0(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 20(a5)
-; RV32I-ILP32E-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 16(a5)
-; RV32I-ILP32E-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, %lo(var+12)(a7)
-; RV32I-ILP32E-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, %lo(var+8)(a7)
-; RV32I-ILP32E-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, %lo(var+4)(a7)
-; RV32I-ILP32E-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, %lo(var)(a7)
-; RV32I-ILP32E-NEXT: lw ra, 32(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: lw s0, 28(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: lw s1, 24(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT: lui a0, %hi(var)
+; RV32I-ILP32E-NEXT: addi a0, a0, %lo(var)
+; RV32I-ILP32E-NEXT: lw a1, 0(a0)
+; RV32I-ILP32E-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: lw a1, 4(a0)
+; RV32I-ILP32E-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: lw a1, 8(a0)
+; RV32I-ILP32E-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: lw a1, 12(a0)
+; RV32I-ILP32E-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: lw a1, 16(a0)
+; RV32I-ILP32E-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: lw a6, 20(a0)
+; RV32I-ILP32E-NEXT: lw a7, 24(a0)
+; RV32I-ILP32E-NEXT: lw t0, 28(a0)
+; RV32I-ILP32E-NEXT: lw t1, 32(a0)
+; RV32I-ILP32E-NEXT: lw t2, 36(a0)
+; RV32I-ILP32E-NEXT: lw t3, 40(a0)
+; RV32I-ILP32E-NEXT: lw t4, 44(a0)
+; RV32I-ILP32E-NEXT: lw t5, 48(a0)
+; RV32I-ILP32E-NEXT: lw t6, 52(a0)
+; RV32I-ILP32E-NEXT: lw s2, 56(a0)
+; RV32I-ILP32E-NEXT: lw s3, 60(a0)
+; RV32I-ILP32E-NEXT: lw s4, 64(a0)
+; RV32I-ILP32E-NEXT: lw s5, 68(a0)
+; RV32I-ILP32E-NEXT: lw s6, 72(a0)
+; RV32I-ILP32E-NEXT: lw s7, 76(a0)
+; RV32I-ILP32E-NEXT: lw s8, 80(a0)
+; RV32I-ILP32E-NEXT: lw s9, 84(a0)
+; RV32I-ILP32E-NEXT: lw s10, 88(a0)
+; RV32I-ILP32E-NEXT: lw s11, 92(a0)
+; RV32I-ILP32E-NEXT: lw s0, 112(a0)
+; RV32I-ILP32E-NEXT: lw s1, 116(a0)
+; RV32I-ILP32E-NEXT: lw ra, 120(a0)
+; RV32I-ILP32E-NEXT: lw a1, 124(a0)
+; RV32I-ILP32E-NEXT: lw a5, 96(a0)
+; RV32I-ILP32E-NEXT: lw a4, 100(a0)
+; RV32I-ILP32E-NEXT: lw a3, 104(a0)
+; RV32I-ILP32E-NEXT: lw a2, 108(a0)
+; RV32I-ILP32E-NEXT: sw a1, 124(a0)
+; RV32I-ILP32E-NEXT: sw ra, 120(a0)
+; RV32I-ILP32E-NEXT: sw s1, 116(a0)
+; RV32I-ILP32E-NEXT: sw s0, 112(a0)
+; RV32I-ILP32E-NEXT: sw a2, 108(a0)
+; RV32I-ILP32E-NEXT: sw a3, 104(a0)
+; RV32I-ILP32E-NEXT: sw a4, 100(a0)
+; RV32I-ILP32E-NEXT: sw a5, 96(a0)
+; RV32I-ILP32E-NEXT: sw s11, 92(a0)
+; RV32I-ILP32E-NEXT: sw s10, 88(a0)
+; RV32I-ILP32E-NEXT: sw s9, 84(a0)
+; RV32I-ILP32E-NEXT: sw s8, 80(a0)
+; RV32I-ILP32E-NEXT: sw s7, 76(a0)
+; RV32I-ILP32E-NEXT: sw s6, 72(a0)
+; RV32I-ILP32E-NEXT: sw s5, 68(a0)
+; RV32I-ILP32E-NEXT: sw s4, 64(a0)
+; RV32I-ILP32E-NEXT: sw s3, 60(a0)
+; RV32I-ILP32E-NEXT: sw s2, 56(a0)
+; RV32I-ILP32E-NEXT: sw t6, 52(a0)
+; RV32I-ILP32E-NEXT: sw t5, 48(a0)
+; RV32I-ILP32E-NEXT: sw t4, 44(a0)
+; RV32I-ILP32E-NEXT: sw t3, 40(a0)
+; RV32I-ILP32E-NEXT: sw t2, 36(a0)
+; RV32I-ILP32E-NEXT: sw t1, 32(a0)
+; RV32I-ILP32E-NEXT: sw t0, 28(a0)
+; RV32I-ILP32E-NEXT: sw a7, 24(a0)
+; RV32I-ILP32E-NEXT: sw a6, 20(a0)
+; RV32I-ILP32E-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT: sw a1, 16(a0)
+; RV32I-ILP32E-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT: sw a1, 12(a0)
+; RV32I-ILP32E-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT: sw a1, 8(a0)
+; RV32I-ILP32E-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT: sw a1, 4(a0)
+; RV32I-ILP32E-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT: sw a1, 0(a0)
+; RV32I-ILP32E-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-ILP32E-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-ILP32E-NEXT: .cfi_restore ra
; RV32I-ILP32E-NEXT: .cfi_restore s0
; RV32I-ILP32E-NEXT: .cfi_restore s1
-; RV32I-ILP32E-NEXT: addi sp, sp, 36
+; RV32I-ILP32E-NEXT: addi sp, sp, 32
; RV32I-ILP32E-NEXT: .cfi_def_cfa_offset 0
; RV32I-ILP32E-NEXT: ret
;
@@ -306,86 +302,84 @@ define void @callee() {
; RV32I-WITH-FP-NEXT: .cfi_offset s11, -52
; RV32I-WITH-FP-NEXT: addi s0, sp, 80
; RV32I-WITH-FP-NEXT: .cfi_def_cfa s0, 0
-; RV32I-WITH-FP-NEXT: lui t0, %hi(var)
-; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(t0)
-; RV32I-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(t0)
-; RV32I-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(t0)
-; RV32I-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(t0)
-; RV32I-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: addi a5, t0, %lo(var)
-; RV32I-WITH-FP-NEXT: lw a0, 16(a5)
-; RV32I-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 20(a5)
-; RV32I-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 24(a5)
-; RV32I-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw t1, 28(a5)
-; RV32I-WITH-FP-NEXT: lw t2, 32(a5)
-; RV32I-WITH-FP-NEXT: lw t3, 36(a5)
-; RV32I-WITH-FP-NEXT: lw t4, 40(a5)
-; RV32I-WITH-FP-NEXT: lw t5, 44(a5)
-; RV32I-WITH-FP-NEXT: lw t6, 48(a5)
-; RV32I-WITH-FP-NEXT: lw s1, 52(a5)
-; RV32I-WITH-FP-NEXT: lw s2, 56(a5)
-; RV32I-WITH-FP-NEXT: lw s3, 60(a5)
-; RV32I-WITH-FP-NEXT: lw s4, 64(a5)
-; RV32I-WITH-FP-NEXT: lw s5, 68(a5)
-; RV32I-WITH-FP-NEXT: lw s6, 72(a5)
-; RV32I-WITH-FP-NEXT: lw s7, 76(a5)
-; RV32I-WITH-FP-NEXT: lw s8, 80(a5)
-; RV32I-WITH-FP-NEXT: lw s9, 84(a5)
-; RV32I-WITH-FP-NEXT: lw s10, 88(a5)
-; RV32I-WITH-FP-NEXT: lw s11, 92(a5)
-; RV32I-WITH-FP-NEXT: lw ra, 112(a5)
-; RV32I-WITH-FP-NEXT: lw a4, 116(a5)
-; RV32I-WITH-FP-NEXT: lw a3, 120(a5)
-; RV32I-WITH-FP-NEXT: lw a0, 124(a5)
-; RV32I-WITH-FP-NEXT: lw a7, 96(a5)
-; RV32I-WITH-FP-NEXT: lw a6, 100(a5)
-; RV32I-WITH-FP-NEXT: lw a2, 104(a5)
-; RV32I-WITH-FP-NEXT: lw a1, 108(a5)
-; RV32I-WITH-FP-NEXT: sw a0, 124(a5)
-; RV32I-WITH-FP-NEXT: sw a3, 120(a5)
-; RV32I-WITH-FP-NEXT: sw a4, 116(a5)
-; RV32I-WITH-FP-NEXT: sw ra, 112(a5)
-; RV32I-WITH-FP-NEXT: sw a1, 108(a5)
-; RV32I-WITH-FP-NEXT: sw a2, 104(a5)
-; RV32I-WITH-FP-NEXT: sw a6, 100(a5)
-; RV32I-WITH-FP-NEXT: sw a7, 96(a5)
-; RV32I-WITH-FP-NEXT: sw s11, 92(a5)
-; RV32I-WITH-FP-NEXT: sw s10, 88(a5)
-; RV32I-WITH-FP-NEXT: sw s9, 84(a5)
-; RV32I-WITH-FP-NEXT: sw s8, 80(a5)
-; RV32I-WITH-FP-NEXT: sw s7, 76(a5)
-; RV32I-WITH-FP-NEXT: sw s6, 72(a5)
-; RV32I-WITH-FP-NEXT: sw s5, 68(a5)
-; RV32I-WITH-FP-NEXT: sw s4, 64(a5)
-; RV32I-WITH-FP-NEXT: sw s3, 60(a5)
-; RV32I-WITH-FP-NEXT: sw s2, 56(a5)
-; RV32I-WITH-FP-NEXT: sw s1, 52(a5)
-; RV32I-WITH-FP-NEXT: sw t6, 48(a5)
-; RV32I-WITH-FP-NEXT: sw t5, 44(a5)
-; RV32I-WITH-FP-NEXT: sw t4, 40(a5)
-; RV32I-WITH-FP-NEXT: sw t3, 36(a5)
-; RV32I-WITH-FP-NEXT: sw t2, 32(a5)
-; RV32I-WITH-FP-NEXT: sw t1, 28(a5)
-; RV32I-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 24(a5)
-; RV32I-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 20(a5)
-; RV32I-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 16(a5)
-; RV32I-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(t0)
-; RV32I-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(t0)
-; RV32I-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(t0)
-; RV32I-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(t0)
+; RV32I-WITH-FP-NEXT: lui a0, %hi(var)
+; RV32I-WITH-FP-NEXT: addi a0, a0, %lo(var)
+; RV32I-WITH-FP-NEXT: lw a1, 0(a0)
+; RV32I-WITH-FP-NEXT: sw a1, -56(s0) # 4-byte Folded Spill
+; RV32I-WITH-FP-NEXT: lw a1, 4(a0)
+; RV32I-WITH-FP-NEXT: sw a1, -60(s0) # 4-byte Folded Spill
+; RV32I-WITH-FP-NEXT: lw a1, 8(a0)
+; RV32I-WITH-FP-NEXT: sw a1, -64(s0) # 4-byte Folded Spill
+; RV32I-WITH-FP-NEXT: lw a1, 12(a0)
+; RV32I-WITH-FP-NEXT: sw a1, -68(s0) # 4-byte Folded Spill
+; RV32I-WITH-FP-NEXT: lw a1, 16(a0)
+; RV32I-WITH-FP-NEXT: sw a1, -72(s0) # 4-byte Folded Spill
+; RV32I-WITH-FP-NEXT: lw a1, 20(a0)
+; RV32I-WITH-FP-NEXT: sw a1, -76(s0) # 4-byte Folded Spill
+; RV32I-WITH-FP-NEXT: lw a7, 24(a0)
+; RV32I-WITH-FP-NEXT: lw t0, 28(a0)
+; RV32I-WITH-FP-NEXT: lw t1, 32(a0)
+; RV32I-WITH-FP-NEXT: lw t2, 36(a0)
+; RV32I-WITH-FP-NEXT: lw t3, 40(a0)
+; RV32I-WITH-FP-NEXT: lw t4, 44(a0)
+; RV32I-WITH-FP-NEXT: lw t5, 48(a0)
+; RV32I-WITH-FP-NEXT: lw t6, 52(a0)
+; RV32I-WITH-FP-NEXT: lw s1, 56(a0)
+; RV32I-WITH-FP-NEXT: lw s2, 60(a0)
+; RV32I-WITH-FP-NEXT: lw s3, 64(a0)
+; RV32I-WITH-FP-NEXT: lw s4, 68(a0)
+; RV32I-WITH-FP-NEXT: lw s5, 72(a0)
+; RV32I-WITH-FP-NEXT: lw s6, 76(a0)
+; RV32I-WITH-FP-NEXT: lw s7, 80(a0)
+; RV32I-WITH-FP-NEXT: lw s8, 84(a0)
+; RV32I-WITH-FP-NEXT: lw s9, 88(a0)
+; RV32I-WITH-FP-NEXT: lw s10, 92(a0)
+; RV32I-WITH-FP-NEXT: lw s11, 112(a0)
+; RV32I-WITH-FP-NEXT: lw ra, 116(a0)
+; RV32I-WITH-FP-NEXT: lw a4, 120(a0)
+; RV32I-WITH-FP-NEXT: lw a1, 124(a0)
+; RV32I-WITH-FP-NEXT: lw a6, 96(a0)
+; RV32I-WITH-FP-NEXT: lw a5, 100(a0)
+; RV32I-WITH-FP-NEXT: lw a3, 104(a0)
+; RV32I-WITH-FP-NEXT: lw a2, 108(a0)
+; RV32I-WITH-FP-NEXT: sw a1, 124(a0)
+; RV32I-WITH-FP-NEXT: sw a4, 120(a0)
+; RV32I-WITH-FP-NEXT: sw ra, 116(a0)
+; RV32I-WITH-FP-NEXT: sw s11, 112(a0)
+; RV32I-WITH-FP-NEXT: sw a2, 108(a0)
+; RV32I-WITH-FP-NEXT: sw a3, 104(a0)
+; RV32I-WITH-FP-NEXT: sw a5, 100(a0)
+; RV32I-WITH-FP-NEXT: sw a6, 96(a0)
+; RV32I-WITH-FP-NEXT: sw s10, 92(a0)
+; RV32I-WITH-FP-NEXT: sw s9, 88(a0)
+; RV32I-WITH-FP-NEXT: sw s8, 84(a0)
+; RV32I-WITH-FP-NEXT: sw s7, 80(a0)
+; RV32I-WITH-FP-NEXT: sw s6, 76(a0)
+; RV32I-WITH-FP-NEXT: sw s5, 72(a0)
+; RV32I-WITH-FP-NEXT: sw s4, 68(a0)
+; RV32I-WITH-FP-NEXT: sw s3, 64(a0)
+; RV32I-WITH-FP-NEXT: sw s2, 60(a0)
+; RV32I-WITH-FP-NEXT: sw s1, 56(a0)
+; RV32I-WITH-FP-NEXT: sw t6, 52(a0)
+; RV32I-WITH-FP-NEXT: sw t5, 48(a0)
+; RV32I-WITH-FP-NEXT: sw t4, 44(a0)
+; RV32I-WITH-FP-NEXT: sw t3, 40(a0)
+; RV32I-WITH-FP-NEXT: sw t2, 36(a0)
+; RV32I-WITH-FP-NEXT: sw t1, 32(a0)
+; RV32I-WITH-FP-NEXT: sw t0, 28(a0)
+; RV32I-WITH-FP-NEXT: sw a7, 24(a0)
+; RV32I-WITH-FP-NEXT: lw a1, -76(s0) # 4-byte Folded Reload
+; RV32I-WITH-FP-NEXT: sw a1, 20(a0)
+; RV32I-WITH-FP-NEXT: lw a1, -72(s0) # 4-byte Folded Reload
+; RV32I-WITH-FP-NEXT: sw a1, 16(a0)
+; RV32I-WITH-FP-NEXT: lw a1, -68(s0) # 4-byte Folded Reload
+; RV32I-WITH-FP-NEXT: sw a1, 12(a0)
+; RV32I-WITH-FP-NEXT: lw a1, -64(s0) # 4-byte Folded Reload
+; RV32I-WITH-FP-NEXT: sw a1, 8(a0)
+; RV32I-WITH-FP-NEXT: lw a1, -60(s0) # 4-byte Folded Reload
+; RV32I-WITH-FP-NEXT: sw a1, 4(a0)
+; RV32I-WITH-FP-NEXT: lw a1, -56(s0) # 4-byte Folded Reload
+; RV32I-WITH-FP-NEXT: sw a1, 0(a0)
; RV32I-WITH-FP-NEXT: .cfi_def_cfa sp, 80
; RV32I-WITH-FP-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -434,84 +428,82 @@ define void @callee() {
; RV32IZCMP-NEXT: .cfi_offset s9, -12
; RV32IZCMP-NEXT: .cfi_offset s10, -8
; RV32IZCMP-NEXT: .cfi_offset s11, -4
-; RV32IZCMP-NEXT: lui t0, %hi(var)
-; RV32IZCMP-NEXT: lw a0, %lo(var)(t0)
-; RV32IZCMP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var+4)(t0)
-; RV32IZCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var+8)(t0)
-; RV32IZCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var+12)(t0)
-; RV32IZCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: addi a5, t0, %lo(var)
-; RV32IZCMP-NEXT: lw a0, 16(a5)
-; RV32IZCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 20(a5)
-; RV32IZCMP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw t4, 24(a5)
-; RV32IZCMP-NEXT: lw t5, 28(a5)
-; RV32IZCMP-NEXT: lw t6, 32(a5)
-; RV32IZCMP-NEXT: lw s2, 36(a5)
-; RV32IZCMP-NEXT: lw s3, 40(a5)
-; RV32IZCMP-NEXT: lw s4, 44(a5)
-; RV32IZCMP-NEXT: lw s5, 48(a5)
-; RV32IZCMP-NEXT: lw s6, 52(a5)
-; RV32IZCMP-NEXT: lw s7, 56(a5)
-; RV32IZCMP-NEXT: lw s8, 60(a5)
-; RV32IZCMP-NEXT: lw s9, 64(a5)
-; RV32IZCMP-NEXT: lw s10, 68(a5)
-; RV32IZCMP-NEXT: lw s11, 72(a5)
-; RV32IZCMP-NEXT: lw ra, 76(a5)
-; RV32IZCMP-NEXT: lw s1, 80(a5)
-; RV32IZCMP-NEXT: lw t3, 84(a5)
-; RV32IZCMP-NEXT: lw t2, 88(a5)
-; RV32IZCMP-NEXT: lw t1, 92(a5)
-; RV32IZCMP-NEXT: lw a7, 112(a5)
-; RV32IZCMP-NEXT: lw s0, 116(a5)
-; RV32IZCMP-NEXT: lw a3, 120(a5)
-; RV32IZCMP-NEXT: lw a0, 124(a5)
-; RV32IZCMP-NEXT: lw a6, 96(a5)
-; RV32IZCMP-NEXT: lw a4, 100(a5)
-; RV32IZCMP-NEXT: lw a2, 104(a5)
-; RV32IZCMP-NEXT: lw a1, 108(a5)
-; RV32IZCMP-NEXT: sw a0, 124(a5)
-; RV32IZCMP-NEXT: sw a3, 120(a5)
-; RV32IZCMP-NEXT: sw s0, 116(a5)
-; RV32IZCMP-NEXT: sw a7, 112(a5)
-; RV32IZCMP-NEXT: sw a1, 108(a5)
-; RV32IZCMP-NEXT: sw a2, 104(a5)
-; RV32IZCMP-NEXT: sw a4, 100(a5)
-; RV32IZCMP-NEXT: sw a6, 96(a5)
-; RV32IZCMP-NEXT: sw t1, 92(a5)
-; RV32IZCMP-NEXT: sw t2, 88(a5)
-; RV32IZCMP-NEXT: sw t3, 84(a5)
-; RV32IZCMP-NEXT: sw s1, 80(a5)
-; RV32IZCMP-NEXT: sw ra, 76(a5)
-; RV32IZCMP-NEXT: sw s11, 72(a5)
-; RV32IZCMP-NEXT: sw s10, 68(a5)
-; RV32IZCMP-NEXT: sw s9, 64(a5)
-; RV32IZCMP-NEXT: sw s8, 60(a5)
-; RV32IZCMP-NEXT: sw s7, 56(a5)
-; RV32IZCMP-NEXT: sw s6, 52(a5)
-; RV32IZCMP-NEXT: sw s5, 48(a5)
-; RV32IZCMP-NEXT: sw s4, 44(a5)
-; RV32IZCMP-NEXT: sw s3, 40(a5)
-; RV32IZCMP-NEXT: sw s2, 36(a5)
-; RV32IZCMP-NEXT: sw t6, 32(a5)
-; RV32IZCMP-NEXT: sw t5, 28(a5)
-; RV32IZCMP-NEXT: sw t4, 24(a5)
-; RV32IZCMP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 20(a5)
-; RV32IZCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 16(a5)
-; RV32IZCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var+12)(t0)
-; RV32IZCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var+8)(t0)
-; RV32IZCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var+4)(t0)
-; RV32IZCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var)(t0)
+; RV32IZCMP-NEXT: lui a0, %hi(var)
+; RV32IZCMP-NEXT: addi a0, a0, %lo(var)
+; RV32IZCMP-NEXT: lw a1, 0(a0)
+; RV32IZCMP-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 4(a0)
+; RV32IZCMP-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 8(a0)
+; RV32IZCMP-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 12(a0)
+; RV32IZCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 16(a0)
+; RV32IZCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw t3, 20(a0)
+; RV32IZCMP-NEXT: lw t4, 24(a0)
+; RV32IZCMP-NEXT: lw t5, 28(a0)
+; RV32IZCMP-NEXT: lw t6, 32(a0)
+; RV32IZCMP-NEXT: lw s2, 36(a0)
+; RV32IZCMP-NEXT: lw s3, 40(a0)
+; RV32IZCMP-NEXT: lw s4, 44(a0)
+; RV32IZCMP-NEXT: lw s5, 48(a0)
+; RV32IZCMP-NEXT: lw s6, 52(a0)
+; RV32IZCMP-NEXT: lw s7, 56(a0)
+; RV32IZCMP-NEXT: lw s8, 60(a0)
+; RV32IZCMP-NEXT: lw s9, 64(a0)
+; RV32IZCMP-NEXT: lw s10, 68(a0)
+; RV32IZCMP-NEXT: lw s11, 72(a0)
+; RV32IZCMP-NEXT: lw ra, 76(a0)
+; RV32IZCMP-NEXT: lw t2, 80(a0)
+; RV32IZCMP-NEXT: lw s0, 84(a0)
+; RV32IZCMP-NEXT: lw s1, 88(a0)
+; RV32IZCMP-NEXT: lw t1, 92(a0)
+; RV32IZCMP-NEXT: lw t0, 112(a0)
+; RV32IZCMP-NEXT: lw a5, 116(a0)
+; RV32IZCMP-NEXT: lw a3, 120(a0)
+; RV32IZCMP-NEXT: lw a1, 124(a0)
+; RV32IZCMP-NEXT: lw a7, 96(a0)
+; RV32IZCMP-NEXT: lw a6, 100(a0)
+; RV32IZCMP-NEXT: lw a4, 104(a0)
+; RV32IZCMP-NEXT: lw a2, 108(a0)
+; RV32IZCMP-NEXT: sw a1, 124(a0)
+; RV32IZCMP-NEXT: sw a3, 120(a0)
+; RV32IZCMP-NEXT: sw a5, 116(a0)
+; RV32IZCMP-NEXT: sw t0, 112(a0)
+; RV32IZCMP-NEXT: sw a2, 108(a0)
+; RV32IZCMP-NEXT: sw a4, 104(a0)
+; RV32IZCMP-NEXT: sw a6, 100(a0)
+; RV32IZCMP-NEXT: sw a7, 96(a0)
+; RV32IZCMP-NEXT: sw t1, 92(a0)
+; RV32IZCMP-NEXT: sw s1, 88(a0)
+; RV32IZCMP-NEXT: sw s0, 84(a0)
+; RV32IZCMP-NEXT: sw t2, 80(a0)
+; RV32IZCMP-NEXT: sw ra, 76(a0)
+; RV32IZCMP-NEXT: sw s11, 72(a0)
+; RV32IZCMP-NEXT: sw s10, 68(a0)
+; RV32IZCMP-NEXT: sw s9, 64(a0)
+; RV32IZCMP-NEXT: sw s8, 60(a0)
+; RV32IZCMP-NEXT: sw s7, 56(a0)
+; RV32IZCMP-NEXT: sw s6, 52(a0)
+; RV32IZCMP-NEXT: sw s5, 48(a0)
+; RV32IZCMP-NEXT: sw s4, 44(a0)
+; RV32IZCMP-NEXT: sw s3, 40(a0)
+; RV32IZCMP-NEXT: sw s2, 36(a0)
+; RV32IZCMP-NEXT: sw t6, 32(a0)
+; RV32IZCMP-NEXT: sw t5, 28(a0)
+; RV32IZCMP-NEXT: sw t4, 24(a0)
+; RV32IZCMP-NEXT: sw t3, 20(a0)
+; RV32IZCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 16(a0)
+; RV32IZCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 12(a0)
+; RV32IZCMP-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 8(a0)
+; RV32IZCMP-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 4(a0)
+; RV32IZCMP-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 0(a0)
; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 96
;
; RV32IZCMP-WITH-FP-LABEL: callee:
@@ -546,86 +538,84 @@ define void @callee() {
; RV32IZCMP-WITH-FP-NEXT: .cfi_offset s11, -52
; RV32IZCMP-WITH-FP-NEXT: addi s0, sp, 80
; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
-; RV32IZCMP-WITH-FP-NEXT: lui t1, %hi(var)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var)(t1)
-; RV32IZCMP-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(t1)
-; RV32IZCMP-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(t1)
-; RV32IZCMP-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(t1)
-; RV32IZCMP-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: addi a5, t1, %lo(var)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, 16(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw a0, 20(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw a0, 24(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw t5, 28(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw t6, 32(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s2, 36(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s3, 40(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s4, 44(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s5, 48(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s6, 52(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s7, 56(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s8, 60(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s9, 64(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s10, 68(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s11, 72(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw ra, 76(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw t4, 80(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw t3, 84(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw t2, 88(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw s1, 92(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw t0, 112(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a4, 116(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a3, 120(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, 124(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a7, 96(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a6, 100(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a2, 104(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a1, 108(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw a0, 124(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw a3, 120(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw a4, 116(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw t0, 112(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw a1, 108(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw a2, 104(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw a6, 100(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw a7, 96(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s1, 92(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw t2, 88(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw t3, 84(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw t4, 80(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw ra, 76(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s11, 72(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s10, 68(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s9, 64(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s8, 60(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s7, 56(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s6, 52(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s5, 48(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s4, 44(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s3, 40(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw s2, 36(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw t6, 32(a5)
-; RV32IZCMP-WITH-FP-NEXT: sw t5, 28(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, 24(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, 20(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, 16(a5)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(t1)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(t1)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(t1)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var)(t1)
+; RV32IZCMP-WITH-FP-NEXT: lui a0, %hi(var)
+; RV32IZCMP-WITH-FP-NEXT: addi a0, a0, %lo(var)
+; RV32IZCMP-WITH-FP-NEXT: lw a1, 0(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a1, -56(s0) # 4-byte Folded Spill
+; RV32IZCMP-WITH-FP-NEXT: lw a1, 4(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a1, -60(s0) # 4-byte Folded Spill
+; RV32IZCMP-WITH-FP-NEXT: lw a1, 8(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a1, -64(s0) # 4-byte Folded Spill
+; RV32IZCMP-WITH-FP-NEXT: lw a1, 12(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a1, -68(s0) # 4-byte Folded Spill
+; RV32IZCMP-WITH-FP-NEXT: lw a1, 16(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a1, -72(s0) # 4-byte Folded Spill
+; RV32IZCMP-WITH-FP-NEXT: lw a1, 20(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a1, -76(s0) # 4-byte Folded Spill
+; RV32IZCMP-WITH-FP-NEXT: lw t4, 24(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t5, 28(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t6, 32(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s2, 36(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s3, 40(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s4, 44(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s5, 48(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s6, 52(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s7, 56(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s8, 60(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s9, 64(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s10, 68(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s11, 72(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw ra, 76(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s1, 80(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t3, 84(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t2, 88(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t1, 92(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t0, 112(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a6, 116(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a4, 120(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a1, 124(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a7, 96(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a5, 100(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a3, 104(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a2, 108(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a1, 124(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a4, 120(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a6, 116(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t0, 112(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a2, 108(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a3, 104(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a5, 100(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a7, 96(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t1, 92(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t2, 88(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t3, 84(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s1, 80(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw ra, 76(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s11, 72(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s10, 68(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s9, 64(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s8, 60(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s7, 56(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s6, 52(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s5, 48(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s4, 44(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s3, 40(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s2, 36(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t6, 32(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t5, 28(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t4, 24(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a1, -76(s0) # 4-byte Folded Reload
+; RV32IZCMP-WITH-FP-NEXT: sw a1, 20(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a1, -72(s0) # 4-byte Folded Reload
+; RV32IZCMP-WITH-FP-NEXT: sw a1, 16(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a1, -68(s0) # 4-byte Folded Reload
+; RV32IZCMP-WITH-FP-NEXT: sw a1, 12(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a1, -64(s0) # 4-byte Folded Reload
+; RV32IZCMP-WITH-FP-NEXT: sw a1, 8(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a1, -60(s0) # 4-byte Folded Reload
+; RV32IZCMP-WITH-FP-NEXT: sw a1, 4(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a1, -56(s0) # 4-byte Folded Reload
+; RV32IZCMP-WITH-FP-NEXT: sw a1, 0(a0)
; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa sp, 80
; RV32IZCMP-WITH-FP-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -659,21 +649,21 @@ define void @callee() {
;
; RV64I-LABEL: callee:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -160
-; RV64I-NEXT: .cfi_def_cfa_offset 160
-; RV64I-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s4, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s5, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s6, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s7, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s8, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s9, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s10, 64(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s11, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -144
+; RV64I-NEXT: .cfi_def_cfa_offset 144
+; RV64I-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 128(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 120(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 104(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s5, 88(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s6, 80(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s7, 72(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s8, 64(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s9, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s10, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s11, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
@@ -687,97 +677,95 @@ define void @callee() {
; RV64I-NEXT: .cfi_offset s9, -88
; RV64I-NEXT: .cfi_offset s10, -96
; RV64I-NEXT: .cfi_offset s11, -104
-; RV64I-NEXT: lui a7, %hi(var)
-; RV64I-NEXT: lw a0, %lo(var)(a7)
-; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var+4)(a7)
-; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var+8)(a7)
-; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var+12)(a7)
-; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addi a5, a7, %lo(var)
-; RV64I-NEXT: lw a0, 16(a5)
-; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 20(a5)
-; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw t0, 24(a5)
-; RV64I-NEXT: lw t1, 28(a5)
-; RV64I-NEXT: lw t2, 32(a5)
-; RV64I-NEXT: lw t3, 36(a5)
-; RV64I-NEXT: lw t4, 40(a5)
-; RV64I-NEXT: lw t5, 44(a5)
-; RV64I-NEXT: lw t6, 48(a5)
-; RV64I-NEXT: lw s0, 52(a5)
-; RV64I-NEXT: lw s1, 56(a5)
-; RV64I-NEXT: lw s2, 60(a5)
-; RV64I-NEXT: lw s3, 64(a5)
-; RV64I-NEXT: lw s4, 68(a5)
-; RV64I-NEXT: lw s5, 72(a5)
-; RV64I-NEXT: lw s6, 76(a5)
-; RV64I-NEXT: lw s7, 80(a5)
-; RV64I-NEXT: lw s8, 84(a5)
-; RV64I-NEXT: lw s9, 88(a5)
-; RV64I-NEXT: lw s10, 92(a5)
-; RV64I-NEXT: lw s11, 112(a5)
-; RV64I-NEXT: lw ra, 116(a5)
-; RV64I-NEXT: lw a3, 120(a5)
-; RV64I-NEXT: lw a0, 124(a5)
-; RV64I-NEXT: lw a6, 96(a5)
-; RV64I-NEXT: lw a4, 100(a5)
-; RV64I-NEXT: lw a2, 104(a5)
-; RV64I-NEXT: lw a1, 108(a5)
-; RV64I-NEXT: sw a0, 124(a5)
-; RV64I-NEXT: sw a3, 120(a5)
-; RV64I-NEXT: sw ra, 116(a5)
-; RV64I-NEXT: sw s11, 112(a5)
-; RV64I-NEXT: sw a1, 108(a5)
-; RV64I-NEXT: sw a2, 104(a5)
-; RV64I-NEXT: sw a4, 100(a5)
-; RV64I-NEXT: sw a6, 96(a5)
-; RV64I-NEXT: sw s10, 92(a5)
-; RV64I-NEXT: sw s9, 88(a5)
-; RV64I-NEXT: sw s8, 84(a5)
-; RV64I-NEXT: sw s7, 80(a5)
-; RV64I-NEXT: sw s6, 76(a5)
-; RV64I-NEXT: sw s5, 72(a5)
-; RV64I-NEXT: sw s4, 68(a5)
-; RV64I-NEXT: sw s3, 64(a5)
-; RV64I-NEXT: sw s2, 60(a5)
-; RV64I-NEXT: sw s1, 56(a5)
-; RV64I-NEXT: sw s0, 52(a5)
-; RV64I-NEXT: sw t6, 48(a5)
-; RV64I-NEXT: sw t5, 44(a5)
-; RV64I-NEXT: sw t4, 40(a5)
-; RV64I-NEXT: sw t3, 36(a5)
-; RV64I-NEXT: sw t2, 32(a5)
-; RV64I-NEXT: sw t1, 28(a5)
-; RV64I-NEXT: sw t0, 24(a5)
-; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 20(a5)
-; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 16(a5)
-; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var+12)(a7)
-; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var+8)(a7)
-; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var+4)(a7)
-; RV64I-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var)(a7)
-; RV64I-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 128(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s4, 112(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 104(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s6, 96(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s7, 88(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s8, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s9, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s10, 64(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s11, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: lui a0, %hi(var)
+; RV64I-NEXT: addi a0, a0, %lo(var)
+; RV64I-NEXT: lw a1, 0(a0)
+; RV64I-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 4(a0)
+; RV64I-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 8(a0)
+; RV64I-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 12(a0)
+; RV64I-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 16(a0)
+; RV64I-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a6, 20(a0)
+; RV64I-NEXT: lw a7, 24(a0)
+; RV64I-NEXT: lw t0, 28(a0)
+; RV64I-NEXT: lw t1, 32(a0)
+; RV64I-NEXT: lw t2, 36(a0)
+; RV64I-NEXT: lw t3, 40(a0)
+; RV64I-NEXT: lw t4, 44(a0)
+; RV64I-NEXT: lw t5, 48(a0)
+; RV64I-NEXT: lw t6, 52(a0)
+; RV64I-NEXT: lw s0, 56(a0)
+; RV64I-NEXT: lw s1, 60(a0)
+; RV64I-NEXT: lw s2, 64(a0)
+; RV64I-NEXT: lw s3, 68(a0)
+; RV64I-NEXT: lw s4, 72(a0)
+; RV64I-NEXT: lw s5, 76(a0)
+; RV64I-NEXT: lw s6, 80(a0)
+; RV64I-NEXT: lw s7, 84(a0)
+; RV64I-NEXT: lw s8, 88(a0)
+; RV64I-NEXT: lw s9, 92(a0)
+; RV64I-NEXT: lw s10, 112(a0)
+; RV64I-NEXT: lw s11, 116(a0)
+; RV64I-NEXT: lw ra, 120(a0)
+; RV64I-NEXT: lw a1, 124(a0)
+; RV64I-NEXT: lw a5, 96(a0)
+; RV64I-NEXT: lw a4, 100(a0)
+; RV64I-NEXT: lw a3, 104(a0)
+; RV64I-NEXT: lw a2, 108(a0)
+; RV64I-NEXT: sw a1, 124(a0)
+; RV64I-NEXT: sw ra, 120(a0)
+; RV64I-NEXT: sw s11, 116(a0)
+; RV64I-NEXT: sw s10, 112(a0)
+; RV64I-NEXT: sw a2, 108(a0)
+; RV64I-NEXT: sw a3, 104(a0)
+; RV64I-NEXT: sw a4, 100(a0)
+; RV64I-NEXT: sw a5, 96(a0)
+; RV64I-NEXT: sw s9, 92(a0)
+; RV64I-NEXT: sw s8, 88(a0)
+; RV64I-NEXT: sw s7, 84(a0)
+; RV64I-NEXT: sw s6, 80(a0)
+; RV64I-NEXT: sw s5, 76(a0)
+; RV64I-NEXT: sw s4, 72(a0)
+; RV64I-NEXT: sw s3, 68(a0)
+; RV64I-NEXT: sw s2, 64(a0)
+; RV64I-NEXT: sw s1, 60(a0)
+; RV64I-NEXT: sw s0, 56(a0)
+; RV64I-NEXT: sw t6, 52(a0)
+; RV64I-NEXT: sw t5, 48(a0)
+; RV64I-NEXT: sw t4, 44(a0)
+; RV64I-NEXT: sw t3, 40(a0)
+; RV64I-NEXT: sw t2, 36(a0)
+; RV64I-NEXT: sw t1, 32(a0)
+; RV64I-NEXT: sw t0, 28(a0)
+; RV64I-NEXT: sw a7, 24(a0)
+; RV64I-NEXT: sw a6, 20(a0)
+; RV64I-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 16(a0)
+; RV64I-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 12(a0)
+; RV64I-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 8(a0)
+; RV64I-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 4(a0)
+; RV64I-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 0(a0)
+; RV64I-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 128(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 112(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 104(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 96(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s5, 88(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s6, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s7, 72(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s8, 64(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s9, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s10, 48(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s11, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
@@ -791,105 +779,103 @@ define void @callee() {
; RV64I-NEXT: .cfi_restore s9
; RV64I-NEXT: .cfi_restore s10
; RV64I-NEXT: .cfi_restore s11
-; RV64I-NEXT: addi sp, sp, 160
+; RV64I-NEXT: addi sp, sp, 144
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
; RV64I-LP64E-LABEL: callee:
; RV64I-LP64E: # %bb.0:
-; RV64I-LP64E-NEXT: addi sp, sp, -72
-; RV64I-LP64E-NEXT: .cfi_def_cfa_offset 72
-; RV64I-LP64E-NEXT: sd ra, 64(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: sd s0, 56(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: sd s1, 48(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: addi sp, sp, -64
+; RV64I-LP64E-NEXT: .cfi_def_cfa_offset 64
+; RV64I-LP64E-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
; RV64I-LP64E-NEXT: .cfi_offset ra, -8
; RV64I-LP64E-NEXT: .cfi_offset s0, -16
; RV64I-LP64E-NEXT: .cfi_offset s1, -24
-; RV64I-LP64E-NEXT: lui a7, %hi(var)
-; RV64I-LP64E-NEXT: lw a0, %lo(var)(a7)
-; RV64I-LP64E-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, %lo(var+4)(a7)
-; RV64I-LP64E-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, %lo(var+8)(a7)
-; RV64I-LP64E-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, %lo(var+12)(a7)
-; RV64I-LP64E-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: addi a5, a7, %lo(var)
-; RV64I-LP64E-NEXT: lw a0, 16(a5)
-; RV64I-LP64E-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 20(a5)
-; RV64I-LP64E-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw t0, 24(a5)
-; RV64I-LP64E-NEXT: lw t1, 28(a5)
-; RV64I-LP64E-NEXT: lw t2, 32(a5)
-; RV64I-LP64E-NEXT: lw t3, 36(a5)
-; RV64I-LP64E-NEXT: lw t4, 40(a5)
-; RV64I-LP64E-NEXT: lw t5, 44(a5)
-; RV64I-LP64E-NEXT: lw t6, 48(a5)
-; RV64I-LP64E-NEXT: lw s2, 52(a5)
-; RV64I-LP64E-NEXT: lw s3, 56(a5)
-; RV64I-LP64E-NEXT: lw s4, 60(a5)
-; RV64I-LP64E-NEXT: lw s5, 64(a5)
-; RV64I-LP64E-NEXT: lw s6, 68(a5)
-; RV64I-LP64E-NEXT: lw s7, 72(a5)
-; RV64I-LP64E-NEXT: lw s8, 76(a5)
-; RV64I-LP64E-NEXT: lw s9, 80(a5)
-; RV64I-LP64E-NEXT: lw s10, 84(a5)
-; RV64I-LP64E-NEXT: lw s11, 88(a5)
-; RV64I-LP64E-NEXT: lw s0, 92(a5)
-; RV64I-LP64E-NEXT: lw s1, 112(a5)
-; RV64I-LP64E-NEXT: lw ra, 116(a5)
-; RV64I-LP64E-NEXT: lw a3, 120(a5)
-; RV64I-LP64E-NEXT: lw a0, 124(a5)
-; RV64I-LP64E-NEXT: lw a6, 96(a5)
-; RV64I-LP64E-NEXT: lw a4, 100(a5)
-; RV64I-LP64E-NEXT: lw a2, 104(a5)
-; RV64I-LP64E-NEXT: lw a1, 108(a5)
-; RV64I-LP64E-NEXT: sw a0, 124(a5)
-; RV64I-LP64E-NEXT: sw a3, 120(a5)
-; RV64I-LP64E-NEXT: sw ra, 116(a5)
-; RV64I-LP64E-NEXT: sw s1, 112(a5)
-; RV64I-LP64E-NEXT: sw a1, 108(a5)
-; RV64I-LP64E-NEXT: sw a2, 104(a5)
-; RV64I-LP64E-NEXT: sw a4, 100(a5)
-; RV64I-LP64E-NEXT: sw a6, 96(a5)
-; RV64I-LP64E-NEXT: sw s0, 92(a5)
-; RV64I-LP64E-NEXT: sw s11, 88(a5)
-; RV64I-LP64E-NEXT: sw s10, 84(a5)
-; RV64I-LP64E-NEXT: sw s9, 80(a5)
-; RV64I-LP64E-NEXT: sw s8, 76(a5)
-; RV64I-LP64E-NEXT: sw s7, 72(a5)
-; RV64I-LP64E-NEXT: sw s6, 68(a5)
-; RV64I-LP64E-NEXT: sw s5, 64(a5)
-; RV64I-LP64E-NEXT: sw s4, 60(a5)
-; RV64I-LP64E-NEXT: sw s3, 56(a5)
-; RV64I-LP64E-NEXT: sw s2, 52(a5)
-; RV64I-LP64E-NEXT: sw t6, 48(a5)
-; RV64I-LP64E-NEXT: sw t5, 44(a5)
-; RV64I-LP64E-NEXT: sw t4, 40(a5)
-; RV64I-LP64E-NEXT: sw t3, 36(a5)
-; RV64I-LP64E-NEXT: sw t2, 32(a5)
-; RV64I-LP64E-NEXT: sw t1, 28(a5)
-; RV64I-LP64E-NEXT: sw t0, 24(a5)
-; RV64I-LP64E-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 20(a5)
-; RV64I-LP64E-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 16(a5)
-; RV64I-LP64E-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, %lo(var+12)(a7)
-; RV64I-LP64E-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, %lo(var+8)(a7)
-; RV64I-LP64E-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, %lo(var+4)(a7)
-; RV64I-LP64E-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, %lo(var)(a7)
-; RV64I-LP64E-NEXT: ld ra, 64(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: ld s0, 56(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: ld s1, 48(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT: lui a0, %hi(var)
+; RV64I-LP64E-NEXT: addi a0, a0, %lo(var)
+; RV64I-LP64E-NEXT: lw a1, 0(a0)
+; RV64I-LP64E-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: lw a1, 4(a0)
+; RV64I-LP64E-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: lw a1, 8(a0)
+; RV64I-LP64E-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: lw a1, 12(a0)
+; RV64I-LP64E-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: lw a1, 16(a0)
+; RV64I-LP64E-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: lw a6, 20(a0)
+; RV64I-LP64E-NEXT: lw a7, 24(a0)
+; RV64I-LP64E-NEXT: lw t0, 28(a0)
+; RV64I-LP64E-NEXT: lw t1, 32(a0)
+; RV64I-LP64E-NEXT: lw t2, 36(a0)
+; RV64I-LP64E-NEXT: lw t3, 40(a0)
+; RV64I-LP64E-NEXT: lw t4, 44(a0)
+; RV64I-LP64E-NEXT: lw t5, 48(a0)
+; RV64I-LP64E-NEXT: lw t6, 52(a0)
+; RV64I-LP64E-NEXT: lw s2, 56(a0)
+; RV64I-LP64E-NEXT: lw s3, 60(a0)
+; RV64I-LP64E-NEXT: lw s4, 64(a0)
+; RV64I-LP64E-NEXT: lw s5, 68(a0)
+; RV64I-LP64E-NEXT: lw s6, 72(a0)
+; RV64I-LP64E-NEXT: lw s7, 76(a0)
+; RV64I-LP64E-NEXT: lw s8, 80(a0)
+; RV64I-LP64E-NEXT: lw s9, 84(a0)
+; RV64I-LP64E-NEXT: lw s10, 88(a0)
+; RV64I-LP64E-NEXT: lw s11, 92(a0)
+; RV64I-LP64E-NEXT: lw s0, 112(a0)
+; RV64I-LP64E-NEXT: lw s1, 116(a0)
+; RV64I-LP64E-NEXT: lw ra, 120(a0)
+; RV64I-LP64E-NEXT: lw a1, 124(a0)
+; RV64I-LP64E-NEXT: lw a5, 96(a0)
+; RV64I-LP64E-NEXT: lw a4, 100(a0)
+; RV64I-LP64E-NEXT: lw a3, 104(a0)
+; RV64I-LP64E-NEXT: lw a2, 108(a0)
+; RV64I-LP64E-NEXT: sw a1, 124(a0)
+; RV64I-LP64E-NEXT: sw ra, 120(a0)
+; RV64I-LP64E-NEXT: sw s1, 116(a0)
+; RV64I-LP64E-NEXT: sw s0, 112(a0)
+; RV64I-LP64E-NEXT: sw a2, 108(a0)
+; RV64I-LP64E-NEXT: sw a3, 104(a0)
+; RV64I-LP64E-NEXT: sw a4, 100(a0)
+; RV64I-LP64E-NEXT: sw a5, 96(a0)
+; RV64I-LP64E-NEXT: sw s11, 92(a0)
+; RV64I-LP64E-NEXT: sw s10, 88(a0)
+; RV64I-LP64E-NEXT: sw s9, 84(a0)
+; RV64I-LP64E-NEXT: sw s8, 80(a0)
+; RV64I-LP64E-NEXT: sw s7, 76(a0)
+; RV64I-LP64E-NEXT: sw s6, 72(a0)
+; RV64I-LP64E-NEXT: sw s5, 68(a0)
+; RV64I-LP64E-NEXT: sw s4, 64(a0)
+; RV64I-LP64E-NEXT: sw s3, 60(a0)
+; RV64I-LP64E-NEXT: sw s2, 56(a0)
+; RV64I-LP64E-NEXT: sw t6, 52(a0)
+; RV64I-LP64E-NEXT: sw t5, 48(a0)
+; RV64I-LP64E-NEXT: sw t4, 44(a0)
+; RV64I-LP64E-NEXT: sw t3, 40(a0)
+; RV64I-LP64E-NEXT: sw t2, 36(a0)
+; RV64I-LP64E-NEXT: sw t1, 32(a0)
+; RV64I-LP64E-NEXT: sw t0, 28(a0)
+; RV64I-LP64E-NEXT: sw a7, 24(a0)
+; RV64I-LP64E-NEXT: sw a6, 20(a0)
+; RV64I-LP64E-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT: sw a1, 16(a0)
+; RV64I-LP64E-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT: sw a1, 12(a0)
+; RV64I-LP64E-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT: sw a1, 8(a0)
+; RV64I-LP64E-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT: sw a1, 4(a0)
+; RV64I-LP64E-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT: sw a1, 0(a0)
+; RV64I-LP64E-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
+; RV64I-LP64E-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; RV64I-LP64E-NEXT: .cfi_restore ra
; RV64I-LP64E-NEXT: .cfi_restore s0
; RV64I-LP64E-NEXT: .cfi_restore s1
-; RV64I-LP64E-NEXT: addi sp, sp, 72
+; RV64I-LP64E-NEXT: addi sp, sp, 64
; RV64I-LP64E-NEXT: .cfi_def_cfa_offset 0
; RV64I-LP64E-NEXT: ret
;
@@ -925,86 +911,84 @@ define void @callee() {
; RV64I-WITH-FP-NEXT: .cfi_offset s11, -104
; RV64I-WITH-FP-NEXT: addi s0, sp, 160
; RV64I-WITH-FP-NEXT: .cfi_def_cfa s0, 0
-; RV64I-WITH-FP-NEXT: lui t0, %hi(var)
-; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(t0)
-; RV64I-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(t0)
-; RV64I-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(t0)
-; RV64I-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(t0)
-; RV64I-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: addi a5, t0, %lo(var)
-; RV64I-WITH-FP-NEXT: lw a0, 16(a5)
-; RV64I-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 20(a5)
-; RV64I-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 24(a5)
-; RV64I-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw t1, 28(a5)
-; RV64I-WITH-FP-NEXT: lw t2, 32(a5)
-; RV64I-WITH-FP-NEXT: lw t3, 36(a5)
-; RV64I-WITH-FP-NEXT: lw t4, 40(a5)
-; RV64I-WITH-FP-NEXT: lw t5, 44(a5)
-; RV64I-WITH-FP-NEXT: lw t6, 48(a5)
-; RV64I-WITH-FP-NEXT: lw s1, 52(a5)
-; RV64I-WITH-FP-NEXT: lw s2, 56(a5)
-; RV64I-WITH-FP-NEXT: lw s3, 60(a5)
-; RV64I-WITH-FP-NEXT: lw s4, 64(a5)
-; RV64I-WITH-FP-NEXT: lw s5, 68(a5)
-; RV64I-WITH-FP-NEXT: lw s6, 72(a5)
-; RV64I-WITH-FP-NEXT: lw s7, 76(a5)
-; RV64I-WITH-FP-NEXT: lw s8, 80(a5)
-; RV64I-WITH-FP-NEXT: lw s9, 84(a5)
-; RV64I-WITH-FP-NEXT: lw s10, 88(a5)
-; RV64I-WITH-FP-NEXT: lw s11, 92(a5)
-; RV64I-WITH-FP-NEXT: lw ra, 112(a5)
-; RV64I-WITH-FP-NEXT: lw a4, 116(a5)
-; RV64I-WITH-FP-NEXT: lw a3, 120(a5)
-; RV64I-WITH-FP-NEXT: lw a0, 124(a5)
-; RV64I-WITH-FP-NEXT: lw a7, 96(a5)
-; RV64I-WITH-FP-NEXT: lw a6, 100(a5)
-; RV64I-WITH-FP-NEXT: lw a2, 104(a5)
-; RV64I-WITH-FP-NEXT: lw a1, 108(a5)
-; RV64I-WITH-FP-NEXT: sw a0, 124(a5)
-; RV64I-WITH-FP-NEXT: sw a3, 120(a5)
-; RV64I-WITH-FP-NEXT: sw a4, 116(a5)
-; RV64I-WITH-FP-NEXT: sw ra, 112(a5)
-; RV64I-WITH-FP-NEXT: sw a1, 108(a5)
-; RV64I-WITH-FP-NEXT: sw a2, 104(a5)
-; RV64I-WITH-FP-NEXT: sw a6, 100(a5)
-; RV64I-WITH-FP-NEXT: sw a7, 96(a5)
-; RV64I-WITH-FP-NEXT: sw s11, 92(a5)
-; RV64I-WITH-FP-NEXT: sw s10, 88(a5)
-; RV64I-WITH-FP-NEXT: sw s9, 84(a5)
-; RV64I-WITH-FP-NEXT: sw s8, 80(a5)
-; RV64I-WITH-FP-NEXT: sw s7, 76(a5)
-; RV64I-WITH-FP-NEXT: sw s6, 72(a5)
-; RV64I-WITH-FP-NEXT: sw s5, 68(a5)
-; RV64I-WITH-FP-NEXT: sw s4, 64(a5)
-; RV64I-WITH-FP-NEXT: sw s3, 60(a5)
-; RV64I-WITH-FP-NEXT: sw s2, 56(a5)
-; RV64I-WITH-FP-NEXT: sw s1, 52(a5)
-; RV64I-WITH-FP-NEXT: sw t6, 48(a5)
-; RV64I-WITH-FP-NEXT: sw t5, 44(a5)
-; RV64I-WITH-FP-NEXT: sw t4, 40(a5)
-; RV64I-WITH-FP-NEXT: sw t3, 36(a5)
-; RV64I-WITH-FP-NEXT: sw t2, 32(a5)
-; RV64I-WITH-FP-NEXT: sw t1, 28(a5)
-; RV64I-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 24(a5)
-; RV64I-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 20(a5)
-; RV64I-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 16(a5)
-; RV64I-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(t0)
-; RV64I-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(t0)
-; RV64I-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(t0)
-; RV64I-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(t0)
+; RV64I-WITH-FP-NEXT: lui a0, %hi(var)
+; RV64I-WITH-FP-NEXT: addi a0, a0, %lo(var)
+; RV64I-WITH-FP-NEXT: lw a1, 0(a0)
+; RV64I-WITH-FP-NEXT: sd a1, -112(s0) # 8-byte Folded Spill
+; RV64I-WITH-FP-NEXT: lw a1, 4(a0)
+; RV64I-WITH-FP-NEXT: sd a1, -120(s0) # 8-byte Folded Spill
+; RV64I-WITH-FP-NEXT: lw a1, 8(a0)
+; RV64I-WITH-FP-NEXT: sd a1, -128(s0) # 8-byte Folded Spill
+; RV64I-WITH-FP-NEXT: lw a1, 12(a0)
+; RV64I-WITH-FP-NEXT: sd a1, -136(s0) # 8-byte Folded Spill
+; RV64I-WITH-FP-NEXT: lw a1, 16(a0)
+; RV64I-WITH-FP-NEXT: sd a1, -144(s0) # 8-byte Folded Spill
+; RV64I-WITH-FP-NEXT: lw a1, 20(a0)
+; RV64I-WITH-FP-NEXT: sd a1, -152(s0) # 8-byte Folded Spill
+; RV64I-WITH-FP-NEXT: lw a7, 24(a0)
+; RV64I-WITH-FP-NEXT: lw t0, 28(a0)
+; RV64I-WITH-FP-NEXT: lw t1, 32(a0)
+; RV64I-WITH-FP-NEXT: lw t2, 36(a0)
+; RV64I-WITH-FP-NEXT: lw t3, 40(a0)
+; RV64I-WITH-FP-NEXT: lw t4, 44(a0)
+; RV64I-WITH-FP-NEXT: lw t5, 48(a0)
+; RV64I-WITH-FP-NEXT: lw t6, 52(a0)
+; RV64I-WITH-FP-NEXT: lw s1, 56(a0)
+; RV64I-WITH-FP-NEXT: lw s2, 60(a0)
+; RV64I-WITH-FP-NEXT: lw s3, 64(a0)
+; RV64I-WITH-FP-NEXT: lw s4, 68(a0)
+; RV64I-WITH-FP-NEXT: lw s5, 72(a0)
+; RV64I-WITH-FP-NEXT: lw s6, 76(a0)
+; RV64I-WITH-FP-NEXT: lw s7, 80(a0)
+; RV64I-WITH-FP-NEXT: lw s8, 84(a0)
+; RV64I-WITH-FP-NEXT: lw s9, 88(a0)
+; RV64I-WITH-FP-NEXT: lw s10, 92(a0)
+; RV64I-WITH-FP-NEXT: lw s11, 112(a0)
+; RV64I-WITH-FP-NEXT: lw ra, 116(a0)
+; RV64I-WITH-FP-NEXT: lw a4, 120(a0)
+; RV64I-WITH-FP-NEXT: lw a1, 124(a0)
+; RV64I-WITH-FP-NEXT: lw a6, 96(a0)
+; RV64I-WITH-FP-NEXT: lw a5, 100(a0)
+; RV64I-WITH-FP-NEXT: lw a3, 104(a0)
+; RV64I-WITH-FP-NEXT: lw a2, 108(a0)
+; RV64I-WITH-FP-NEXT: sw a1, 124(a0)
+; RV64I-WITH-FP-NEXT: sw a4, 120(a0)
+; RV64I-WITH-FP-NEXT: sw ra, 116(a0)
+; RV64I-WITH-FP-NEXT: sw s11, 112(a0)
+; RV64I-WITH-FP-NEXT: sw a2, 108(a0)
+; RV64I-WITH-FP-NEXT: sw a3, 104(a0)
+; RV64I-WITH-FP-NEXT: sw a5, 100(a0)
+; RV64I-WITH-FP-NEXT: sw a6, 96(a0)
+; RV64I-WITH-FP-NEXT: sw s10, 92(a0)
+; RV64I-WITH-FP-NEXT: sw s9, 88(a0)
+; RV64I-WITH-FP-NEXT: sw s8, 84(a0)
+; RV64I-WITH-FP-NEXT: sw s7, 80(a0)
+; RV64I-WITH-FP-NEXT: sw s6, 76(a0)
+; RV64I-WITH-FP-NEXT: sw s5, 72(a0)
+; RV64I-WITH-FP-NEXT: sw s4, 68(a0)
+; RV64I-WITH-FP-NEXT: sw s3, 64(a0)
+; RV64I-WITH-FP-NEXT: sw s2, 60(a0)
+; RV64I-WITH-FP-NEXT: sw s1, 56(a0)
+; RV64I-WITH-FP-NEXT: sw t6, 52(a0)
+; RV64I-WITH-FP-NEXT: sw t5, 48(a0)
+; RV64I-WITH-FP-NEXT: sw t4, 44(a0)
+; RV64I-WITH-FP-NEXT: sw t3, 40(a0)
+; RV64I-WITH-FP-NEXT: sw t2, 36(a0)
+; RV64I-WITH-FP-NEXT: sw t1, 32(a0)
+; RV64I-WITH-FP-NEXT: sw t0, 28(a0)
+; RV64I-WITH-FP-NEXT: sw a7, 24(a0)
+; RV64I-WITH-FP-NEXT: ld a1, -152(s0) # 8-byte Folded Reload
+; RV64I-WITH-FP-NEXT: sw a1, 20(a0)
+; RV64I-WITH-FP-NEXT: ld a1, -144(s0) # 8-byte Folded Reload
+; RV64I-WITH-FP-NEXT: sw a1, 16(a0)
+; RV64I-WITH-FP-NEXT: ld a1, -136(s0) # 8-byte Folded Reload
+; RV64I-WITH-FP-NEXT: sw a1, 12(a0)
+; RV64I-WITH-FP-NEXT: ld a1, -128(s0) # 8-byte Folded Reload
+; RV64I-WITH-FP-NEXT: sw a1, 8(a0)
+; RV64I-WITH-FP-NEXT: ld a1, -120(s0) # 8-byte Folded Reload
+; RV64I-WITH-FP-NEXT: sw a1, 4(a0)
+; RV64I-WITH-FP-NEXT: ld a1, -112(s0) # 8-byte Folded Reload
+; RV64I-WITH-FP-NEXT: sw a1, 0(a0)
; RV64I-WITH-FP-NEXT: .cfi_def_cfa sp, 160
; RV64I-WITH-FP-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
@@ -1053,84 +1037,82 @@ define void @callee() {
; RV64IZCMP-NEXT: .cfi_offset s9, -24
; RV64IZCMP-NEXT: .cfi_offset s10, -16
; RV64IZCMP-NEXT: .cfi_offset s11, -8
-; RV64IZCMP-NEXT: lui t0, %hi(var)
-; RV64IZCMP-NEXT: lw a0, %lo(var)(t0)
-; RV64IZCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var+4)(t0)
-; RV64IZCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var+8)(t0)
-; RV64IZCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var+12)(t0)
-; RV64IZCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: addi a5, t0, %lo(var)
-; RV64IZCMP-NEXT: lw a0, 16(a5)
-; RV64IZCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 20(a5)
-; RV64IZCMP-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw t4, 24(a5)
-; RV64IZCMP-NEXT: lw t5, 28(a5)
-; RV64IZCMP-NEXT: lw t6, 32(a5)
-; RV64IZCMP-NEXT: lw s2, 36(a5)
-; RV64IZCMP-NEXT: lw s3, 40(a5)
-; RV64IZCMP-NEXT: lw s4, 44(a5)
-; RV64IZCMP-NEXT: lw s5, 48(a5)
-; RV64IZCMP-NEXT: lw s6, 52(a5)
-; RV64IZCMP-NEXT: lw s7, 56(a5)
-; RV64IZCMP-NEXT: lw s8, 60(a5)
-; RV64IZCMP-NEXT: lw s9, 64(a5)
-; RV64IZCMP-NEXT: lw s10, 68(a5)
-; RV64IZCMP-NEXT: lw s11, 72(a5)
-; RV64IZCMP-NEXT: lw ra, 76(a5)
-; RV64IZCMP-NEXT: lw s1, 80(a5)
-; RV64IZCMP-NEXT: lw t3, 84(a5)
-; RV64IZCMP-NEXT: lw t2, 88(a5)
-; RV64IZCMP-NEXT: lw t1, 92(a5)
-; RV64IZCMP-NEXT: lw a7, 112(a5)
-; RV64IZCMP-NEXT: lw s0, 116(a5)
-; RV64IZCMP-NEXT: lw a3, 120(a5)
-; RV64IZCMP-NEXT: lw a0, 124(a5)
-; RV64IZCMP-NEXT: lw a6, 96(a5)
-; RV64IZCMP-NEXT: lw a4, 100(a5)
-; RV64IZCMP-NEXT: lw a2, 104(a5)
-; RV64IZCMP-NEXT: lw a1, 108(a5)
-; RV64IZCMP-NEXT: sw a0, 124(a5)
-; RV64IZCMP-NEXT: sw a3, 120(a5)
-; RV64IZCMP-NEXT: sw s0, 116(a5)
-; RV64IZCMP-NEXT: sw a7, 112(a5)
-; RV64IZCMP-NEXT: sw a1, 108(a5)
-; RV64IZCMP-NEXT: sw a2, 104(a5)
-; RV64IZCMP-NEXT: sw a4, 100(a5)
-; RV64IZCMP-NEXT: sw a6, 96(a5)
-; RV64IZCMP-NEXT: sw t1, 92(a5)
-; RV64IZCMP-NEXT: sw t2, 88(a5)
-; RV64IZCMP-NEXT: sw t3, 84(a5)
-; RV64IZCMP-NEXT: sw s1, 80(a5)
-; RV64IZCMP-NEXT: sw ra, 76(a5)
-; RV64IZCMP-NEXT: sw s11, 72(a5)
-; RV64IZCMP-NEXT: sw s10, 68(a5)
-; RV64IZCMP-NEXT: sw s9, 64(a5)
-; RV64IZCMP-NEXT: sw s8, 60(a5)
-; RV64IZCMP-NEXT: sw s7, 56(a5)
-; RV64IZCMP-NEXT: sw s6, 52(a5)
-; RV64IZCMP-NEXT: sw s5, 48(a5)
-; RV64IZCMP-NEXT: sw s4, 44(a5)
-; RV64IZCMP-NEXT: sw s3, 40(a5)
-; RV64IZCMP-NEXT: sw s2, 36(a5)
-; RV64IZCMP-NEXT: sw t6, 32(a5)
-; RV64IZCMP-NEXT: sw t5, 28(a5)
-; RV64IZCMP-NEXT: sw t4, 24(a5)
-; RV64IZCMP-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 20(a5)
-; RV64IZCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 16(a5)
-; RV64IZCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var+12)(t0)
-; RV64IZCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var+8)(t0)
-; RV64IZCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var+4)(t0)
-; RV64IZCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var)(t0)
+; RV64IZCMP-NEXT: lui a0, %hi(var)
+; RV64IZCMP-NEXT: addi a0, a0, %lo(var)
+; RV64IZCMP-NEXT: lw a1, 0(a0)
+; RV64IZCMP-NEXT: sd a1, 40(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 4(a0)
+; RV64IZCMP-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 8(a0)
+; RV64IZCMP-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 12(a0)
+; RV64IZCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 16(a0)
+; RV64IZCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw t3, 20(a0)
+; RV64IZCMP-NEXT: lw t4, 24(a0)
+; RV64IZCMP-NEXT: lw t5, 28(a0)
+; RV64IZCMP-NEXT: lw t6, 32(a0)
+; RV64IZCMP-NEXT: lw s2, 36(a0)
+; RV64IZCMP-NEXT: lw s3, 40(a0)
+; RV64IZCMP-NEXT: lw s4, 44(a0)
+; RV64IZCMP-NEXT: lw s5, 48(a0)
+; RV64IZCMP-NEXT: lw s6, 52(a0)
+; RV64IZCMP-NEXT: lw s7, 56(a0)
+; RV64IZCMP-NEXT: lw s8, 60(a0)
+; RV64IZCMP-NEXT: lw s9, 64(a0)
+; RV64IZCMP-NEXT: lw s10, 68(a0)
+; RV64IZCMP-NEXT: lw s11, 72(a0)
+; RV64IZCMP-NEXT: lw ra, 76(a0)
+; RV64IZCMP-NEXT: lw t2, 80(a0)
+; RV64IZCMP-NEXT: lw s0, 84(a0)
+; RV64IZCMP-NEXT: lw s1, 88(a0)
+; RV64IZCMP-NEXT: lw t1, 92(a0)
+; RV64IZCMP-NEXT: lw t0, 112(a0)
+; RV64IZCMP-NEXT: lw a5, 116(a0)
+; RV64IZCMP-NEXT: lw a3, 120(a0)
+; RV64IZCMP-NEXT: lw a1, 124(a0)
+; RV64IZCMP-NEXT: lw a7, 96(a0)
+; RV64IZCMP-NEXT: lw a6, 100(a0)
+; RV64IZCMP-NEXT: lw a4, 104(a0)
+; RV64IZCMP-NEXT: lw a2, 108(a0)
+; RV64IZCMP-NEXT: sw a1, 124(a0)
+; RV64IZCMP-NEXT: sw a3, 120(a0)
+; RV64IZCMP-NEXT: sw a5, 116(a0)
+; RV64IZCMP-NEXT: sw t0, 112(a0)
+; RV64IZCMP-NEXT: sw a2, 108(a0)
+; RV64IZCMP-NEXT: sw a4, 104(a0)
+; RV64IZCMP-NEXT: sw a6, 100(a0)
+; RV64IZCMP-NEXT: sw a7, 96(a0)
+; RV64IZCMP-NEXT: sw t1, 92(a0)
+; RV64IZCMP-NEXT: sw s1, 88(a0)
+; RV64IZCMP-NEXT: sw s0, 84(a0)
+; RV64IZCMP-NEXT: sw t2, 80(a0)
+; RV64IZCMP-NEXT: sw ra, 76(a0)
+; RV64IZCMP-NEXT: sw s11, 72(a0)
+; RV64IZCMP-NEXT: sw s10, 68(a0)
+; RV64IZCMP-NEXT: sw s9, 64(a0)
+; RV64IZCMP-NEXT: sw s8, 60(a0)
+; RV64IZCMP-NEXT: sw s7, 56(a0)
+; RV64IZCMP-NEXT: sw s6, 52(a0)
+; RV64IZCMP-NEXT: sw s5, 48(a0)
+; RV64IZCMP-NEXT: sw s4, 44(a0)
+; RV64IZCMP-NEXT: sw s3, 40(a0)
+; RV64IZCMP-NEXT: sw s2, 36(a0)
+; RV64IZCMP-NEXT: sw t6, 32(a0)
+; RV64IZCMP-NEXT: sw t5, 28(a0)
+; RV64IZCMP-NEXT: sw t4, 24(a0)
+; RV64IZCMP-NEXT: sw t3, 20(a0)
+; RV64IZCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 16(a0)
+; RV64IZCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 12(a0)
+; RV64IZCMP-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 8(a0)
+; RV64IZCMP-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 4(a0)
+; RV64IZCMP-NEXT: ld a1, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 0(a0)
; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 160
;
; RV64IZCMP-WITH-FP-LABEL: callee:
@@ -1165,86 +1147,84 @@ define void @callee() {
; RV64IZCMP-WITH-FP-NEXT: .cfi_offset s11, -104
; RV64IZCMP-WITH-FP-NEXT: addi s0, sp, 160
; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
-; RV64IZCMP-WITH-FP-NEXT: lui t1, %hi(var)
-; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var)(t1)
-; RV64IZCMP-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(t1)
-; RV64IZCMP-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(t1)
-; RV64IZCMP-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(t1)
-; RV64IZCMP-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: addi a5, t1, %lo(var)
-; RV64IZCMP-WITH-FP-NEXT: lw a0, 16(a5)
-; RV64IZCMP-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw a0, 20(a5)
-; RV64IZCMP-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw a0, 24(a5)
-; RV64IZCMP-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw t5, 28(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw t6, 32(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s2, 36(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s3, 40(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s4, 44(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s5, 48(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s6, 52(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s7, 56(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s8, 60(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s9, 64(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s10, 68(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s11, 72(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw ra, 76(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw t4, 80(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw t3, 84(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw t2, 88(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw s1, 92(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw t0, 112(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw a4, 116(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw a3, 120(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw a0, 124(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw a7, 96(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw a6, 100(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw a2, 104(a5)
-; RV64IZCMP-WITH-FP-NEXT: lw a1, 108(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw a0, 124(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw a3, 120(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw a4, 116(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw t0, 112(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw a1, 108(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw a2, 104(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw a6, 100(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw a7, 96(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s1, 92(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw t2, 88(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw t3, 84(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw t4, 80(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw ra, 76(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s11, 72(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s10, 68(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s9, 64(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s8, 60(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s7, 56(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s6, 52(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s5, 48(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s4, 44(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s3, 40(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw s2, 36(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw t6, 32(a5)
-; RV64IZCMP-WITH-FP-NEXT: sw t5, 28(a5)
-; RV64IZCMP-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, 24(a5)
-; RV64IZCMP-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, 20(a5)
-; RV64IZCMP-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, 16(a5)
-; RV64IZCMP-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(t1)
-; RV64IZCMP-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(t1)
-; RV64IZCMP-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(t1)
-; RV64IZCMP-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var)(t1)
+; RV64IZCMP-WITH-FP-NEXT: lui a0, %hi(var)
+; RV64IZCMP-WITH-FP-NEXT: addi a0, a0, %lo(var)
+; RV64IZCMP-WITH-FP-NEXT: lw a1, 0(a0)
+; RV64IZCMP-WITH-FP-NEXT: sd a1, -112(s0) # 8-byte Folded Spill
+; RV64IZCMP-WITH-FP-NEXT: lw a1, 4(a0)
+; RV64IZCMP-WITH-FP-NEXT: sd a1, -120(s0) # 8-byte Folded Spill
+; RV64IZCMP-WITH-FP-NEXT: lw a1, 8(a0)
+; RV64IZCMP-WITH-FP-NEXT: sd a1, -128(s0) # 8-byte Folded Spill
+; RV64IZCMP-WITH-FP-NEXT: lw a1, 12(a0)
+; RV64IZCMP-WITH-FP-NEXT: sd a1, -136(s0) # 8-byte Folded Spill
+; RV64IZCMP-WITH-FP-NEXT: lw a1, 16(a0)
+; RV64IZCMP-WITH-FP-NEXT: sd a1, -144(s0) # 8-byte Folded Spill
+; RV64IZCMP-WITH-FP-NEXT: lw a1, 20(a0)
+; RV64IZCMP-WITH-FP-NEXT: sd a1, -152(s0) # 8-byte Folded Spill
+; RV64IZCMP-WITH-FP-NEXT: lw t4, 24(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t5, 28(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t6, 32(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s2, 36(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s3, 40(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s4, 44(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s5, 48(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s6, 52(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s7, 56(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s8, 60(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s9, 64(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s10, 68(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s11, 72(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw ra, 76(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s1, 80(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t3, 84(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t2, 88(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t1, 92(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t0, 112(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a6, 116(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a4, 120(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a1, 124(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a7, 96(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a5, 100(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a3, 104(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a2, 108(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a1, 124(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a4, 120(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a6, 116(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t0, 112(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a2, 108(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a3, 104(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a5, 100(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a7, 96(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t1, 92(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t2, 88(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t3, 84(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s1, 80(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw ra, 76(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s11, 72(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s10, 68(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s9, 64(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s8, 60(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s7, 56(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s6, 52(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s5, 48(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s4, 44(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s3, 40(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s2, 36(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t6, 32(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t5, 28(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t4, 24(a0)
+; RV64IZCMP-WITH-FP-NEXT: ld a1, -152(s0) # 8-byte Folded Reload
+; RV64IZCMP-WITH-FP-NEXT: sw a1, 20(a0)
+; RV64IZCMP-WITH-FP-NEXT: ld a1, -144(s0) # 8-byte Folded Reload
+; RV64IZCMP-WITH-FP-NEXT: sw a1, 16(a0)
+; RV64IZCMP-WITH-FP-NEXT: ld a1, -136(s0) # 8-byte Folded Reload
+; RV64IZCMP-WITH-FP-NEXT: sw a1, 12(a0)
+; RV64IZCMP-WITH-FP-NEXT: ld a1, -128(s0) # 8-byte Folded Reload
+; RV64IZCMP-WITH-FP-NEXT: sw a1, 8(a0)
+; RV64IZCMP-WITH-FP-NEXT: ld a1, -120(s0) # 8-byte Folded Reload
+; RV64IZCMP-WITH-FP-NEXT: sw a1, 4(a0)
+; RV64IZCMP-WITH-FP-NEXT: ld a1, -112(s0) # 8-byte Folded Reload
+; RV64IZCMP-WITH-FP-NEXT: sw a1, 0(a0)
; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa sp, 160
; RV64IZCMP-WITH-FP-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
@@ -1315,116 +1295,114 @@ define void @caller() {
; RV32I-NEXT: .cfi_offset s10, -48
; RV32I-NEXT: .cfi_offset s11, -52
; RV32I-NEXT: lui s0, %hi(var)
-; RV32I-NEXT: lw a0, %lo(var)(s0)
+; RV32I-NEXT: addi s0, s0, %lo(var)
+; RV32I-NEXT: lw a0, 0(s0)
; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var+4)(s0)
+; RV32I-NEXT: lw a0, 4(s0)
; RV32I-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var+8)(s0)
+; RV32I-NEXT: lw a0, 8(s0)
; RV32I-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var+12)(s0)
+; RV32I-NEXT: lw a0, 12(s0)
; RV32I-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi s5, s0, %lo(var)
-; RV32I-NEXT: lw a0, 16(s5)
+; RV32I-NEXT: lw a0, 16(s0)
; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 20(s5)
+; RV32I-NEXT: lw a0, 20(s0)
; RV32I-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 24(s5)
+; RV32I-NEXT: lw a0, 24(s0)
; RV32I-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 28(s5)
+; RV32I-NEXT: lw a0, 28(s0)
; RV32I-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 32(s5)
+; RV32I-NEXT: lw a0, 32(s0)
; RV32I-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 36(s5)
+; RV32I-NEXT: lw a0, 36(s0)
; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 40(s5)
+; RV32I-NEXT: lw a0, 40(s0)
; RV32I-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 44(s5)
+; RV32I-NEXT: lw a0, 44(s0)
; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 48(s5)
+; RV32I-NEXT: lw a0, 48(s0)
; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 52(s5)
+; RV32I-NEXT: lw a0, 52(s0)
; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 56(s5)
+; RV32I-NEXT: lw a0, 56(s0)
; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 60(s5)
+; RV32I-NEXT: lw a0, 60(s0)
; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 64(s5)
+; RV32I-NEXT: lw a0, 64(s0)
; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 68(s5)
+; RV32I-NEXT: lw a0, 68(s0)
; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 72(s5)
+; RV32I-NEXT: lw a0, 72(s0)
; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 76(s5)
+; RV32I-NEXT: lw a0, 76(s0)
; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 80(s5)
+; RV32I-NEXT: lw a0, 80(s0)
; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 84(s5)
-; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw s3, 88(s5)
-; RV32I-NEXT: lw s4, 92(s5)
-; RV32I-NEXT: lw s6, 96(s5)
-; RV32I-NEXT: lw s7, 100(s5)
-; RV32I-NEXT: lw s8, 104(s5)
-; RV32I-NEXT: lw s9, 108(s5)
-; RV32I-NEXT: lw s10, 112(s5)
-; RV32I-NEXT: lw s11, 116(s5)
-; RV32I-NEXT: lw s1, 120(s5)
-; RV32I-NEXT: lw s2, 124(s5)
+; RV32I-NEXT: lw s11, 84(s0)
+; RV32I-NEXT: lw s1, 88(s0)
+; RV32I-NEXT: lw s2, 92(s0)
+; RV32I-NEXT: lw s3, 96(s0)
+; RV32I-NEXT: lw s4, 100(s0)
+; RV32I-NEXT: lw s5, 104(s0)
+; RV32I-NEXT: lw s6, 108(s0)
+; RV32I-NEXT: lw s7, 112(s0)
+; RV32I-NEXT: lw s8, 116(s0)
+; RV32I-NEXT: lw s9, 120(s0)
+; RV32I-NEXT: lw s10, 124(s0)
; RV32I-NEXT: call callee
-; RV32I-NEXT: sw s2, 124(s5)
-; RV32I-NEXT: sw s1, 120(s5)
-; RV32I-NEXT: sw s11, 116(s5)
-; RV32I-NEXT: sw s10, 112(s5)
-; RV32I-NEXT: sw s9, 108(s5)
-; RV32I-NEXT: sw s8, 104(s5)
-; RV32I-NEXT: sw s7, 100(s5)
-; RV32I-NEXT: sw s6, 96(s5)
-; RV32I-NEXT: sw s4, 92(s5)
-; RV32I-NEXT: sw s3, 88(s5)
-; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 84(s5)
+; RV32I-NEXT: sw s10, 124(s0)
+; RV32I-NEXT: sw s9, 120(s0)
+; RV32I-NEXT: sw s8, 116(s0)
+; RV32I-NEXT: sw s7, 112(s0)
+; RV32I-NEXT: sw s6, 108(s0)
+; RV32I-NEXT: sw s5, 104(s0)
+; RV32I-NEXT: sw s4, 100(s0)
+; RV32I-NEXT: sw s3, 96(s0)
+; RV32I-NEXT: sw s2, 92(s0)
+; RV32I-NEXT: sw s1, 88(s0)
+; RV32I-NEXT: sw s11, 84(s0)
; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 80(s5)
+; RV32I-NEXT: sw a0, 80(s0)
; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 76(s5)
+; RV32I-NEXT: sw a0, 76(s0)
; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 72(s5)
+; RV32I-NEXT: sw a0, 72(s0)
; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 68(s5)
+; RV32I-NEXT: sw a0, 68(s0)
; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 64(s5)
+; RV32I-NEXT: sw a0, 64(s0)
; RV32I-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 60(s5)
+; RV32I-NEXT: sw a0, 60(s0)
; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 56(s5)
+; RV32I-NEXT: sw a0, 56(s0)
; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 52(s5)
+; RV32I-NEXT: sw a0, 52(s0)
; RV32I-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 48(s5)
+; RV32I-NEXT: sw a0, 48(s0)
; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 44(s5)
+; RV32I-NEXT: sw a0, 44(s0)
; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 40(s5)
+; RV32I-NEXT: sw a0, 40(s0)
; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 36(s5)
+; RV32I-NEXT: sw a0, 36(s0)
; RV32I-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 32(s5)
+; RV32I-NEXT: sw a0, 32(s0)
; RV32I-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 28(s5)
+; RV32I-NEXT: sw a0, 28(s0)
; RV32I-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 24(s5)
+; RV32I-NEXT: sw a0, 24(s0)
; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 20(s5)
+; RV32I-NEXT: sw a0, 20(s0)
; RV32I-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 16(s5)
+; RV32I-NEXT: sw a0, 16(s0)
; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var+12)(s0)
+; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var+8)(s0)
+; RV32I-NEXT: sw a0, 8(s0)
; RV32I-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var+4)(s0)
+; RV32I-NEXT: sw a0, 4(s0)
; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var)(s0)
+; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
@@ -1465,136 +1443,135 @@ define void @caller() {
; RV32I-ILP32E-NEXT: .cfi_offset ra, -4
; RV32I-ILP32E-NEXT: .cfi_offset s0, -8
; RV32I-ILP32E-NEXT: .cfi_offset s1, -12
-; RV32I-ILP32E-NEXT: lui a0, %hi(var)
-; RV32I-ILP32E-NEXT: lw a1, %lo(var)(a0)
-; RV32I-ILP32E-NEXT: sw a1, 120(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a1, %lo(var+4)(a0)
-; RV32I-ILP32E-NEXT: sw a1, 116(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a1, %lo(var+8)(a0)
-; RV32I-ILP32E-NEXT: sw a1, 112(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a1, %lo(var+12)(a0)
-; RV32I-ILP32E-NEXT: sw a1, 108(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: addi s1, a0, %lo(var)
-; RV32I-ILP32E-NEXT: lw a0, 16(s1)
+; RV32I-ILP32E-NEXT: lui s0, %hi(var)
+; RV32I-ILP32E-NEXT: addi s0, s0, %lo(var)
+; RV32I-ILP32E-NEXT: lw a0, 0(s0)
+; RV32I-ILP32E-NEXT: sw a0, 120(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: lw a0, 4(s0)
+; RV32I-ILP32E-NEXT: sw a0, 116(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: lw a0, 8(s0)
+; RV32I-ILP32E-NEXT: sw a0, 112(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: lw a0, 12(s0)
+; RV32I-ILP32E-NEXT: sw a0, 108(sp) # 4-byte Folded Spill
+; RV32I-ILP32E-NEXT: lw a0, 16(s0)
; RV32I-ILP32E-NEXT: sw a0, 104(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 20(s1)
+; RV32I-ILP32E-NEXT: lw a0, 20(s0)
; RV32I-ILP32E-NEXT: sw a0, 100(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 24(s1)
+; RV32I-ILP32E-NEXT: lw a0, 24(s0)
; RV32I-ILP32E-NEXT: sw a0, 96(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 28(s1)
+; RV32I-ILP32E-NEXT: lw a0, 28(s0)
; RV32I-ILP32E-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 32(s1)
+; RV32I-ILP32E-NEXT: lw a0, 32(s0)
; RV32I-ILP32E-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 36(s1)
+; RV32I-ILP32E-NEXT: lw a0, 36(s0)
; RV32I-ILP32E-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 40(s1)
+; RV32I-ILP32E-NEXT: lw a0, 40(s0)
; RV32I-ILP32E-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 44(s1)
+; RV32I-ILP32E-NEXT: lw a0, 44(s0)
; RV32I-ILP32E-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 48(s1)
+; RV32I-ILP32E-NEXT: lw a0, 48(s0)
; RV32I-ILP32E-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 52(s1)
+; RV32I-ILP32E-NEXT: lw a0, 52(s0)
; RV32I-ILP32E-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 56(s1)
+; RV32I-ILP32E-NEXT: lw a0, 56(s0)
; RV32I-ILP32E-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 60(s1)
+; RV32I-ILP32E-NEXT: lw a0, 60(s0)
; RV32I-ILP32E-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 64(s1)
+; RV32I-ILP32E-NEXT: lw a0, 64(s0)
; RV32I-ILP32E-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 68(s1)
+; RV32I-ILP32E-NEXT: lw a0, 68(s0)
; RV32I-ILP32E-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 72(s1)
+; RV32I-ILP32E-NEXT: lw a0, 72(s0)
; RV32I-ILP32E-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 76(s1)
+; RV32I-ILP32E-NEXT: lw a0, 76(s0)
; RV32I-ILP32E-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 80(s1)
+; RV32I-ILP32E-NEXT: lw a0, 80(s0)
; RV32I-ILP32E-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 84(s1)
+; RV32I-ILP32E-NEXT: lw a0, 84(s0)
; RV32I-ILP32E-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 88(s1)
+; RV32I-ILP32E-NEXT: lw a0, 88(s0)
; RV32I-ILP32E-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 92(s1)
+; RV32I-ILP32E-NEXT: lw a0, 92(s0)
; RV32I-ILP32E-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 96(s1)
+; RV32I-ILP32E-NEXT: lw a0, 96(s0)
; RV32I-ILP32E-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 100(s1)
+; RV32I-ILP32E-NEXT: lw a0, 100(s0)
; RV32I-ILP32E-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 104(s1)
+; RV32I-ILP32E-NEXT: lw a0, 104(s0)
; RV32I-ILP32E-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 108(s1)
+; RV32I-ILP32E-NEXT: lw a0, 108(s0)
; RV32I-ILP32E-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 112(s1)
+; RV32I-ILP32E-NEXT: lw a0, 112(s0)
; RV32I-ILP32E-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 116(s1)
+; RV32I-ILP32E-NEXT: lw a0, 116(s0)
; RV32I-ILP32E-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw a0, 120(s1)
+; RV32I-ILP32E-NEXT: lw a0, 120(s0)
; RV32I-ILP32E-NEXT: sw a0, 0(sp) # 4-byte Folded Spill
-; RV32I-ILP32E-NEXT: lw s0, 124(s1)
+; RV32I-ILP32E-NEXT: lw s1, 124(s0)
; RV32I-ILP32E-NEXT: call callee
-; RV32I-ILP32E-NEXT: sw s0, 124(s1)
+; RV32I-ILP32E-NEXT: sw s1, 124(s0)
; RV32I-ILP32E-NEXT: lw a0, 0(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 120(s1)
+; RV32I-ILP32E-NEXT: sw a0, 120(s0)
; RV32I-ILP32E-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 116(s1)
+; RV32I-ILP32E-NEXT: sw a0, 116(s0)
; RV32I-ILP32E-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 112(s1)
+; RV32I-ILP32E-NEXT: sw a0, 112(s0)
; RV32I-ILP32E-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 108(s1)
+; RV32I-ILP32E-NEXT: sw a0, 108(s0)
; RV32I-ILP32E-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 104(s1)
+; RV32I-ILP32E-NEXT: sw a0, 104(s0)
; RV32I-ILP32E-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 100(s1)
+; RV32I-ILP32E-NEXT: sw a0, 100(s0)
; RV32I-ILP32E-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 96(s1)
+; RV32I-ILP32E-NEXT: sw a0, 96(s0)
; RV32I-ILP32E-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 92(s1)
+; RV32I-ILP32E-NEXT: sw a0, 92(s0)
; RV32I-ILP32E-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 88(s1)
+; RV32I-ILP32E-NEXT: sw a0, 88(s0)
; RV32I-ILP32E-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 84(s1)
+; RV32I-ILP32E-NEXT: sw a0, 84(s0)
; RV32I-ILP32E-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 80(s1)
+; RV32I-ILP32E-NEXT: sw a0, 80(s0)
; RV32I-ILP32E-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 76(s1)
+; RV32I-ILP32E-NEXT: sw a0, 76(s0)
; RV32I-ILP32E-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 72(s1)
+; RV32I-ILP32E-NEXT: sw a0, 72(s0)
; RV32I-ILP32E-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 68(s1)
+; RV32I-ILP32E-NEXT: sw a0, 68(s0)
; RV32I-ILP32E-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 64(s1)
+; RV32I-ILP32E-NEXT: sw a0, 64(s0)
; RV32I-ILP32E-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 60(s1)
+; RV32I-ILP32E-NEXT: sw a0, 60(s0)
; RV32I-ILP32E-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 56(s1)
+; RV32I-ILP32E-NEXT: sw a0, 56(s0)
; RV32I-ILP32E-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 52(s1)
+; RV32I-ILP32E-NEXT: sw a0, 52(s0)
; RV32I-ILP32E-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 48(s1)
+; RV32I-ILP32E-NEXT: sw a0, 48(s0)
; RV32I-ILP32E-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 44(s1)
+; RV32I-ILP32E-NEXT: sw a0, 44(s0)
; RV32I-ILP32E-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 40(s1)
+; RV32I-ILP32E-NEXT: sw a0, 40(s0)
; RV32I-ILP32E-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 36(s1)
+; RV32I-ILP32E-NEXT: sw a0, 36(s0)
; RV32I-ILP32E-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 32(s1)
+; RV32I-ILP32E-NEXT: sw a0, 32(s0)
; RV32I-ILP32E-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 28(s1)
+; RV32I-ILP32E-NEXT: sw a0, 28(s0)
; RV32I-ILP32E-NEXT: lw a0, 96(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 24(s1)
+; RV32I-ILP32E-NEXT: sw a0, 24(s0)
; RV32I-ILP32E-NEXT: lw a0, 100(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 20(s1)
+; RV32I-ILP32E-NEXT: sw a0, 20(s0)
; RV32I-ILP32E-NEXT: lw a0, 104(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, 16(s1)
-; RV32I-ILP32E-NEXT: lui a1, %hi(var)
+; RV32I-ILP32E-NEXT: sw a0, 16(s0)
; RV32I-ILP32E-NEXT: lw a0, 108(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, %lo(var+12)(a1)
+; RV32I-ILP32E-NEXT: sw a0, 12(s0)
; RV32I-ILP32E-NEXT: lw a0, 112(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, %lo(var+8)(a1)
+; RV32I-ILP32E-NEXT: sw a0, 8(s0)
; RV32I-ILP32E-NEXT: lw a0, 116(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, %lo(var+4)(a1)
+; RV32I-ILP32E-NEXT: sw a0, 4(s0)
; RV32I-ILP32E-NEXT: lw a0, 120(sp) # 4-byte Folded Reload
-; RV32I-ILP32E-NEXT: sw a0, %lo(var)(a1)
+; RV32I-ILP32E-NEXT: sw a0, 0(s0)
; RV32I-ILP32E-NEXT: lw ra, 132(sp) # 4-byte Folded Reload
; RV32I-ILP32E-NEXT: lw s0, 128(sp) # 4-byte Folded Reload
; RV32I-ILP32E-NEXT: lw s1, 124(sp) # 4-byte Folded Reload
@@ -1638,118 +1615,116 @@ define void @caller() {
; RV32I-WITH-FP-NEXT: addi s0, sp, 144
; RV32I-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV32I-WITH-FP-NEXT: lui s1, %hi(var)
-; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(s1)
+; RV32I-WITH-FP-NEXT: addi s1, s1, %lo(var)
+; RV32I-WITH-FP-NEXT: lw a0, 0(s1)
; RV32I-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(s1)
+; RV32I-WITH-FP-NEXT: lw a0, 4(s1)
; RV32I-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(s1)
+; RV32I-WITH-FP-NEXT: lw a0, 8(s1)
; RV32I-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(s1)
+; RV32I-WITH-FP-NEXT: lw a0, 12(s1)
; RV32I-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: addi s6, s1, %lo(var)
-; RV32I-WITH-FP-NEXT: lw a0, 16(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 16(s1)
; RV32I-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 20(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 20(s1)
; RV32I-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 24(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 24(s1)
; RV32I-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 28(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 28(s1)
; RV32I-WITH-FP-NEXT: sw a0, -84(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 32(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 32(s1)
; RV32I-WITH-FP-NEXT: sw a0, -88(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 36(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 36(s1)
; RV32I-WITH-FP-NEXT: sw a0, -92(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 40(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 40(s1)
; RV32I-WITH-FP-NEXT: sw a0, -96(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 44(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 44(s1)
; RV32I-WITH-FP-NEXT: sw a0, -100(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 48(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 48(s1)
; RV32I-WITH-FP-NEXT: sw a0, -104(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 52(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 52(s1)
; RV32I-WITH-FP-NEXT: sw a0, -108(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 56(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 56(s1)
; RV32I-WITH-FP-NEXT: sw a0, -112(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 60(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 60(s1)
; RV32I-WITH-FP-NEXT: sw a0, -116(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 64(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 64(s1)
; RV32I-WITH-FP-NEXT: sw a0, -120(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 68(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 68(s1)
; RV32I-WITH-FP-NEXT: sw a0, -124(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 72(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 72(s1)
; RV32I-WITH-FP-NEXT: sw a0, -128(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 76(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 76(s1)
; RV32I-WITH-FP-NEXT: sw a0, -132(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 80(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 80(s1)
; RV32I-WITH-FP-NEXT: sw a0, -136(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 84(s6)
+; RV32I-WITH-FP-NEXT: lw a0, 84(s1)
; RV32I-WITH-FP-NEXT: sw a0, -140(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw a0, 88(s6)
-; RV32I-WITH-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill
-; RV32I-WITH-FP-NEXT: lw s8, 92(s6)
-; RV32I-WITH-FP-NEXT: lw s9, 96(s6)
-; RV32I-WITH-FP-NEXT: lw s10, 100(s6)
-; RV32I-WITH-FP-NEXT: lw s11, 104(s6)
-; RV32I-WITH-FP-NEXT: lw s2, 108(s6)
-; RV32I-WITH-FP-NEXT: lw s3, 112(s6)
-; RV32I-WITH-FP-NEXT: lw s4, 116(s6)
-; RV32I-WITH-FP-NEXT: lw s5, 120(s6)
-; RV32I-WITH-FP-NEXT: lw s7, 124(s6)
+; RV32I-WITH-FP-NEXT: lw s4, 88(s1)
+; RV32I-WITH-FP-NEXT: lw s5, 92(s1)
+; RV32I-WITH-FP-NEXT: lw s6, 96(s1)
+; RV32I-WITH-FP-NEXT: lw s7, 100(s1)
+; RV32I-WITH-FP-NEXT: lw s8, 104(s1)
+; RV32I-WITH-FP-NEXT: lw s9, 108(s1)
+; RV32I-WITH-FP-NEXT: lw s10, 112(s1)
+; RV32I-WITH-FP-NEXT: lw s11, 116(s1)
+; RV32I-WITH-FP-NEXT: lw s2, 120(s1)
+; RV32I-WITH-FP-NEXT: lw s3, 124(s1)
; RV32I-WITH-FP-NEXT: call callee
-; RV32I-WITH-FP-NEXT: sw s7, 124(s6)
-; RV32I-WITH-FP-NEXT: sw s5, 120(s6)
-; RV32I-WITH-FP-NEXT: sw s4, 116(s6)
-; RV32I-WITH-FP-NEXT: sw s3, 112(s6)
-; RV32I-WITH-FP-NEXT: sw s2, 108(s6)
-; RV32I-WITH-FP-NEXT: sw s11, 104(s6)
-; RV32I-WITH-FP-NEXT: sw s10, 100(s6)
-; RV32I-WITH-FP-NEXT: sw s9, 96(s6)
-; RV32I-WITH-FP-NEXT: sw s8, 92(s6)
-; RV32I-WITH-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 88(s6)
+; RV32I-WITH-FP-NEXT: sw s3, 124(s1)
+; RV32I-WITH-FP-NEXT: sw s2, 120(s1)
+; RV32I-WITH-FP-NEXT: sw s11, 116(s1)
+; RV32I-WITH-FP-NEXT: sw s10, 112(s1)
+; RV32I-WITH-FP-NEXT: sw s9, 108(s1)
+; RV32I-WITH-FP-NEXT: sw s8, 104(s1)
+; RV32I-WITH-FP-NEXT: sw s7, 100(s1)
+; RV32I-WITH-FP-NEXT: sw s6, 96(s1)
+; RV32I-WITH-FP-NEXT: sw s5, 92(s1)
+; RV32I-WITH-FP-NEXT: sw s4, 88(s1)
; RV32I-WITH-FP-NEXT: lw a0, -140(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 84(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 84(s1)
; RV32I-WITH-FP-NEXT: lw a0, -136(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 80(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 80(s1)
; RV32I-WITH-FP-NEXT: lw a0, -132(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 76(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 76(s1)
; RV32I-WITH-FP-NEXT: lw a0, -128(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 72(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 72(s1)
; RV32I-WITH-FP-NEXT: lw a0, -124(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 68(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 68(s1)
; RV32I-WITH-FP-NEXT: lw a0, -120(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 64(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 64(s1)
; RV32I-WITH-FP-NEXT: lw a0, -116(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 60(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 60(s1)
; RV32I-WITH-FP-NEXT: lw a0, -112(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 56(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 56(s1)
; RV32I-WITH-FP-NEXT: lw a0, -108(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 52(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 52(s1)
; RV32I-WITH-FP-NEXT: lw a0, -104(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 48(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 48(s1)
; RV32I-WITH-FP-NEXT: lw a0, -100(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 44(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 44(s1)
; RV32I-WITH-FP-NEXT: lw a0, -96(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 40(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 40(s1)
; RV32I-WITH-FP-NEXT: lw a0, -92(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 36(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 36(s1)
; RV32I-WITH-FP-NEXT: lw a0, -88(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 32(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 32(s1)
; RV32I-WITH-FP-NEXT: lw a0, -84(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 28(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 28(s1)
; RV32I-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 24(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 24(s1)
; RV32I-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 20(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 20(s1)
; RV32I-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, 16(s6)
+; RV32I-WITH-FP-NEXT: sw a0, 16(s1)
; RV32I-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(s1)
+; RV32I-WITH-FP-NEXT: sw a0, 12(s1)
; RV32I-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(s1)
+; RV32I-WITH-FP-NEXT: sw a0, 8(s1)
; RV32I-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(s1)
+; RV32I-WITH-FP-NEXT: sw a0, 4(s1)
; RV32I-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload
-; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(s1)
+; RV32I-WITH-FP-NEXT: sw a0, 0(s1)
; RV32I-WITH-FP-NEXT: .cfi_def_cfa sp, 144
; RV32I-WITH-FP-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
@@ -1801,116 +1776,114 @@ define void @caller() {
; RV32IZCMP-NEXT: addi sp, sp, -48
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 160
; RV32IZCMP-NEXT: lui s0, %hi(var)
-; RV32IZCMP-NEXT: lw a0, %lo(var)(s0)
+; RV32IZCMP-NEXT: addi s0, s0, %lo(var)
+; RV32IZCMP-NEXT: lw a0, 0(s0)
; RV32IZCMP-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var+4)(s0)
+; RV32IZCMP-NEXT: lw a0, 4(s0)
; RV32IZCMP-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var+8)(s0)
+; RV32IZCMP-NEXT: lw a0, 8(s0)
; RV32IZCMP-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var+12)(s0)
+; RV32IZCMP-NEXT: lw a0, 12(s0)
; RV32IZCMP-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: addi s1, s0, %lo(var)
-; RV32IZCMP-NEXT: lw a0, 16(s1)
+; RV32IZCMP-NEXT: lw a0, 16(s0)
; RV32IZCMP-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 20(s1)
+; RV32IZCMP-NEXT: lw a0, 20(s0)
; RV32IZCMP-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 24(s1)
+; RV32IZCMP-NEXT: lw a0, 24(s0)
; RV32IZCMP-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 28(s1)
+; RV32IZCMP-NEXT: lw a0, 28(s0)
; RV32IZCMP-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 32(s1)
+; RV32IZCMP-NEXT: lw a0, 32(s0)
; RV32IZCMP-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 36(s1)
+; RV32IZCMP-NEXT: lw a0, 36(s0)
; RV32IZCMP-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 40(s1)
+; RV32IZCMP-NEXT: lw a0, 40(s0)
; RV32IZCMP-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 44(s1)
+; RV32IZCMP-NEXT: lw a0, 44(s0)
; RV32IZCMP-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 48(s1)
+; RV32IZCMP-NEXT: lw a0, 48(s0)
; RV32IZCMP-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 52(s1)
+; RV32IZCMP-NEXT: lw a0, 52(s0)
; RV32IZCMP-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 56(s1)
+; RV32IZCMP-NEXT: lw a0, 56(s0)
; RV32IZCMP-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 60(s1)
+; RV32IZCMP-NEXT: lw a0, 60(s0)
; RV32IZCMP-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 64(s1)
+; RV32IZCMP-NEXT: lw a0, 64(s0)
; RV32IZCMP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 68(s1)
+; RV32IZCMP-NEXT: lw a0, 68(s0)
; RV32IZCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 72(s1)
+; RV32IZCMP-NEXT: lw a0, 72(s0)
; RV32IZCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 76(s1)
+; RV32IZCMP-NEXT: lw a0, 76(s0)
; RV32IZCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 80(s1)
+; RV32IZCMP-NEXT: lw a0, 80(s0)
; RV32IZCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 84(s1)
-; RV32IZCMP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw s4, 88(s1)
-; RV32IZCMP-NEXT: lw s5, 92(s1)
-; RV32IZCMP-NEXT: lw s6, 96(s1)
-; RV32IZCMP-NEXT: lw s7, 100(s1)
-; RV32IZCMP-NEXT: lw s8, 104(s1)
-; RV32IZCMP-NEXT: lw s9, 108(s1)
-; RV32IZCMP-NEXT: lw s10, 112(s1)
-; RV32IZCMP-NEXT: lw s11, 116(s1)
-; RV32IZCMP-NEXT: lw s2, 120(s1)
-; RV32IZCMP-NEXT: lw s3, 124(s1)
+; RV32IZCMP-NEXT: lw s1, 84(s0)
+; RV32IZCMP-NEXT: lw s2, 88(s0)
+; RV32IZCMP-NEXT: lw s3, 92(s0)
+; RV32IZCMP-NEXT: lw s4, 96(s0)
+; RV32IZCMP-NEXT: lw s5, 100(s0)
+; RV32IZCMP-NEXT: lw s6, 104(s0)
+; RV32IZCMP-NEXT: lw s7, 108(s0)
+; RV32IZCMP-NEXT: lw s8, 112(s0)
+; RV32IZCMP-NEXT: lw s9, 116(s0)
+; RV32IZCMP-NEXT: lw s10, 120(s0)
+; RV32IZCMP-NEXT: lw s11, 124(s0)
; RV32IZCMP-NEXT: call callee
-; RV32IZCMP-NEXT: sw s3, 124(s1)
-; RV32IZCMP-NEXT: sw s2, 120(s1)
-; RV32IZCMP-NEXT: sw s11, 116(s1)
-; RV32IZCMP-NEXT: sw s10, 112(s1)
-; RV32IZCMP-NEXT: sw s9, 108(s1)
-; RV32IZCMP-NEXT: sw s8, 104(s1)
-; RV32IZCMP-NEXT: sw s7, 100(s1)
-; RV32IZCMP-NEXT: sw s6, 96(s1)
-; RV32IZCMP-NEXT: sw s5, 92(s1)
-; RV32IZCMP-NEXT: sw s4, 88(s1)
-; RV32IZCMP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 84(s1)
+; RV32IZCMP-NEXT: sw s11, 124(s0)
+; RV32IZCMP-NEXT: sw s10, 120(s0)
+; RV32IZCMP-NEXT: sw s9, 116(s0)
+; RV32IZCMP-NEXT: sw s8, 112(s0)
+; RV32IZCMP-NEXT: sw s7, 108(s0)
+; RV32IZCMP-NEXT: sw s6, 104(s0)
+; RV32IZCMP-NEXT: sw s5, 100(s0)
+; RV32IZCMP-NEXT: sw s4, 96(s0)
+; RV32IZCMP-NEXT: sw s3, 92(s0)
+; RV32IZCMP-NEXT: sw s2, 88(s0)
+; RV32IZCMP-NEXT: sw s1, 84(s0)
; RV32IZCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 80(s1)
+; RV32IZCMP-NEXT: sw a0, 80(s0)
; RV32IZCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 76(s1)
+; RV32IZCMP-NEXT: sw a0, 76(s0)
; RV32IZCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 72(s1)
+; RV32IZCMP-NEXT: sw a0, 72(s0)
; RV32IZCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 68(s1)
+; RV32IZCMP-NEXT: sw a0, 68(s0)
; RV32IZCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 64(s1)
+; RV32IZCMP-NEXT: sw a0, 64(s0)
; RV32IZCMP-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 60(s1)
+; RV32IZCMP-NEXT: sw a0, 60(s0)
; RV32IZCMP-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 56(s1)
+; RV32IZCMP-NEXT: sw a0, 56(s0)
; RV32IZCMP-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 52(s1)
+; RV32IZCMP-NEXT: sw a0, 52(s0)
; RV32IZCMP-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 48(s1)
+; RV32IZCMP-NEXT: sw a0, 48(s0)
; RV32IZCMP-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 44(s1)
+; RV32IZCMP-NEXT: sw a0, 44(s0)
; RV32IZCMP-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 40(s1)
+; RV32IZCMP-NEXT: sw a0, 40(s0)
; RV32IZCMP-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 36(s1)
+; RV32IZCMP-NEXT: sw a0, 36(s0)
; RV32IZCMP-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 32(s1)
+; RV32IZCMP-NEXT: sw a0, 32(s0)
; RV32IZCMP-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 28(s1)
+; RV32IZCMP-NEXT: sw a0, 28(s0)
; RV32IZCMP-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 24(s1)
+; RV32IZCMP-NEXT: sw a0, 24(s0)
; RV32IZCMP-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 20(s1)
+; RV32IZCMP-NEXT: sw a0, 20(s0)
; RV32IZCMP-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 16(s1)
+; RV32IZCMP-NEXT: sw a0, 16(s0)
; RV32IZCMP-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var+12)(s0)
+; RV32IZCMP-NEXT: sw a0, 12(s0)
; RV32IZCMP-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var+8)(s0)
+; RV32IZCMP-NEXT: sw a0, 8(s0)
; RV32IZCMP-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var+4)(s0)
+; RV32IZCMP-NEXT: sw a0, 4(s0)
; RV32IZCMP-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var)(s0)
+; RV32IZCMP-NEXT: sw a0, 0(s0)
; RV32IZCMP-NEXT: addi sp, sp, 48
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 112
; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 112
@@ -1947,16 +1920,16 @@ define void @caller() {
; RV32IZCMP-WITH-FP-NEXT: .cfi_offset s11, -52
; RV32IZCMP-WITH-FP-NEXT: addi s0, sp, 144
; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
-; RV32IZCMP-WITH-FP-NEXT: lui s6, %hi(var)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var)(s6)
+; RV32IZCMP-WITH-FP-NEXT: lui s1, %hi(var)
+; RV32IZCMP-WITH-FP-NEXT: addi s1, s1, %lo(var)
+; RV32IZCMP-WITH-FP-NEXT: lw a0, 0(s1)
; RV32IZCMP-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(s6)
+; RV32IZCMP-WITH-FP-NEXT: lw a0, 4(s1)
; RV32IZCMP-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(s6)
+; RV32IZCMP-WITH-FP-NEXT: lw a0, 8(s1)
; RV32IZCMP-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(s6)
+; RV32IZCMP-WITH-FP-NEXT: lw a0, 12(s1)
; RV32IZCMP-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: addi s1, s6, %lo(var)
; RV32IZCMP-WITH-FP-NEXT: lw a0, 16(s1)
; RV32IZCMP-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
; RV32IZCMP-WITH-FP-NEXT: lw a0, 20(s1)
@@ -1993,29 +1966,27 @@ define void @caller() {
; RV32IZCMP-WITH-FP-NEXT: sw a0, -136(s0) # 4-byte Folded Spill
; RV32IZCMP-WITH-FP-NEXT: lw a0, 84(s1)
; RV32IZCMP-WITH-FP-NEXT: sw a0, -140(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw a0, 88(s1)
-; RV32IZCMP-WITH-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw s8, 92(s1)
-; RV32IZCMP-WITH-FP-NEXT: lw s9, 96(s1)
-; RV32IZCMP-WITH-FP-NEXT: lw s10, 100(s1)
-; RV32IZCMP-WITH-FP-NEXT: lw s11, 104(s1)
-; RV32IZCMP-WITH-FP-NEXT: lw s2, 108(s1)
-; RV32IZCMP-WITH-FP-NEXT: lw s3, 112(s1)
-; RV32IZCMP-WITH-FP-NEXT: lw s4, 116(s1)
-; RV32IZCMP-WITH-FP-NEXT: lw s5, 120(s1)
-; RV32IZCMP-WITH-FP-NEXT: lw s7, 124(s1)
+; RV32IZCMP-WITH-FP-NEXT: lw s4, 88(s1)
+; RV32IZCMP-WITH-FP-NEXT: lw s5, 92(s1)
+; RV32IZCMP-WITH-FP-NEXT: lw s6, 96(s1)
+; RV32IZCMP-WITH-FP-NEXT: lw s7, 100(s1)
+; RV32IZCMP-WITH-FP-NEXT: lw s8, 104(s1)
+; RV32IZCMP-WITH-FP-NEXT: lw s9, 108(s1)
+; RV32IZCMP-WITH-FP-NEXT: lw s10, 112(s1)
+; RV32IZCMP-WITH-FP-NEXT: lw s11, 116(s1)
+; RV32IZCMP-WITH-FP-NEXT: lw s2, 120(s1)
+; RV32IZCMP-WITH-FP-NEXT: lw s3, 124(s1)
; RV32IZCMP-WITH-FP-NEXT: call callee
-; RV32IZCMP-WITH-FP-NEXT: sw s7, 124(s1)
-; RV32IZCMP-WITH-FP-NEXT: sw s5, 120(s1)
-; RV32IZCMP-WITH-FP-NEXT: sw s4, 116(s1)
-; RV32IZCMP-WITH-FP-NEXT: sw s3, 112(s1)
-; RV32IZCMP-WITH-FP-NEXT: sw s2, 108(s1)
-; RV32IZCMP-WITH-FP-NEXT: sw s11, 104(s1)
-; RV32IZCMP-WITH-FP-NEXT: sw s10, 100(s1)
-; RV32IZCMP-WITH-FP-NEXT: sw s9, 96(s1)
-; RV32IZCMP-WITH-FP-NEXT: sw s8, 92(s1)
-; RV32IZCMP-WITH-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, 88(s1)
+; RV32IZCMP-WITH-FP-NEXT: sw s3, 124(s1)
+; RV32IZCMP-WITH-FP-NEXT: sw s2, 120(s1)
+; RV32IZCMP-WITH-FP-NEXT: sw s11, 116(s1)
+; RV32IZCMP-WITH-FP-NEXT: sw s10, 112(s1)
+; RV32IZCMP-WITH-FP-NEXT: sw s9, 108(s1)
+; RV32IZCMP-WITH-FP-NEXT: sw s8, 104(s1)
+; RV32IZCMP-WITH-FP-NEXT: sw s7, 100(s1)
+; RV32IZCMP-WITH-FP-NEXT: sw s6, 96(s1)
+; RV32IZCMP-WITH-FP-NEXT: sw s5, 92(s1)
+; RV32IZCMP-WITH-FP-NEXT: sw s4, 88(s1)
; RV32IZCMP-WITH-FP-NEXT: lw a0, -140(s0) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: sw a0, 84(s1)
; RV32IZCMP-WITH-FP-NEXT: lw a0, -136(s0) # 4-byte Folded Reload
@@ -2053,13 +2024,13 @@ define void @caller() {
; RV32IZCMP-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: sw a0, 16(s1)
; RV32IZCMP-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(s6)
+; RV32IZCMP-WITH-FP-NEXT: sw a0, 12(s1)
; RV32IZCMP-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(s6)
+; RV32IZCMP-WITH-FP-NEXT: sw a0, 8(s1)
; RV32IZCMP-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(s6)
+; RV32IZCMP-WITH-FP-NEXT: sw a0, 4(s1)
; RV32IZCMP-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload
-; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var)(s6)
+; RV32IZCMP-WITH-FP-NEXT: sw a0, 0(s1)
; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa sp, 144
; RV32IZCMP-WITH-FP-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
@@ -2093,21 +2064,21 @@ define void @caller() {
;
; RV64I-LABEL: caller:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -288
-; RV64I-NEXT: .cfi_def_cfa_offset 288
-; RV64I-NEXT: sd ra, 280(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 272(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 264(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 256(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 248(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s4, 240(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s5, 232(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s6, 224(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s7, 216(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s8, 208(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s9, 200(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s10, 192(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s11, 184(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -272
+; RV64I-NEXT: .cfi_def_cfa_offset 272
+; RV64I-NEXT: sd ra, 264(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 256(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 248(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 240(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 232(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 224(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s5, 216(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s6, 208(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s7, 200(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s8, 192(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s9, 184(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s10, 176(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s11, 168(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
@@ -2122,129 +2093,127 @@ define void @caller() {
; RV64I-NEXT: .cfi_offset s10, -96
; RV64I-NEXT: .cfi_offset s11, -104
; RV64I-NEXT: lui s0, %hi(var)
-; RV64I-NEXT: lw a0, %lo(var)(s0)
-; RV64I-NEXT: sd a0, 176(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var+4)(s0)
-; RV64I-NEXT: sd a0, 168(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var+8)(s0)
+; RV64I-NEXT: addi s0, s0, %lo(var)
+; RV64I-NEXT: lw a0, 0(s0)
; RV64I-NEXT: sd a0, 160(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var+12)(s0)
+; RV64I-NEXT: lw a0, 4(s0)
; RV64I-NEXT: sd a0, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addi s5, s0, %lo(var)
-; RV64I-NEXT: lw a0, 16(s5)
+; RV64I-NEXT: lw a0, 8(s0)
; RV64I-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 20(s5)
+; RV64I-NEXT: lw a0, 12(s0)
; RV64I-NEXT: sd a0, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 24(s5)
+; RV64I-NEXT: lw a0, 16(s0)
; RV64I-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 28(s5)
+; RV64I-NEXT: lw a0, 20(s0)
; RV64I-NEXT: sd a0, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 32(s5)
+; RV64I-NEXT: lw a0, 24(s0)
; RV64I-NEXT: sd a0, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 36(s5)
+; RV64I-NEXT: lw a0, 28(s0)
; RV64I-NEXT: sd a0, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 40(s5)
+; RV64I-NEXT: lw a0, 32(s0)
; RV64I-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 44(s5)
+; RV64I-NEXT: lw a0, 36(s0)
; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 48(s5)
+; RV64I-NEXT: lw a0, 40(s0)
; RV64I-NEXT: sd a0, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 52(s5)
+; RV64I-NEXT: lw a0, 44(s0)
; RV64I-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 56(s5)
+; RV64I-NEXT: lw a0, 48(s0)
; RV64I-NEXT: sd a0, 64(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 60(s5)
+; RV64I-NEXT: lw a0, 52(s0)
; RV64I-NEXT: sd a0, 56(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 64(s5)
+; RV64I-NEXT: lw a0, 56(s0)
; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 68(s5)
+; RV64I-NEXT: lw a0, 60(s0)
; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 72(s5)
+; RV64I-NEXT: lw a0, 64(s0)
; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 76(s5)
+; RV64I-NEXT: lw a0, 68(s0)
; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 80(s5)
+; RV64I-NEXT: lw a0, 72(s0)
; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 84(s5)
+; RV64I-NEXT: lw a0, 76(s0)
; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw s3, 88(s5)
-; RV64I-NEXT: lw s4, 92(s5)
-; RV64I-NEXT: lw s6, 96(s5)
-; RV64I-NEXT: lw s7, 100(s5)
-; RV64I-NEXT: lw s8, 104(s5)
-; RV64I-NEXT: lw s9, 108(s5)
-; RV64I-NEXT: lw s10, 112(s5)
-; RV64I-NEXT: lw s11, 116(s5)
-; RV64I-NEXT: lw s1, 120(s5)
-; RV64I-NEXT: lw s2, 124(s5)
+; RV64I-NEXT: lw a0, 80(s0)
+; RV64I-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw s11, 84(s0)
+; RV64I-NEXT: lw s1, 88(s0)
+; RV64I-NEXT: lw s2, 92(s0)
+; RV64I-NEXT: lw s3, 96(s0)
+; RV64I-NEXT: lw s4, 100(s0)
+; RV64I-NEXT: lw s5, 104(s0)
+; RV64I-NEXT: lw s6, 108(s0)
+; RV64I-NEXT: lw s7, 112(s0)
+; RV64I-NEXT: lw s8, 116(s0)
+; RV64I-NEXT: lw s9, 120(s0)
+; RV64I-NEXT: lw s10, 124(s0)
; RV64I-NEXT: call callee
-; RV64I-NEXT: sw s2, 124(s5)
-; RV64I-NEXT: sw s1, 120(s5)
-; RV64I-NEXT: sw s11, 116(s5)
-; RV64I-NEXT: sw s10, 112(s5)
-; RV64I-NEXT: sw s9, 108(s5)
-; RV64I-NEXT: sw s8, 104(s5)
-; RV64I-NEXT: sw s7, 100(s5)
-; RV64I-NEXT: sw s6, 96(s5)
-; RV64I-NEXT: sw s4, 92(s5)
-; RV64I-NEXT: sw s3, 88(s5)
+; RV64I-NEXT: sw s10, 124(s0)
+; RV64I-NEXT: sw s9, 120(s0)
+; RV64I-NEXT: sw s8, 116(s0)
+; RV64I-NEXT: sw s7, 112(s0)
+; RV64I-NEXT: sw s6, 108(s0)
+; RV64I-NEXT: sw s5, 104(s0)
+; RV64I-NEXT: sw s4, 100(s0)
+; RV64I-NEXT: sw s3, 96(s0)
+; RV64I-NEXT: sw s2, 92(s0)
+; RV64I-NEXT: sw s1, 88(s0)
+; RV64I-NEXT: sw s11, 84(s0)
+; RV64I-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a0, 80(s0)
; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 84(s5)
+; RV64I-NEXT: sw a0, 76(s0)
; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 80(s5)
+; RV64I-NEXT: sw a0, 72(s0)
; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 76(s5)
+; RV64I-NEXT: sw a0, 68(s0)
; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 72(s5)
+; RV64I-NEXT: sw a0, 64(s0)
; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 68(s5)
+; RV64I-NEXT: sw a0, 60(s0)
; RV64I-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 64(s5)
+; RV64I-NEXT: sw a0, 56(s0)
; RV64I-NEXT: ld a0, 56(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 60(s5)
+; RV64I-NEXT: sw a0, 52(s0)
; RV64I-NEXT: ld a0, 64(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 56(s5)
+; RV64I-NEXT: sw a0, 48(s0)
; RV64I-NEXT: ld a0, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 52(s5)
+; RV64I-NEXT: sw a0, 44(s0)
; RV64I-NEXT: ld a0, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 48(s5)
+; RV64I-NEXT: sw a0, 40(s0)
; RV64I-NEXT: ld a0, 88(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 44(s5)
+; RV64I-NEXT: sw a0, 36(s0)
; RV64I-NEXT: ld a0, 96(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 40(s5)
+; RV64I-NEXT: sw a0, 32(s0)
; RV64I-NEXT: ld a0, 104(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 36(s5)
+; RV64I-NEXT: sw a0, 28(s0)
; RV64I-NEXT: ld a0, 112(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 32(s5)
+; RV64I-NEXT: sw a0, 24(s0)
; RV64I-NEXT: ld a0, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 28(s5)
+; RV64I-NEXT: sw a0, 20(s0)
; RV64I-NEXT: ld a0, 128(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 24(s5)
+; RV64I-NEXT: sw a0, 16(s0)
; RV64I-NEXT: ld a0, 136(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 20(s5)
+; RV64I-NEXT: sw a0, 12(s0)
; RV64I-NEXT: ld a0, 144(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 16(s5)
+; RV64I-NEXT: sw a0, 8(s0)
; RV64I-NEXT: ld a0, 152(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var+12)(s0)
+; RV64I-NEXT: sw a0, 4(s0)
; RV64I-NEXT: ld a0, 160(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var+8)(s0)
-; RV64I-NEXT: ld a0, 168(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var+4)(s0)
-; RV64I-NEXT: ld a0, 176(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var)(s0)
-; RV64I-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 256(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 248(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s4, 240(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 232(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s6, 224(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s7, 216(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s8, 208(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s9, 200(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s10, 192(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s11, 184(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a0, 0(s0)
+; RV64I-NEXT: ld ra, 264(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 256(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 248(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 240(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 232(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 224(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s5, 216(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s6, 208(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s7, 200(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s8, 192(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s9, 184(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s10, 176(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s11, 168(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
@@ -2258,7 +2227,7 @@ define void @caller() {
; RV64I-NEXT: .cfi_restore s9
; RV64I-NEXT: .cfi_restore s10
; RV64I-NEXT: .cfi_restore s11
-; RV64I-NEXT: addi sp, sp, 288
+; RV64I-NEXT: addi sp, sp, 272
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
;
@@ -2272,136 +2241,135 @@ define void @caller() {
; RV64I-LP64E-NEXT: .cfi_offset ra, -8
; RV64I-LP64E-NEXT: .cfi_offset s0, -16
; RV64I-LP64E-NEXT: .cfi_offset s1, -24
-; RV64I-LP64E-NEXT: lui a0, %hi(var)
-; RV64I-LP64E-NEXT: lw a1, %lo(var)(a0)
-; RV64I-LP64E-NEXT: sd a1, 240(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a1, %lo(var+4)(a0)
-; RV64I-LP64E-NEXT: sd a1, 232(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a1, %lo(var+8)(a0)
-; RV64I-LP64E-NEXT: sd a1, 224(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a1, %lo(var+12)(a0)
-; RV64I-LP64E-NEXT: sd a1, 216(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: addi s1, a0, %lo(var)
-; RV64I-LP64E-NEXT: lw a0, 16(s1)
+; RV64I-LP64E-NEXT: lui s0, %hi(var)
+; RV64I-LP64E-NEXT: addi s0, s0, %lo(var)
+; RV64I-LP64E-NEXT: lw a0, 0(s0)
+; RV64I-LP64E-NEXT: sd a0, 240(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: lw a0, 4(s0)
+; RV64I-LP64E-NEXT: sd a0, 232(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: lw a0, 8(s0)
+; RV64I-LP64E-NEXT: sd a0, 224(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: lw a0, 12(s0)
+; RV64I-LP64E-NEXT: sd a0, 216(sp) # 8-byte Folded Spill
+; RV64I-LP64E-NEXT: lw a0, 16(s0)
; RV64I-LP64E-NEXT: sd a0, 208(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 20(s1)
+; RV64I-LP64E-NEXT: lw a0, 20(s0)
; RV64I-LP64E-NEXT: sd a0, 200(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 24(s1)
+; RV64I-LP64E-NEXT: lw a0, 24(s0)
; RV64I-LP64E-NEXT: sd a0, 192(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 28(s1)
+; RV64I-LP64E-NEXT: lw a0, 28(s0)
; RV64I-LP64E-NEXT: sd a0, 184(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 32(s1)
+; RV64I-LP64E-NEXT: lw a0, 32(s0)
; RV64I-LP64E-NEXT: sd a0, 176(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 36(s1)
+; RV64I-LP64E-NEXT: lw a0, 36(s0)
; RV64I-LP64E-NEXT: sd a0, 168(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 40(s1)
+; RV64I-LP64E-NEXT: lw a0, 40(s0)
; RV64I-LP64E-NEXT: sd a0, 160(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 44(s1)
+; RV64I-LP64E-NEXT: lw a0, 44(s0)
; RV64I-LP64E-NEXT: sd a0, 152(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 48(s1)
+; RV64I-LP64E-NEXT: lw a0, 48(s0)
; RV64I-LP64E-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 52(s1)
+; RV64I-LP64E-NEXT: lw a0, 52(s0)
; RV64I-LP64E-NEXT: sd a0, 136(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 56(s1)
+; RV64I-LP64E-NEXT: lw a0, 56(s0)
; RV64I-LP64E-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 60(s1)
+; RV64I-LP64E-NEXT: lw a0, 60(s0)
; RV64I-LP64E-NEXT: sd a0, 120(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 64(s1)
+; RV64I-LP64E-NEXT: lw a0, 64(s0)
; RV64I-LP64E-NEXT: sd a0, 112(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 68(s1)
+; RV64I-LP64E-NEXT: lw a0, 68(s0)
; RV64I-LP64E-NEXT: sd a0, 104(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 72(s1)
+; RV64I-LP64E-NEXT: lw a0, 72(s0)
; RV64I-LP64E-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 76(s1)
+; RV64I-LP64E-NEXT: lw a0, 76(s0)
; RV64I-LP64E-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 80(s1)
+; RV64I-LP64E-NEXT: lw a0, 80(s0)
; RV64I-LP64E-NEXT: sd a0, 80(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 84(s1)
+; RV64I-LP64E-NEXT: lw a0, 84(s0)
; RV64I-LP64E-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 88(s1)
+; RV64I-LP64E-NEXT: lw a0, 88(s0)
; RV64I-LP64E-NEXT: sd a0, 64(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 92(s1)
+; RV64I-LP64E-NEXT: lw a0, 92(s0)
; RV64I-LP64E-NEXT: sd a0, 56(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 96(s1)
+; RV64I-LP64E-NEXT: lw a0, 96(s0)
; RV64I-LP64E-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 100(s1)
+; RV64I-LP64E-NEXT: lw a0, 100(s0)
; RV64I-LP64E-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 104(s1)
+; RV64I-LP64E-NEXT: lw a0, 104(s0)
; RV64I-LP64E-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 108(s1)
+; RV64I-LP64E-NEXT: lw a0, 108(s0)
; RV64I-LP64E-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 112(s1)
+; RV64I-LP64E-NEXT: lw a0, 112(s0)
; RV64I-LP64E-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 116(s1)
+; RV64I-LP64E-NEXT: lw a0, 116(s0)
; RV64I-LP64E-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw a0, 120(s1)
+; RV64I-LP64E-NEXT: lw a0, 120(s0)
; RV64I-LP64E-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64I-LP64E-NEXT: lw s0, 124(s1)
+; RV64I-LP64E-NEXT: lw s1, 124(s0)
; RV64I-LP64E-NEXT: call callee
-; RV64I-LP64E-NEXT: sw s0, 124(s1)
+; RV64I-LP64E-NEXT: sw s1, 124(s0)
; RV64I-LP64E-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 120(s1)
+; RV64I-LP64E-NEXT: sw a0, 120(s0)
; RV64I-LP64E-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 116(s1)
+; RV64I-LP64E-NEXT: sw a0, 116(s0)
; RV64I-LP64E-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 112(s1)
+; RV64I-LP64E-NEXT: sw a0, 112(s0)
; RV64I-LP64E-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 108(s1)
+; RV64I-LP64E-NEXT: sw a0, 108(s0)
; RV64I-LP64E-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 104(s1)
+; RV64I-LP64E-NEXT: sw a0, 104(s0)
; RV64I-LP64E-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 100(s1)
+; RV64I-LP64E-NEXT: sw a0, 100(s0)
; RV64I-LP64E-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 96(s1)
+; RV64I-LP64E-NEXT: sw a0, 96(s0)
; RV64I-LP64E-NEXT: ld a0, 56(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 92(s1)
+; RV64I-LP64E-NEXT: sw a0, 92(s0)
; RV64I-LP64E-NEXT: ld a0, 64(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 88(s1)
+; RV64I-LP64E-NEXT: sw a0, 88(s0)
; RV64I-LP64E-NEXT: ld a0, 72(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 84(s1)
+; RV64I-LP64E-NEXT: sw a0, 84(s0)
; RV64I-LP64E-NEXT: ld a0, 80(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 80(s1)
+; RV64I-LP64E-NEXT: sw a0, 80(s0)
; RV64I-LP64E-NEXT: ld a0, 88(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 76(s1)
+; RV64I-LP64E-NEXT: sw a0, 76(s0)
; RV64I-LP64E-NEXT: ld a0, 96(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 72(s1)
+; RV64I-LP64E-NEXT: sw a0, 72(s0)
; RV64I-LP64E-NEXT: ld a0, 104(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 68(s1)
+; RV64I-LP64E-NEXT: sw a0, 68(s0)
; RV64I-LP64E-NEXT: ld a0, 112(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 64(s1)
+; RV64I-LP64E-NEXT: sw a0, 64(s0)
; RV64I-LP64E-NEXT: ld a0, 120(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 60(s1)
+; RV64I-LP64E-NEXT: sw a0, 60(s0)
; RV64I-LP64E-NEXT: ld a0, 128(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 56(s1)
+; RV64I-LP64E-NEXT: sw a0, 56(s0)
; RV64I-LP64E-NEXT: ld a0, 136(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 52(s1)
+; RV64I-LP64E-NEXT: sw a0, 52(s0)
; RV64I-LP64E-NEXT: ld a0, 144(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 48(s1)
+; RV64I-LP64E-NEXT: sw a0, 48(s0)
; RV64I-LP64E-NEXT: ld a0, 152(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 44(s1)
+; RV64I-LP64E-NEXT: sw a0, 44(s0)
; RV64I-LP64E-NEXT: ld a0, 160(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 40(s1)
+; RV64I-LP64E-NEXT: sw a0, 40(s0)
; RV64I-LP64E-NEXT: ld a0, 168(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 36(s1)
+; RV64I-LP64E-NEXT: sw a0, 36(s0)
; RV64I-LP64E-NEXT: ld a0, 176(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 32(s1)
+; RV64I-LP64E-NEXT: sw a0, 32(s0)
; RV64I-LP64E-NEXT: ld a0, 184(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 28(s1)
+; RV64I-LP64E-NEXT: sw a0, 28(s0)
; RV64I-LP64E-NEXT: ld a0, 192(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 24(s1)
+; RV64I-LP64E-NEXT: sw a0, 24(s0)
; RV64I-LP64E-NEXT: ld a0, 200(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 20(s1)
+; RV64I-LP64E-NEXT: sw a0, 20(s0)
; RV64I-LP64E-NEXT: ld a0, 208(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, 16(s1)
-; RV64I-LP64E-NEXT: lui a1, %hi(var)
+; RV64I-LP64E-NEXT: sw a0, 16(s0)
; RV64I-LP64E-NEXT: ld a0, 216(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, %lo(var+12)(a1)
+; RV64I-LP64E-NEXT: sw a0, 12(s0)
; RV64I-LP64E-NEXT: ld a0, 224(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, %lo(var+8)(a1)
+; RV64I-LP64E-NEXT: sw a0, 8(s0)
; RV64I-LP64E-NEXT: ld a0, 232(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, %lo(var+4)(a1)
+; RV64I-LP64E-NEXT: sw a0, 4(s0)
; RV64I-LP64E-NEXT: ld a0, 240(sp) # 8-byte Folded Reload
-; RV64I-LP64E-NEXT: sw a0, %lo(var)(a1)
+; RV64I-LP64E-NEXT: sw a0, 0(s0)
; RV64I-LP64E-NEXT: ld ra, 264(sp) # 8-byte Folded Reload
; RV64I-LP64E-NEXT: ld s0, 256(sp) # 8-byte Folded Reload
; RV64I-LP64E-NEXT: ld s1, 248(sp) # 8-byte Folded Reload
@@ -2445,118 +2413,116 @@ define void @caller() {
; RV64I-WITH-FP-NEXT: addi s0, sp, 288
; RV64I-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV64I-WITH-FP-NEXT: lui s1, %hi(var)
-; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(s1)
+; RV64I-WITH-FP-NEXT: addi s1, s1, %lo(var)
+; RV64I-WITH-FP-NEXT: lw a0, 0(s1)
; RV64I-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(s1)
+; RV64I-WITH-FP-NEXT: lw a0, 4(s1)
; RV64I-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(s1)
+; RV64I-WITH-FP-NEXT: lw a0, 8(s1)
; RV64I-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(s1)
+; RV64I-WITH-FP-NEXT: lw a0, 12(s1)
; RV64I-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: addi s6, s1, %lo(var)
-; RV64I-WITH-FP-NEXT: lw a0, 16(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 16(s1)
; RV64I-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 20(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 20(s1)
; RV64I-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 24(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 24(s1)
; RV64I-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 28(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 28(s1)
; RV64I-WITH-FP-NEXT: sd a0, -168(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 32(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 32(s1)
; RV64I-WITH-FP-NEXT: sd a0, -176(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 36(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 36(s1)
; RV64I-WITH-FP-NEXT: sd a0, -184(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 40(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 40(s1)
; RV64I-WITH-FP-NEXT: sd a0, -192(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 44(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 44(s1)
; RV64I-WITH-FP-NEXT: sd a0, -200(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 48(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 48(s1)
; RV64I-WITH-FP-NEXT: sd a0, -208(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 52(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 52(s1)
; RV64I-WITH-FP-NEXT: sd a0, -216(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 56(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 56(s1)
; RV64I-WITH-FP-NEXT: sd a0, -224(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 60(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 60(s1)
; RV64I-WITH-FP-NEXT: sd a0, -232(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 64(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 64(s1)
; RV64I-WITH-FP-NEXT: sd a0, -240(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 68(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 68(s1)
; RV64I-WITH-FP-NEXT: sd a0, -248(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 72(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 72(s1)
; RV64I-WITH-FP-NEXT: sd a0, -256(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 76(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 76(s1)
; RV64I-WITH-FP-NEXT: sd a0, -264(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 80(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 80(s1)
; RV64I-WITH-FP-NEXT: sd a0, -272(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 84(s6)
+; RV64I-WITH-FP-NEXT: lw a0, 84(s1)
; RV64I-WITH-FP-NEXT: sd a0, -280(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw a0, 88(s6)
-; RV64I-WITH-FP-NEXT: sd a0, -288(s0) # 8-byte Folded Spill
-; RV64I-WITH-FP-NEXT: lw s8, 92(s6)
-; RV64I-WITH-FP-NEXT: lw s9, 96(s6)
-; RV64I-WITH-FP-NEXT: lw s10, 100(s6)
-; RV64I-WITH-FP-NEXT: lw s11, 104(s6)
-; RV64I-WITH-FP-NEXT: lw s2, 108(s6)
-; RV64I-WITH-FP-NEXT: lw s3, 112(s6)
-; RV64I-WITH-FP-NEXT: lw s4, 116(s6)
-; RV64I-WITH-FP-NEXT: lw s5, 120(s6)
-; RV64I-WITH-FP-NEXT: lw s7, 124(s6)
+; RV64I-WITH-FP-NEXT: lw s4, 88(s1)
+; RV64I-WITH-FP-NEXT: lw s5, 92(s1)
+; RV64I-WITH-FP-NEXT: lw s6, 96(s1)
+; RV64I-WITH-FP-NEXT: lw s7, 100(s1)
+; RV64I-WITH-FP-NEXT: lw s8, 104(s1)
+; RV64I-WITH-FP-NEXT: lw s9, 108(s1)
+; RV64I-WITH-FP-NEXT: lw s10, 112(s1)
+; RV64I-WITH-FP-NEXT: lw s11, 116(s1)
+; RV64I-WITH-FP-NEXT: lw s2, 120(s1)
+; RV64I-WITH-FP-NEXT: lw s3, 124(s1)
; RV64I-WITH-FP-NEXT: call callee
-; RV64I-WITH-FP-NEXT: sw s7, 124(s6)
-; RV64I-WITH-FP-NEXT: sw s5, 120(s6)
-; RV64I-WITH-FP-NEXT: sw s4, 116(s6)
-; RV64I-WITH-FP-NEXT: sw s3, 112(s6)
-; RV64I-WITH-FP-NEXT: sw s2, 108(s6)
-; RV64I-WITH-FP-NEXT: sw s11, 104(s6)
-; RV64I-WITH-FP-NEXT: sw s10, 100(s6)
-; RV64I-WITH-FP-NEXT: sw s9, 96(s6)
-; RV64I-WITH-FP-NEXT: sw s8, 92(s6)
-; RV64I-WITH-FP-NEXT: ld a0, -288(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 88(s6)
+; RV64I-WITH-FP-NEXT: sw s3, 124(s1)
+; RV64I-WITH-FP-NEXT: sw s2, 120(s1)
+; RV64I-WITH-FP-NEXT: sw s11, 116(s1)
+; RV64I-WITH-FP-NEXT: sw s10, 112(s1)
+; RV64I-WITH-FP-NEXT: sw s9, 108(s1)
+; RV64I-WITH-FP-NEXT: sw s8, 104(s1)
+; RV64I-WITH-FP-NEXT: sw s7, 100(s1)
+; RV64I-WITH-FP-NEXT: sw s6, 96(s1)
+; RV64I-WITH-FP-NEXT: sw s5, 92(s1)
+; RV64I-WITH-FP-NEXT: sw s4, 88(s1)
; RV64I-WITH-FP-NEXT: ld a0, -280(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 84(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 84(s1)
; RV64I-WITH-FP-NEXT: ld a0, -272(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 80(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 80(s1)
; RV64I-WITH-FP-NEXT: ld a0, -264(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 76(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 76(s1)
; RV64I-WITH-FP-NEXT: ld a0, -256(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 72(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 72(s1)
; RV64I-WITH-FP-NEXT: ld a0, -248(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 68(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 68(s1)
; RV64I-WITH-FP-NEXT: ld a0, -240(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 64(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 64(s1)
; RV64I-WITH-FP-NEXT: ld a0, -232(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 60(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 60(s1)
; RV64I-WITH-FP-NEXT: ld a0, -224(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 56(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 56(s1)
; RV64I-WITH-FP-NEXT: ld a0, -216(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 52(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 52(s1)
; RV64I-WITH-FP-NEXT: ld a0, -208(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 48(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 48(s1)
; RV64I-WITH-FP-NEXT: ld a0, -200(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 44(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 44(s1)
; RV64I-WITH-FP-NEXT: ld a0, -192(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 40(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 40(s1)
; RV64I-WITH-FP-NEXT: ld a0, -184(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 36(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 36(s1)
; RV64I-WITH-FP-NEXT: ld a0, -176(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 32(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 32(s1)
; RV64I-WITH-FP-NEXT: ld a0, -168(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 28(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 28(s1)
; RV64I-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 24(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 24(s1)
; RV64I-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 20(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 20(s1)
; RV64I-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, 16(s6)
+; RV64I-WITH-FP-NEXT: sw a0, 16(s1)
; RV64I-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(s1)
+; RV64I-WITH-FP-NEXT: sw a0, 12(s1)
; RV64I-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(s1)
+; RV64I-WITH-FP-NEXT: sw a0, 8(s1)
; RV64I-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(s1)
+; RV64I-WITH-FP-NEXT: sw a0, 4(s1)
; RV64I-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload
-; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(s1)
+; RV64I-WITH-FP-NEXT: sw a0, 0(s1)
; RV64I-WITH-FP-NEXT: .cfi_def_cfa sp, 288
; RV64I-WITH-FP-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
@@ -2608,116 +2574,114 @@ define void @caller() {
; RV64IZCMP-NEXT: addi sp, sp, -128
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 288
; RV64IZCMP-NEXT: lui s0, %hi(var)
-; RV64IZCMP-NEXT: lw a0, %lo(var)(s0)
+; RV64IZCMP-NEXT: addi s0, s0, %lo(var)
+; RV64IZCMP-NEXT: lw a0, 0(s0)
; RV64IZCMP-NEXT: sd a0, 168(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var+4)(s0)
+; RV64IZCMP-NEXT: lw a0, 4(s0)
; RV64IZCMP-NEXT: sd a0, 160(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var+8)(s0)
+; RV64IZCMP-NEXT: lw a0, 8(s0)
; RV64IZCMP-NEXT: sd a0, 152(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var+12)(s0)
+; RV64IZCMP-NEXT: lw a0, 12(s0)
; RV64IZCMP-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: addi s1, s0, %lo(var)
-; RV64IZCMP-NEXT: lw a0, 16(s1)
+; RV64IZCMP-NEXT: lw a0, 16(s0)
; RV64IZCMP-NEXT: sd a0, 136(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 20(s1)
+; RV64IZCMP-NEXT: lw a0, 20(s0)
; RV64IZCMP-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 24(s1)
+; RV64IZCMP-NEXT: lw a0, 24(s0)
; RV64IZCMP-NEXT: sd a0, 120(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 28(s1)
+; RV64IZCMP-NEXT: lw a0, 28(s0)
; RV64IZCMP-NEXT: sd a0, 112(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 32(s1)
+; RV64IZCMP-NEXT: lw a0, 32(s0)
; RV64IZCMP-NEXT: sd a0, 104(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 36(s1)
+; RV64IZCMP-NEXT: lw a0, 36(s0)
; RV64IZCMP-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 40(s1)
+; RV64IZCMP-NEXT: lw a0, 40(s0)
; RV64IZCMP-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 44(s1)
+; RV64IZCMP-NEXT: lw a0, 44(s0)
; RV64IZCMP-NEXT: sd a0, 80(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 48(s1)
+; RV64IZCMP-NEXT: lw a0, 48(s0)
; RV64IZCMP-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 52(s1)
+; RV64IZCMP-NEXT: lw a0, 52(s0)
; RV64IZCMP-NEXT: sd a0, 64(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 56(s1)
+; RV64IZCMP-NEXT: lw a0, 56(s0)
; RV64IZCMP-NEXT: sd a0, 56(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 60(s1)
+; RV64IZCMP-NEXT: lw a0, 60(s0)
; RV64IZCMP-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 64(s1)
+; RV64IZCMP-NEXT: lw a0, 64(s0)
; RV64IZCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 68(s1)
+; RV64IZCMP-NEXT: lw a0, 68(s0)
; RV64IZCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 72(s1)
+; RV64IZCMP-NEXT: lw a0, 72(s0)
; RV64IZCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 76(s1)
+; RV64IZCMP-NEXT: lw a0, 76(s0)
; RV64IZCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 80(s1)
+; RV64IZCMP-NEXT: lw a0, 80(s0)
; RV64IZCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 84(s1)
-; RV64IZCMP-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw s4, 88(s1)
-; RV64IZCMP-NEXT: lw s5, 92(s1)
-; RV64IZCMP-NEXT: lw s6, 96(s1)
-; RV64IZCMP-NEXT: lw s7, 100(s1)
-; RV64IZCMP-NEXT: lw s8, 104(s1)
-; RV64IZCMP-NEXT: lw s9, 108(s1)
-; RV64IZCMP-NEXT: lw s10, 112(s1)
-; RV64IZCMP-NEXT: lw s11, 116(s1)
-; RV64IZCMP-NEXT: lw s2, 120(s1)
-; RV64IZCMP-NEXT: lw s3, 124(s1)
+; RV64IZCMP-NEXT: lw s1, 84(s0)
+; RV64IZCMP-NEXT: lw s2, 88(s0)
+; RV64IZCMP-NEXT: lw s3, 92(s0)
+; RV64IZCMP-NEXT: lw s4, 96(s0)
+; RV64IZCMP-NEXT: lw s5, 100(s0)
+; RV64IZCMP-NEXT: lw s6, 104(s0)
+; RV64IZCMP-NEXT: lw s7, 108(s0)
+; RV64IZCMP-NEXT: lw s8, 112(s0)
+; RV64IZCMP-NEXT: lw s9, 116(s0)
+; RV64IZCMP-NEXT: lw s10, 120(s0)
+; RV64IZCMP-NEXT: lw s11, 124(s0)
; RV64IZCMP-NEXT: call callee
-; RV64IZCMP-NEXT: sw s3, 124(s1)
-; RV64IZCMP-NEXT: sw s2, 120(s1)
-; RV64IZCMP-NEXT: sw s11, 116(s1)
-; RV64IZCMP-NEXT: sw s10, 112(s1)
-; RV64IZCMP-NEXT: sw s9, 108(s1)
-; RV64IZCMP-NEXT: sw s8, 104(s1)
-; RV64IZCMP-NEXT: sw s7, 100(s1)
-; RV64IZCMP-NEXT: sw s6, 96(s1)
-; RV64IZCMP-NEXT: sw s5, 92(s1)
-; RV64IZCMP-NEXT: sw s4, 88(s1)
-; RV64IZCMP-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 84(s1)
+; RV64IZCMP-NEXT: sw s11, 124(s0)
+; RV64IZCMP-NEXT: sw s10, 120(s0)
+; RV64IZCMP-NEXT: sw s9, 116(s0)
+; RV64IZCMP-NEXT: sw s8, 112(s0)
+; RV64IZCMP-NEXT: sw s7, 108(s0)
+; RV64IZCMP-NEXT: sw s6, 104(s0)
+; RV64IZCMP-NEXT: sw s5, 100(s0)
+; RV64IZCMP-NEXT: sw s4, 96(s0)
+; RV64IZCMP-NEXT: sw s3, 92(s0)
+; RV64IZCMP-NEXT: sw s2, 88(s0)
+; RV64IZCMP-NEXT: sw s1, 84(s0)
; RV64IZCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 80(s1)
+; RV64IZCMP-NEXT: sw a0, 80(s0)
; RV64IZCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 76(s1)
+; RV64IZCMP-NEXT: sw a0, 76(s0)
; RV64IZCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 72(s1)
+; RV64IZCMP-NEXT: sw a0, 72(s0)
; RV64IZCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 68(s1)
+; RV64IZCMP-NEXT: sw a0, 68(s0)
; RV64IZCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 64(s1)
+; RV64IZCMP-NEXT: sw a0, 64(s0)
; RV64IZCMP-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 60(s1)
+; RV64IZCMP-NEXT: sw a0, 60(s0)
; RV64IZCMP-NEXT: ld a0, 56(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 56(s1)
+; RV64IZCMP-NEXT: sw a0, 56(s0)
; RV64IZCMP-NEXT: ld a0, 64(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 52(s1)
+; RV64IZCMP-NEXT: sw a0, 52(s0)
; RV64IZCMP-NEXT: ld a0, 72(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 48(s1)
+; RV64IZCMP-NEXT: sw a0, 48(s0)
; RV64IZCMP-NEXT: ld a0, 80(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 44(s1)
+; RV64IZCMP-NEXT: sw a0, 44(s0)
; RV64IZCMP-NEXT: ld a0, 88(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 40(s1)
+; RV64IZCMP-NEXT: sw a0, 40(s0)
; RV64IZCMP-NEXT: ld a0, 96(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 36(s1)
+; RV64IZCMP-NEXT: sw a0, 36(s0)
; RV64IZCMP-NEXT: ld a0, 104(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 32(s1)
+; RV64IZCMP-NEXT: sw a0, 32(s0)
; RV64IZCMP-NEXT: ld a0, 112(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 28(s1)
+; RV64IZCMP-NEXT: sw a0, 28(s0)
; RV64IZCMP-NEXT: ld a0, 120(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 24(s1)
+; RV64IZCMP-NEXT: sw a0, 24(s0)
; RV64IZCMP-NEXT: ld a0, 128(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 20(s1)
+; RV64IZCMP-NEXT: sw a0, 20(s0)
; RV64IZCMP-NEXT: ld a0, 136(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 16(s1)
+; RV64IZCMP-NEXT: sw a0, 16(s0)
; RV64IZCMP-NEXT: ld a0, 144(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var+12)(s0)
+; RV64IZCMP-NEXT: sw a0, 12(s0)
; RV64IZCMP-NEXT: ld a0, 152(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var+8)(s0)
+; RV64IZCMP-NEXT: sw a0, 8(s0)
; RV64IZCMP-NEXT: ld a0, 160(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var+4)(s0)
+; RV64IZCMP-NEXT: sw a0, 4(s0)
; RV64IZCMP-NEXT: ld a0, 168(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var)(s0)
+; RV64IZCMP-NEXT: sw a0, 0(s0)
; RV64IZCMP-NEXT: addi sp, sp, 128
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 160
; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 160
@@ -2754,16 +2718,16 @@ define void @caller() {
; RV64IZCMP-WITH-FP-NEXT: .cfi_offset s11, -104
; RV64IZCMP-WITH-FP-NEXT: addi s0, sp, 288
; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
-; RV64IZCMP-WITH-FP-NEXT: lui s6, %hi(var)
-; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var)(s6)
+; RV64IZCMP-WITH-FP-NEXT: lui s1, %hi(var)
+; RV64IZCMP-WITH-FP-NEXT: addi s1, s1, %lo(var)
+; RV64IZCMP-WITH-FP-NEXT: lw a0, 0(s1)
; RV64IZCMP-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(s6)
+; RV64IZCMP-WITH-FP-NEXT: lw a0, 4(s1)
; RV64IZCMP-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(s6)
+; RV64IZCMP-WITH-FP-NEXT: lw a0, 8(s1)
; RV64IZCMP-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(s6)
+; RV64IZCMP-WITH-FP-NEXT: lw a0, 12(s1)
; RV64IZCMP-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: addi s1, s6, %lo(var)
; RV64IZCMP-WITH-FP-NEXT: lw a0, 16(s1)
; RV64IZCMP-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
; RV64IZCMP-WITH-FP-NEXT: lw a0, 20(s1)
@@ -2800,29 +2764,27 @@ define void @caller() {
; RV64IZCMP-WITH-FP-NEXT: sd a0, -272(s0) # 8-byte Folded Spill
; RV64IZCMP-WITH-FP-NEXT: lw a0, 84(s1)
; RV64IZCMP-WITH-FP-NEXT: sd a0, -280(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw a0, 88(s1)
-; RV64IZCMP-WITH-FP-NEXT: sd a0, -288(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw s8, 92(s1)
-; RV64IZCMP-WITH-FP-NEXT: lw s9, 96(s1)
-; RV64IZCMP-WITH-FP-NEXT: lw s10, 100(s1)
-; RV64IZCMP-WITH-FP-NEXT: lw s11, 104(s1)
-; RV64IZCMP-WITH-FP-NEXT: lw s2, 108(s1)
-; RV64IZCMP-WITH-FP-NEXT: lw s3, 112(s1)
-; RV64IZCMP-WITH-FP-NEXT: lw s4, 116(s1)
-; RV64IZCMP-WITH-FP-NEXT: lw s5, 120(s1)
-; RV64IZCMP-WITH-FP-NEXT: lw s7, 124(s1)
+; RV64IZCMP-WITH-FP-NEXT: lw s4, 88(s1)
+; RV64IZCMP-WITH-FP-NEXT: lw s5, 92(s1)
+; RV64IZCMP-WITH-FP-NEXT: lw s6, 96(s1)
+; RV64IZCMP-WITH-FP-NEXT: lw s7, 100(s1)
+; RV64IZCMP-WITH-FP-NEXT: lw s8, 104(s1)
+; RV64IZCMP-WITH-FP-NEXT: lw s9, 108(s1)
+; RV64IZCMP-WITH-FP-NEXT: lw s10, 112(s1)
+; RV64IZCMP-WITH-FP-NEXT: lw s11, 116(s1)
+; RV64IZCMP-WITH-FP-NEXT: lw s2, 120(s1)
+; RV64IZCMP-WITH-FP-NEXT: lw s3, 124(s1)
; RV64IZCMP-WITH-FP-NEXT: call callee
-; RV64IZCMP-WITH-FP-NEXT: sw s7, 124(s1)
-; RV64IZCMP-WITH-FP-NEXT: sw s5, 120(s1)
-; RV64IZCMP-WITH-FP-NEXT: sw s4, 116(s1)
-; RV64IZCMP-WITH-FP-NEXT: sw s3, 112(s1)
-; RV64IZCMP-WITH-FP-NEXT: sw s2, 108(s1)
-; RV64IZCMP-WITH-FP-NEXT: sw s11, 104(s1)
-; RV64IZCMP-WITH-FP-NEXT: sw s10, 100(s1)
-; RV64IZCMP-WITH-FP-NEXT: sw s9, 96(s1)
-; RV64IZCMP-WITH-FP-NEXT: sw s8, 92(s1)
-; RV64IZCMP-WITH-FP-NEXT: ld a0, -288(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, 88(s1)
+; RV64IZCMP-WITH-FP-NEXT: sw s3, 124(s1)
+; RV64IZCMP-WITH-FP-NEXT: sw s2, 120(s1)
+; RV64IZCMP-WITH-FP-NEXT: sw s11, 116(s1)
+; RV64IZCMP-WITH-FP-NEXT: sw s10, 112(s1)
+; RV64IZCMP-WITH-FP-NEXT: sw s9, 108(s1)
+; RV64IZCMP-WITH-FP-NEXT: sw s8, 104(s1)
+; RV64IZCMP-WITH-FP-NEXT: sw s7, 100(s1)
+; RV64IZCMP-WITH-FP-NEXT: sw s6, 96(s1)
+; RV64IZCMP-WITH-FP-NEXT: sw s5, 92(s1)
+; RV64IZCMP-WITH-FP-NEXT: sw s4, 88(s1)
; RV64IZCMP-WITH-FP-NEXT: ld a0, -280(s0) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: sw a0, 84(s1)
; RV64IZCMP-WITH-FP-NEXT: ld a0, -272(s0) # 8-byte Folded Reload
@@ -2860,13 +2822,13 @@ define void @caller() {
; RV64IZCMP-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: sw a0, 16(s1)
; RV64IZCMP-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(s6)
+; RV64IZCMP-WITH-FP-NEXT: sw a0, 12(s1)
; RV64IZCMP-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(s6)
+; RV64IZCMP-WITH-FP-NEXT: sw a0, 8(s1)
; RV64IZCMP-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(s6)
+; RV64IZCMP-WITH-FP-NEXT: sw a0, 4(s1)
; RV64IZCMP-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload
-; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var)(s6)
+; RV64IZCMP-WITH-FP-NEXT: sw a0, 0(s1)
; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa sp, 288
; RV64IZCMP-WITH-FP-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll
index 81ef194da8b47..053688f79fe1c 100644
--- a/llvm/test/CodeGen/RISCV/double-mem.ll
+++ b/llvm/test/CodeGen/RISCV/double-mem.ll
@@ -104,48 +104,48 @@ define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fadd.d fa0, fa0, fa1
; CHECKIFD-NEXT: lui a0, %hi(G)
-; CHECKIFD-NEXT: fld fa5, %lo(G)(a0)
-; CHECKIFD-NEXT: addi a1, a0, %lo(G)
-; CHECKIFD-NEXT: fsd fa0, %lo(G)(a0)
-; CHECKIFD-NEXT: fld fa5, 72(a1)
-; CHECKIFD-NEXT: fsd fa0, 72(a1)
+; CHECKIFD-NEXT: addi a0, a0, %lo(G)
+; CHECKIFD-NEXT: fld fa5, 0(a0)
+; CHECKIFD-NEXT: fsd fa0, 0(a0)
+; CHECKIFD-NEXT: fld fa5, 72(a0)
+; CHECKIFD-NEXT: fsd fa0, 72(a0)
; CHECKIFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: fld_fsd_global:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: lui a4, %hi(G)
+; RV32IZFINXZDINX-NEXT: addi a4, a4, %lo(G)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT: lw zero, %lo(G)(a4)
-; RV32IZFINXZDINX-NEXT: lw zero, %lo(G+4)(a4)
-; RV32IZFINXZDINX-NEXT: addi a2, a4, %lo(G)
-; RV32IZFINXZDINX-NEXT: sw a0, %lo(G)(a4)
-; RV32IZFINXZDINX-NEXT: sw a1, %lo(G+4)(a4)
-; RV32IZFINXZDINX-NEXT: lw zero, 72(a2)
-; RV32IZFINXZDINX-NEXT: lw zero, 76(a2)
-; RV32IZFINXZDINX-NEXT: sw a0, 72(a2)
-; RV32IZFINXZDINX-NEXT: sw a1, 76(a2)
+; RV32IZFINXZDINX-NEXT: lw zero, 0(a4)
+; RV32IZFINXZDINX-NEXT: lw zero, 4(a4)
+; RV32IZFINXZDINX-NEXT: sw a0, 0(a4)
+; RV32IZFINXZDINX-NEXT: sw a1, 4(a4)
+; RV32IZFINXZDINX-NEXT: lw zero, 72(a4)
+; RV32IZFINXZDINX-NEXT: lw zero, 76(a4)
+; RV32IZFINXZDINX-NEXT: sw a0, 72(a4)
+; RV32IZFINXZDINX-NEXT: sw a1, 76(a4)
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fld_fsd_global:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: lui a1, %hi(G)
-; RV64IZFINXZDINX-NEXT: ld zero, %lo(G)(a1)
-; RV64IZFINXZDINX-NEXT: addi a2, a1, %lo(G)
-; RV64IZFINXZDINX-NEXT: sd a0, %lo(G)(a1)
-; RV64IZFINXZDINX-NEXT: ld zero, 72(a2)
-; RV64IZFINXZDINX-NEXT: sd a0, 72(a2)
+; RV64IZFINXZDINX-NEXT: addi a1, a1, %lo(G)
+; RV64IZFINXZDINX-NEXT: ld zero, 0(a1)
+; RV64IZFINXZDINX-NEXT: sd a0, 0(a1)
+; RV64IZFINXZDINX-NEXT: ld zero, 72(a1)
+; RV64IZFINXZDINX-NEXT: sd a0, 72(a1)
; RV64IZFINXZDINX-NEXT: ret
;
; RV32IZFINXZDINXZILSD-LABEL: fld_fsd_global:
; RV32IZFINXZDINXZILSD: # %bb.0:
; RV32IZFINXZDINXZILSD-NEXT: lui a4, %hi(G)
+; RV32IZFINXZDINXZILSD-NEXT: addi a4, a4, %lo(G)
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a2
-; RV32IZFINXZDINXZILSD-NEXT: ld zero, %lo(G)(a4)
-; RV32IZFINXZDINXZILSD-NEXT: addi a2, a4, %lo(G)
-; RV32IZFINXZDINXZILSD-NEXT: sd a0, %lo(G)(a4)
-; RV32IZFINXZDINXZILSD-NEXT: ld zero, 72(a2)
-; RV32IZFINXZDINXZILSD-NEXT: sd a0, 72(a2)
+; RV32IZFINXZDINXZILSD-NEXT: ld zero, 0(a4)
+; RV32IZFINXZDINXZILSD-NEXT: sd a0, 0(a4)
+; RV32IZFINXZDINXZILSD-NEXT: ld zero, 72(a4)
+; RV32IZFINXZDINXZILSD-NEXT: sd a0, 72(a4)
; RV32IZFINXZDINXZILSD-NEXT: ret
; Use %a and %b in an FP op to ensure floating point registers are used, even
; for the soft float ABI
diff --git a/llvm/test/CodeGen/RISCV/float-mem.ll b/llvm/test/CodeGen/RISCV/float-mem.ll
index 3779d39a753e1..55fe5dc598dfb 100644
--- a/llvm/test/CodeGen/RISCV/float-mem.ll
+++ b/llvm/test/CodeGen/RISCV/float-mem.ll
@@ -64,22 +64,22 @@ define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fadd.s fa0, fa0, fa1
; CHECKIF-NEXT: lui a0, %hi(G)
-; CHECKIF-NEXT: flw fa5, %lo(G)(a0)
-; CHECKIF-NEXT: addi a1, a0, %lo(G)
-; CHECKIF-NEXT: fsw fa0, %lo(G)(a0)
-; CHECKIF-NEXT: flw fa5, 36(a1)
-; CHECKIF-NEXT: fsw fa0, 36(a1)
+; CHECKIF-NEXT: addi a0, a0, %lo(G)
+; CHECKIF-NEXT: flw fa5, 0(a0)
+; CHECKIF-NEXT: fsw fa0, 0(a0)
+; CHECKIF-NEXT: flw fa5, 36(a0)
+; CHECKIF-NEXT: fsw fa0, 36(a0)
; CHECKIF-NEXT: ret
;
; CHECKIZFINX-LABEL: flw_fsw_global:
; CHECKIZFINX: # %bb.0:
; CHECKIZFINX-NEXT: fadd.s a0, a0, a1
; CHECKIZFINX-NEXT: lui a1, %hi(G)
-; CHECKIZFINX-NEXT: lw zero, %lo(G)(a1)
-; CHECKIZFINX-NEXT: addi a2, a1, %lo(G)
-; CHECKIZFINX-NEXT: sw a0, %lo(G)(a1)
-; CHECKIZFINX-NEXT: lw zero, 36(a2)
-; CHECKIZFINX-NEXT: sw a0, 36(a2)
+; CHECKIZFINX-NEXT: addi a1, a1, %lo(G)
+; CHECKIZFINX-NEXT: lw zero, 0(a1)
+; CHECKIZFINX-NEXT: sw a0, 0(a1)
+; CHECKIZFINX-NEXT: lw zero, 36(a1)
+; CHECKIZFINX-NEXT: sw a0, 36(a1)
; CHECKIZFINX-NEXT: ret
%1 = fadd float %a, %b
%2 = load volatile float, ptr @G
diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
index aa65ebecbe56a..24fc8c65581af 100644
--- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
+++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
@@ -70,8 +70,8 @@ define dso_local i64 @load_g_1() nounwind {
; RV32I-LABEL: load_g_1:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a1, %hi(g_1)
-; RV32I-NEXT: lw a0, %lo(g_1)(a1)
; RV32I-NEXT: addi a1, a1, %lo(g_1)
+; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: ret
;
@@ -113,8 +113,8 @@ define dso_local i64 @load_g_2() nounwind {
; RV32I-LABEL: load_g_2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a1, %hi(g_2)
-; RV32I-NEXT: lw a0, %lo(g_2)(a1)
; RV32I-NEXT: addi a1, a1, %lo(g_2)
+; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: ret
;
@@ -156,8 +156,8 @@ define dso_local i64 @load_g_4() nounwind {
; RV32I-LABEL: load_g_4:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a1, %hi(g_4)
-; RV32I-NEXT: lw a0, %lo(g_4)(a1)
; RV32I-NEXT: addi a1, a1, %lo(g_4)
+; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: ret
;
@@ -283,8 +283,8 @@ define dso_local void @store_g_4() nounwind {
; RV32I-LABEL: store_g_4:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(g_4)
-; RV32I-NEXT: sw zero, %lo(g_4)(a0)
; RV32I-NEXT: addi a0, a0, %lo(g_4)
+; RV32I-NEXT: sw zero, 0(a0)
; RV32I-NEXT: sw zero, 4(a0)
; RV32I-NEXT: ret
;
@@ -665,18 +665,18 @@ define dso_local i64 @load_tl_4() nounwind {
; RV32I-LABEL: load_tl_4:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %tprel_hi(tl_4)
-; RV32I-NEXT: add a1, a0, tp, %tprel_add(tl_4)
-; RV32I-NEXT: lw a0, %tprel_lo(tl_4)(a1)
-; RV32I-NEXT: addi a1, a1, %tprel_lo(tl_4)
+; RV32I-NEXT: add a0, a0, tp, %tprel_add(tl_4)
+; RV32I-NEXT: addi a1, a0, %tprel_lo(tl_4)
+; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: ret
;
; RV32I-MEDIUM-LABEL: load_tl_4:
; RV32I-MEDIUM: # %bb.0: # %entry
; RV32I-MEDIUM-NEXT: lui a0, %tprel_hi(tl_4)
-; RV32I-MEDIUM-NEXT: add a1, a0, tp, %tprel_add(tl_4)
-; RV32I-MEDIUM-NEXT: lw a0, %tprel_lo(tl_4)(a1)
-; RV32I-MEDIUM-NEXT: addi a1, a1, %tprel_lo(tl_4)
+; RV32I-MEDIUM-NEXT: add a0, a0, tp, %tprel_add(tl_4)
+; RV32I-MEDIUM-NEXT: addi a1, a0, %tprel_lo(tl_4)
+; RV32I-MEDIUM-NEXT: lw a0, 0(a1)
; RV32I-MEDIUM-NEXT: lw a1, 4(a1)
; RV32I-MEDIUM-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll b/llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
index 77fe1783bb5d5..3db7444ccadba 100644
--- a/llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
+++ b/llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
@@ -30,8 +30,8 @@ define void @f1(i32 %a) nounwind {
; MINSIZE-LABEL: f1:
; MINSIZE: # %bb.0:
; MINSIZE-NEXT: lui a1, %hi(.L_MergedGlobals)
-; MINSIZE-NEXT: sw a0, %lo(.L_MergedGlobals)(a1)
; MINSIZE-NEXT: addi a1, a1, %lo(.L_MergedGlobals)
+; MINSIZE-NEXT: sw a0, 0(a1)
; MINSIZE-NEXT: sw a0, 4(a1)
; MINSIZE-NEXT: sw a0, 8(a1)
; MINSIZE-NEXT: sw a0, 12(a1)
diff --git a/llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll b/llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
index c29749c17a5b5..924f140aa207d 100644
--- a/llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
+++ b/llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
@@ -19,8 +19,8 @@ define void @f1(i32 %a) nounwind {
; SMALL-DATA-LABEL: f1:
; SMALL-DATA: # %bb.0:
; SMALL-DATA-NEXT: lui a1, %hi(.L_MergedGlobals)
-; SMALL-DATA-NEXT: sw a0, %lo(.L_MergedGlobals)(a1)
; SMALL-DATA-NEXT: addi a1, a1, %lo(.L_MergedGlobals)
+; SMALL-DATA-NEXT: sw a0, 0(a1)
; SMALL-DATA-NEXT: sw a0, 4(a1)
; SMALL-DATA-NEXT: sw a0, 8(a1)
; SMALL-DATA-NEXT: sw a0, 12(a1)
diff --git a/llvm/test/CodeGen/RISCV/global-merge-minsize.ll b/llvm/test/CodeGen/RISCV/global-merge-minsize.ll
index 915dde388cffd..ba567b6b21768 100644
--- a/llvm/test/CodeGen/RISCV/global-merge-minsize.ll
+++ b/llvm/test/CodeGen/RISCV/global-merge-minsize.ll
@@ -14,8 +14,8 @@ define void @f1(i32 %a) nounwind {
; RV32-LABEL: f1:
; RV32: # %bb.0:
; RV32-NEXT: lui a1, %hi(.L_MergedGlobals)
-; RV32-NEXT: sw a0, %lo(.L_MergedGlobals)(a1)
; RV32-NEXT: addi a1, a1, %lo(.L_MergedGlobals)
+; RV32-NEXT: sw a0, 0(a1)
; RV32-NEXT: sw a0, 4(a1)
; RV32-NEXT: sw a0, 8(a1)
; RV32-NEXT: sw a0, 12(a1)
diff --git a/llvm/test/CodeGen/RISCV/global-merge-offset.ll b/llvm/test/CodeGen/RISCV/global-merge-offset.ll
index c1074bc8ca97e..47001dbe53a8c 100644
--- a/llvm/test/CodeGen/RISCV/global-merge-offset.ll
+++ b/llvm/test/CodeGen/RISCV/global-merge-offset.ll
@@ -22,20 +22,20 @@ define void @f1(i32 %a) nounwind {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.L_MergedGlobals)
-; CHECK-NEXT: addi a2, a1, %lo(.L_MergedGlobals)
-; CHECK-NEXT: sw a0, 2044(a2)
-; CHECK-NEXT: sw a0, 404(a2)
-; CHECK-NEXT: sw a0, %lo(.L_MergedGlobals)(a1)
+; CHECK-NEXT: addi a1, a1, %lo(.L_MergedGlobals)
+; CHECK-NEXT: sw a0, 2044(a1)
+; CHECK-NEXT: sw a0, 404(a1)
+; CHECK-NEXT: sw a0, 0(a1)
; CHECK-NEXT: ret
;
; CHECK-TOOBIG-LABEL: f1:
; CHECK-TOOBIG: # %bb.0:
; CHECK-TOOBIG-NEXT: lui a1, %hi(ga1+1640)
; CHECK-TOOBIG-NEXT: lui a2, %hi(.L_MergedGlobals)
-; CHECK-TOOBIG-NEXT: addi a3, a2, %lo(.L_MergedGlobals)
+; CHECK-TOOBIG-NEXT: addi a2, a2, %lo(.L_MergedGlobals)
; CHECK-TOOBIG-NEXT: sw a0, %lo(ga1+1640)(a1)
-; CHECK-TOOBIG-NEXT: sw a0, 408(a3)
-; CHECK-TOOBIG-NEXT: sw a0, %lo(.L_MergedGlobals)(a2)
+; CHECK-TOOBIG-NEXT: sw a0, 408(a2)
+; CHECK-TOOBIG-NEXT: sw a0, 0(a2)
; CHECK-TOOBIG-NEXT: ret
%ga1_end = getelementptr inbounds [410 x i32], ptr @ga1, i32 0, i64 410
%ga2_end = getelementptr inbounds [ArrSize x i32], ptr @ga2, i32 0, i64 ArrSize
diff --git a/llvm/test/CodeGen/RISCV/global-merge.ll b/llvm/test/CodeGen/RISCV/global-merge.ll
index 31b3aa81b58dd..c2810fcff9d82 100644
--- a/llvm/test/CodeGen/RISCV/global-merge.ll
+++ b/llvm/test/CodeGen/RISCV/global-merge.ll
@@ -21,12 +21,12 @@
define void @f1(i32 %a) nounwind {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a1, %hi(eg1)
-; CHECK-NEXT: sw a0, %lo(eg1)(a1)
; CHECK-NEXT: lui a1, %hi(.L_MergedGlobals)
-; CHECK-NEXT: sw a0, %lo(.L_MergedGlobals)(a1)
; CHECK-NEXT: addi a1, a1, %lo(.L_MergedGlobals)
+; CHECK-NEXT: sw a0, 0(a1)
; CHECK-NEXT: sw a0, 4(a1)
+; CHECK-NEXT: lui a1, %hi(eg1)
+; CHECK-NEXT: sw a0, %lo(eg1)(a1)
; CHECK-NEXT: lui a1, %hi(eg2)
; CHECK-NEXT: sw a0, %lo(eg2)(a1)
; CHECK-NEXT: ret
@@ -34,8 +34,8 @@ define void @f1(i32 %a) nounwind {
; CHECK-WEXTERN-LABEL: f1:
; CHECK-WEXTERN: # %bb.0:
; CHECK-WEXTERN-NEXT: lui a1, %hi(.L_MergedGlobals)
-; CHECK-WEXTERN-NEXT: sw a0, %lo(.L_MergedGlobals)(a1)
; CHECK-WEXTERN-NEXT: addi a1, a1, %lo(.L_MergedGlobals)
+; CHECK-WEXTERN-NEXT: sw a0, 0(a1)
; CHECK-WEXTERN-NEXT: sw a0, 4(a1)
; CHECK-WEXTERN-NEXT: sw a0, 8(a1)
; CHECK-WEXTERN-NEXT: sw a0, 12(a1)
diff --git a/llvm/test/CodeGen/RISCV/half-mem.ll b/llvm/test/CodeGen/RISCV/half-mem.ll
index 9ac2a4d037f8a..5aa759036321d 100644
--- a/llvm/test/CodeGen/RISCV/half-mem.ll
+++ b/llvm/test/CodeGen/RISCV/half-mem.ll
@@ -112,22 +112,22 @@ define half @flh_fsh_global(half %a, half %b) nounwind {
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fadd.h fa0, fa0, fa1
; CHECKIZFH-NEXT: lui a0, %hi(G)
-; CHECKIZFH-NEXT: flh fa5, %lo(G)(a0)
-; CHECKIZFH-NEXT: addi a1, a0, %lo(G)
-; CHECKIZFH-NEXT: fsh fa0, %lo(G)(a0)
-; CHECKIZFH-NEXT: flh fa5, 18(a1)
-; CHECKIZFH-NEXT: fsh fa0, 18(a1)
+; CHECKIZFH-NEXT: addi a0, a0, %lo(G)
+; CHECKIZFH-NEXT: flh fa5, 0(a0)
+; CHECKIZFH-NEXT: fsh fa0, 0(a0)
+; CHECKIZFH-NEXT: flh fa5, 18(a0)
+; CHECKIZFH-NEXT: fsh fa0, 18(a0)
; CHECKIZFH-NEXT: ret
;
; CHECKIZHINX-LABEL: flh_fsh_global:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a0, a0, a1
; CHECKIZHINX-NEXT: lui a1, %hi(G)
-; CHECKIZHINX-NEXT: lh zero, %lo(G)(a1)
-; CHECKIZHINX-NEXT: addi a2, a1, %lo(G)
-; CHECKIZHINX-NEXT: sh a0, %lo(G)(a1)
-; CHECKIZHINX-NEXT: lh zero, 18(a2)
-; CHECKIZHINX-NEXT: sh a0, 18(a2)
+; CHECKIZHINX-NEXT: addi a1, a1, %lo(G)
+; CHECKIZHINX-NEXT: lh zero, 0(a1)
+; CHECKIZHINX-NEXT: sh a0, 0(a1)
+; CHECKIZHINX-NEXT: lh zero, 18(a1)
+; CHECKIZHINX-NEXT: sh a0, 18(a1)
; CHECKIZHINX-NEXT: ret
;
; CHECKIZFHMIN-LABEL: flh_fsh_global:
@@ -135,13 +135,13 @@ define half @flh_fsh_global(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
; CHECKIZFHMIN-NEXT: lui a0, %hi(G)
+; CHECKIZFHMIN-NEXT: addi a0, a0, %lo(G)
; CHECKIZFHMIN-NEXT: fadd.s fa5, fa4, fa5
-; CHECKIZFHMIN-NEXT: flh fa4, %lo(G)(a0)
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: addi a1, a0, %lo(G)
-; CHECKIZFHMIN-NEXT: fsh fa0, %lo(G)(a0)
-; CHECKIZFHMIN-NEXT: flh fa5, 18(a1)
-; CHECKIZFHMIN-NEXT: fsh fa0, 18(a1)
+; CHECKIZFHMIN-NEXT: flh fa5, 0(a0)
+; CHECKIZFHMIN-NEXT: fsh fa0, 0(a0)
+; CHECKIZFHMIN-NEXT: flh fa5, 18(a0)
+; CHECKIZFHMIN-NEXT: fsh fa0, 18(a0)
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: flh_fsh_global:
@@ -149,13 +149,13 @@ define half @flh_fsh_global(half %a, half %b) nounwind {
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECKIZHINXMIN-NEXT: lui a2, %hi(G)
+; CHECKIZHINXMIN-NEXT: addi a2, a2, %lo(G)
; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a1
-; CHECKIZHINXMIN-NEXT: lh zero, %lo(G)(a2)
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: addi a1, a2, %lo(G)
-; CHECKIZHINXMIN-NEXT: sh a0, %lo(G)(a2)
-; CHECKIZHINXMIN-NEXT: lh zero, 18(a1)
-; CHECKIZHINXMIN-NEXT: sh a0, 18(a1)
+; CHECKIZHINXMIN-NEXT: lh zero, 0(a2)
+; CHECKIZHINXMIN-NEXT: sh a0, 0(a2)
+; CHECKIZHINXMIN-NEXT: lh zero, 18(a2)
+; CHECKIZHINXMIN-NEXT: sh a0, 18(a2)
; CHECKIZHINXMIN-NEXT: ret
%1 = fadd half %a, %b
%2 = load volatile half, ptr @G
diff --git a/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll b/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
index 77efffb6358af..d9c2a8cff3123 100644
--- a/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
+++ b/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
@@ -306,8 +306,8 @@ define void @self_store() {
; RV32-LABEL: self_store:
; RV32: # %bb.0:
; RV32-NEXT: lui a0, %hi(f)
-; RV32-NEXT: addi a1, a0, %lo(f)
-; RV32-NEXT: sw a1, %lo(f+4)(a0)
+; RV32-NEXT: addi a0, a0, %lo(f)
+; RV32-NEXT: sw a0, 4(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: self_store:
diff --git a/llvm/test/CodeGen/RISCV/mem.ll b/llvm/test/CodeGen/RISCV/mem.ll
index a9cb80cb66349..d1c5cef6ac00b 100644
--- a/llvm/test/CodeGen/RISCV/mem.ll
+++ b/llvm/test/CodeGen/RISCV/mem.ll
@@ -169,11 +169,11 @@ define dso_local i32 @lw_sw_global(i32 %a) nounwind {
; RV32I-LABEL: lw_sw_global:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, %hi(G)
-; RV32I-NEXT: lw a1, %lo(G)(a2)
-; RV32I-NEXT: addi a3, a2, %lo(G)
-; RV32I-NEXT: sw a0, %lo(G)(a2)
-; RV32I-NEXT: lw zero, 36(a3)
-; RV32I-NEXT: sw a0, 36(a3)
+; RV32I-NEXT: addi a2, a2, %lo(G)
+; RV32I-NEXT: lw a1, 0(a2)
+; RV32I-NEXT: sw a0, 0(a2)
+; RV32I-NEXT: lw zero, 36(a2)
+; RV32I-NEXT: sw a0, 36(a2)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = load volatile i32, ptr @G
diff --git a/llvm/test/CodeGen/RISCV/mem64.ll b/llvm/test/CodeGen/RISCV/mem64.ll
index 248964146325a..df3834e254fd2 100644
--- a/llvm/test/CodeGen/RISCV/mem64.ll
+++ b/llvm/test/CodeGen/RISCV/mem64.ll
@@ -214,11 +214,11 @@ define dso_local i64 @ld_sd_global(i64 %a) nounwind {
; RV64I-LABEL: ld_sd_global:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, %hi(G)
-; RV64I-NEXT: ld a1, %lo(G)(a2)
-; RV64I-NEXT: addi a3, a2, %lo(G)
-; RV64I-NEXT: sd a0, %lo(G)(a2)
-; RV64I-NEXT: ld zero, 72(a3)
-; RV64I-NEXT: sd a0, 72(a3)
+; RV64I-NEXT: addi a2, a2, %lo(G)
+; RV64I-NEXT: ld a1, 0(a2)
+; RV64I-NEXT: sd a0, 0(a2)
+; RV64I-NEXT: ld zero, 72(a2)
+; RV64I-NEXT: sd a0, 72(a2)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
%1 = load volatile i64, ptr @G
diff --git a/llvm/test/CodeGen/RISCV/push-pop-popret.ll b/llvm/test/CodeGen/RISCV/push-pop-popret.ll
index 8f9c97de7b911..5e949f8969e3e 100644
--- a/llvm/test/CodeGen/RISCV/push-pop-popret.ll
+++ b/llvm/test/CodeGen/RISCV/push-pop-popret.ll
@@ -788,18 +788,17 @@ entry:
define i32 @nocompress(i32 signext %size) {
; RV32IZCMP-LABEL: nocompress:
; RV32IZCMP: # %bb.0: # %entry
-; RV32IZCMP-NEXT: cm.push {ra, s0-s8}, -48
+; RV32IZCMP-NEXT: cm.push {ra, s0-s7}, -48
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 48
-; RV32IZCMP-NEXT: .cfi_offset ra, -40
-; RV32IZCMP-NEXT: .cfi_offset s0, -36
-; RV32IZCMP-NEXT: .cfi_offset s1, -32
-; RV32IZCMP-NEXT: .cfi_offset s2, -28
-; RV32IZCMP-NEXT: .cfi_offset s3, -24
-; RV32IZCMP-NEXT: .cfi_offset s4, -20
-; RV32IZCMP-NEXT: .cfi_offset s5, -16
-; RV32IZCMP-NEXT: .cfi_offset s6, -12
-; RV32IZCMP-NEXT: .cfi_offset s7, -8
-; RV32IZCMP-NEXT: .cfi_offset s8, -4
+; RV32IZCMP-NEXT: .cfi_offset ra, -36
+; RV32IZCMP-NEXT: .cfi_offset s0, -32
+; RV32IZCMP-NEXT: .cfi_offset s1, -28
+; RV32IZCMP-NEXT: .cfi_offset s2, -24
+; RV32IZCMP-NEXT: .cfi_offset s3, -20
+; RV32IZCMP-NEXT: .cfi_offset s4, -16
+; RV32IZCMP-NEXT: .cfi_offset s5, -12
+; RV32IZCMP-NEXT: .cfi_offset s6, -8
+; RV32IZCMP-NEXT: .cfi_offset s7, -4
; RV32IZCMP-NEXT: addi s0, sp, 48
; RV32IZCMP-NEXT: .cfi_def_cfa s0, 0
; RV32IZCMP-NEXT: addi a0, a0, 15
@@ -807,23 +806,23 @@ define i32 @nocompress(i32 signext %size) {
; RV32IZCMP-NEXT: sub s2, sp, a0
; RV32IZCMP-NEXT: mv sp, s2
; RV32IZCMP-NEXT: lui s1, %hi(var)
-; RV32IZCMP-NEXT: lw s3, %lo(var)(s1)
-; RV32IZCMP-NEXT: lw s4, %lo(var+4)(s1)
-; RV32IZCMP-NEXT: lw s5, %lo(var+8)(s1)
-; RV32IZCMP-NEXT: lw s6, %lo(var+12)(s1)
-; RV32IZCMP-NEXT: addi s7, s1, %lo(var)
-; RV32IZCMP-NEXT: lw s8, 16(s7)
+; RV32IZCMP-NEXT: addi s1, s1, %lo(var)
+; RV32IZCMP-NEXT: lw s3, 0(s1)
+; RV32IZCMP-NEXT: lw s4, 4(s1)
+; RV32IZCMP-NEXT: lw s5, 8(s1)
+; RV32IZCMP-NEXT: lw s6, 12(s1)
+; RV32IZCMP-NEXT: lw s7, 16(s1)
; RV32IZCMP-NEXT: mv a0, s2
; RV32IZCMP-NEXT: call callee_void
-; RV32IZCMP-NEXT: sw s8, 16(s7)
-; RV32IZCMP-NEXT: sw s6, %lo(var+12)(s1)
-; RV32IZCMP-NEXT: sw s5, %lo(var+8)(s1)
-; RV32IZCMP-NEXT: sw s4, %lo(var+4)(s1)
-; RV32IZCMP-NEXT: sw s3, %lo(var)(s1)
+; RV32IZCMP-NEXT: sw s7, 16(s1)
+; RV32IZCMP-NEXT: sw s6, 12(s1)
+; RV32IZCMP-NEXT: sw s5, 8(s1)
+; RV32IZCMP-NEXT: sw s4, 4(s1)
+; RV32IZCMP-NEXT: sw s3, 0(s1)
; RV32IZCMP-NEXT: mv a0, s2
; RV32IZCMP-NEXT: addi sp, s0, -48
; RV32IZCMP-NEXT: .cfi_def_cfa sp, 48
-; RV32IZCMP-NEXT: cm.pop {ra, s0-s8}, 48
+; RV32IZCMP-NEXT: cm.pop {ra, s0-s7}, 48
; RV32IZCMP-NEXT: .cfi_restore ra
; RV32IZCMP-NEXT: .cfi_restore s0
; RV32IZCMP-NEXT: .cfi_restore s1
@@ -833,24 +832,22 @@ define i32 @nocompress(i32 signext %size) {
; RV32IZCMP-NEXT: .cfi_restore s5
; RV32IZCMP-NEXT: .cfi_restore s6
; RV32IZCMP-NEXT: .cfi_restore s7
-; RV32IZCMP-NEXT: .cfi_restore s8
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 0
; RV32IZCMP-NEXT: tail callee
;
; RV64IZCMP-LABEL: nocompress:
; RV64IZCMP: # %bb.0: # %entry
-; RV64IZCMP-NEXT: cm.push {ra, s0-s8}, -80
+; RV64IZCMP-NEXT: cm.push {ra, s0-s7}, -80
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 80
-; RV64IZCMP-NEXT: .cfi_offset ra, -80
-; RV64IZCMP-NEXT: .cfi_offset s0, -72
-; RV64IZCMP-NEXT: .cfi_offset s1, -64
-; RV64IZCMP-NEXT: .cfi_offset s2, -56
-; RV64IZCMP-NEXT: .cfi_offset s3, -48
-; RV64IZCMP-NEXT: .cfi_offset s4, -40
-; RV64IZCMP-NEXT: .cfi_offset s5, -32
-; RV64IZCMP-NEXT: .cfi_offset s6, -24
-; RV64IZCMP-NEXT: .cfi_offset s7, -16
-; RV64IZCMP-NEXT: .cfi_offset s8, -8
+; RV64IZCMP-NEXT: .cfi_offset ra, -72
+; RV64IZCMP-NEXT: .cfi_offset s0, -64
+; RV64IZCMP-NEXT: .cfi_offset s1, -56
+; RV64IZCMP-NEXT: .cfi_offset s2, -48
+; RV64IZCMP-NEXT: .cfi_offset s3, -40
+; RV64IZCMP-NEXT: .cfi_offset s4, -32
+; RV64IZCMP-NEXT: .cfi_offset s5, -24
+; RV64IZCMP-NEXT: .cfi_offset s6, -16
+; RV64IZCMP-NEXT: .cfi_offset s7, -8
; RV64IZCMP-NEXT: addi s0, sp, 80
; RV64IZCMP-NEXT: .cfi_def_cfa s0, 0
; RV64IZCMP-NEXT: slli a0, a0, 32
@@ -860,23 +857,23 @@ define i32 @nocompress(i32 signext %size) {
; RV64IZCMP-NEXT: sub s2, sp, a0
; RV64IZCMP-NEXT: mv sp, s2
; RV64IZCMP-NEXT: lui s1, %hi(var)
-; RV64IZCMP-NEXT: lw s3, %lo(var)(s1)
-; RV64IZCMP-NEXT: lw s4, %lo(var+4)(s1)
-; RV64IZCMP-NEXT: lw s5, %lo(var+8)(s1)
-; RV64IZCMP-NEXT: lw s6, %lo(var+12)(s1)
-; RV64IZCMP-NEXT: addi s7, s1, %lo(var)
-; RV64IZCMP-NEXT: lw s8, 16(s7)
+; RV64IZCMP-NEXT: addi s1, s1, %lo(var)
+; RV64IZCMP-NEXT: lw s3, 0(s1)
+; RV64IZCMP-NEXT: lw s4, 4(s1)
+; RV64IZCMP-NEXT: lw s5, 8(s1)
+; RV64IZCMP-NEXT: lw s6, 12(s1)
+; RV64IZCMP-NEXT: lw s7, 16(s1)
; RV64IZCMP-NEXT: mv a0, s2
; RV64IZCMP-NEXT: call callee_void
-; RV64IZCMP-NEXT: sw s8, 16(s7)
-; RV64IZCMP-NEXT: sw s6, %lo(var+12)(s1)
-; RV64IZCMP-NEXT: sw s5, %lo(var+8)(s1)
-; RV64IZCMP-NEXT: sw s4, %lo(var+4)(s1)
-; RV64IZCMP-NEXT: sw s3, %lo(var)(s1)
+; RV64IZCMP-NEXT: sw s7, 16(s1)
+; RV64IZCMP-NEXT: sw s6, 12(s1)
+; RV64IZCMP-NEXT: sw s5, 8(s1)
+; RV64IZCMP-NEXT: sw s4, 4(s1)
+; RV64IZCMP-NEXT: sw s3, 0(s1)
; RV64IZCMP-NEXT: mv a0, s2
; RV64IZCMP-NEXT: addi sp, s0, -80
; RV64IZCMP-NEXT: .cfi_def_cfa sp, 80
-; RV64IZCMP-NEXT: cm.pop {ra, s0-s8}, 80
+; RV64IZCMP-NEXT: cm.pop {ra, s0-s7}, 80
; RV64IZCMP-NEXT: .cfi_restore ra
; RV64IZCMP-NEXT: .cfi_restore s0
; RV64IZCMP-NEXT: .cfi_restore s1
@@ -886,24 +883,22 @@ define i32 @nocompress(i32 signext %size) {
; RV64IZCMP-NEXT: .cfi_restore s5
; RV64IZCMP-NEXT: .cfi_restore s6
; RV64IZCMP-NEXT: .cfi_restore s7
-; RV64IZCMP-NEXT: .cfi_restore s8
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 0
; RV64IZCMP-NEXT: tail callee
;
; RV32IZCMP-SR-LABEL: nocompress:
; RV32IZCMP-SR: # %bb.0: # %entry
-; RV32IZCMP-SR-NEXT: cm.push {ra, s0-s8}, -48
+; RV32IZCMP-SR-NEXT: cm.push {ra, s0-s7}, -48
; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 48
-; RV32IZCMP-SR-NEXT: .cfi_offset ra, -40
-; RV32IZCMP-SR-NEXT: .cfi_offset s0, -36
-; RV32IZCMP-SR-NEXT: .cfi_offset s1, -32
-; RV32IZCMP-SR-NEXT: .cfi_offset s2, -28
-; RV32IZCMP-SR-NEXT: .cfi_offset s3, -24
-; RV32IZCMP-SR-NEXT: .cfi_offset s4, -20
-; RV32IZCMP-SR-NEXT: .cfi_offset s5, -16
-; RV32IZCMP-SR-NEXT: .cfi_offset s6, -12
-; RV32IZCMP-SR-NEXT: .cfi_offset s7, -8
-; RV32IZCMP-SR-NEXT: .cfi_offset s8, -4
+; RV32IZCMP-SR-NEXT: .cfi_offset ra, -36
+; RV32IZCMP-SR-NEXT: .cfi_offset s0, -32
+; RV32IZCMP-SR-NEXT: .cfi_offset s1, -28
+; RV32IZCMP-SR-NEXT: .cfi_offset s2, -24
+; RV32IZCMP-SR-NEXT: .cfi_offset s3, -20
+; RV32IZCMP-SR-NEXT: .cfi_offset s4, -16
+; RV32IZCMP-SR-NEXT: .cfi_offset s5, -12
+; RV32IZCMP-SR-NEXT: .cfi_offset s6, -8
+; RV32IZCMP-SR-NEXT: .cfi_offset s7, -4
; RV32IZCMP-SR-NEXT: addi s0, sp, 48
; RV32IZCMP-SR-NEXT: .cfi_def_cfa s0, 0
; RV32IZCMP-SR-NEXT: addi a0, a0, 15
@@ -911,23 +906,23 @@ define i32 @nocompress(i32 signext %size) {
; RV32IZCMP-SR-NEXT: sub s2, sp, a0
; RV32IZCMP-SR-NEXT: mv sp, s2
; RV32IZCMP-SR-NEXT: lui s1, %hi(var)
-; RV32IZCMP-SR-NEXT: lw s3, %lo(var)(s1)
-; RV32IZCMP-SR-NEXT: lw s4, %lo(var+4)(s1)
-; RV32IZCMP-SR-NEXT: lw s5, %lo(var+8)(s1)
-; RV32IZCMP-SR-NEXT: lw s6, %lo(var+12)(s1)
-; RV32IZCMP-SR-NEXT: addi s7, s1, %lo(var)
-; RV32IZCMP-SR-NEXT: lw s8, 16(s7)
+; RV32IZCMP-SR-NEXT: addi s1, s1, %lo(var)
+; RV32IZCMP-SR-NEXT: lw s3, 0(s1)
+; RV32IZCMP-SR-NEXT: lw s4, 4(s1)
+; RV32IZCMP-SR-NEXT: lw s5, 8(s1)
+; RV32IZCMP-SR-NEXT: lw s6, 12(s1)
+; RV32IZCMP-SR-NEXT: lw s7, 16(s1)
; RV32IZCMP-SR-NEXT: mv a0, s2
; RV32IZCMP-SR-NEXT: call callee_void
-; RV32IZCMP-SR-NEXT: sw s8, 16(s7)
-; RV32IZCMP-SR-NEXT: sw s6, %lo(var+12)(s1)
-; RV32IZCMP-SR-NEXT: sw s5, %lo(var+8)(s1)
-; RV32IZCMP-SR-NEXT: sw s4, %lo(var+4)(s1)
-; RV32IZCMP-SR-NEXT: sw s3, %lo(var)(s1)
+; RV32IZCMP-SR-NEXT: sw s7, 16(s1)
+; RV32IZCMP-SR-NEXT: sw s6, 12(s1)
+; RV32IZCMP-SR-NEXT: sw s5, 8(s1)
+; RV32IZCMP-SR-NEXT: sw s4, 4(s1)
+; RV32IZCMP-SR-NEXT: sw s3, 0(s1)
; RV32IZCMP-SR-NEXT: mv a0, s2
; RV32IZCMP-SR-NEXT: addi sp, s0, -48
; RV32IZCMP-SR-NEXT: .cfi_def_cfa sp, 48
-; RV32IZCMP-SR-NEXT: cm.pop {ra, s0-s8}, 48
+; RV32IZCMP-SR-NEXT: cm.pop {ra, s0-s7}, 48
; RV32IZCMP-SR-NEXT: .cfi_restore ra
; RV32IZCMP-SR-NEXT: .cfi_restore s0
; RV32IZCMP-SR-NEXT: .cfi_restore s1
@@ -937,24 +932,22 @@ define i32 @nocompress(i32 signext %size) {
; RV32IZCMP-SR-NEXT: .cfi_restore s5
; RV32IZCMP-SR-NEXT: .cfi_restore s6
; RV32IZCMP-SR-NEXT: .cfi_restore s7
-; RV32IZCMP-SR-NEXT: .cfi_restore s8
; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 0
; RV32IZCMP-SR-NEXT: tail callee
;
; RV64IZCMP-SR-LABEL: nocompress:
; RV64IZCMP-SR: # %bb.0: # %entry
-; RV64IZCMP-SR-NEXT: cm.push {ra, s0-s8}, -80
+; RV64IZCMP-SR-NEXT: cm.push {ra, s0-s7}, -80
; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 80
-; RV64IZCMP-SR-NEXT: .cfi_offset ra, -80
-; RV64IZCMP-SR-NEXT: .cfi_offset s0, -72
-; RV64IZCMP-SR-NEXT: .cfi_offset s1, -64
-; RV64IZCMP-SR-NEXT: .cfi_offset s2, -56
-; RV64IZCMP-SR-NEXT: .cfi_offset s3, -48
-; RV64IZCMP-SR-NEXT: .cfi_offset s4, -40
-; RV64IZCMP-SR-NEXT: .cfi_offset s5, -32
-; RV64IZCMP-SR-NEXT: .cfi_offset s6, -24
-; RV64IZCMP-SR-NEXT: .cfi_offset s7, -16
-; RV64IZCMP-SR-NEXT: .cfi_offset s8, -8
+; RV64IZCMP-SR-NEXT: .cfi_offset ra, -72
+; RV64IZCMP-SR-NEXT: .cfi_offset s0, -64
+; RV64IZCMP-SR-NEXT: .cfi_offset s1, -56
+; RV64IZCMP-SR-NEXT: .cfi_offset s2, -48
+; RV64IZCMP-SR-NEXT: .cfi_offset s3, -40
+; RV64IZCMP-SR-NEXT: .cfi_offset s4, -32
+; RV64IZCMP-SR-NEXT: .cfi_offset s5, -24
+; RV64IZCMP-SR-NEXT: .cfi_offset s6, -16
+; RV64IZCMP-SR-NEXT: .cfi_offset s7, -8
; RV64IZCMP-SR-NEXT: addi s0, sp, 80
; RV64IZCMP-SR-NEXT: .cfi_def_cfa s0, 0
; RV64IZCMP-SR-NEXT: slli a0, a0, 32
@@ -964,23 +957,23 @@ define i32 @nocompress(i32 signext %size) {
; RV64IZCMP-SR-NEXT: sub s2, sp, a0
; RV64IZCMP-SR-NEXT: mv sp, s2
; RV64IZCMP-SR-NEXT: lui s1, %hi(var)
-; RV64IZCMP-SR-NEXT: lw s3, %lo(var)(s1)
-; RV64IZCMP-SR-NEXT: lw s4, %lo(var+4)(s1)
-; RV64IZCMP-SR-NEXT: lw s5, %lo(var+8)(s1)
-; RV64IZCMP-SR-NEXT: lw s6, %lo(var+12)(s1)
-; RV64IZCMP-SR-NEXT: addi s7, s1, %lo(var)
-; RV64IZCMP-SR-NEXT: lw s8, 16(s7)
+; RV64IZCMP-SR-NEXT: addi s1, s1, %lo(var)
+; RV64IZCMP-SR-NEXT: lw s3, 0(s1)
+; RV64IZCMP-SR-NEXT: lw s4, 4(s1)
+; RV64IZCMP-SR-NEXT: lw s5, 8(s1)
+; RV64IZCMP-SR-NEXT: lw s6, 12(s1)
+; RV64IZCMP-SR-NEXT: lw s7, 16(s1)
; RV64IZCMP-SR-NEXT: mv a0, s2
; RV64IZCMP-SR-NEXT: call callee_void
-; RV64IZCMP-SR-NEXT: sw s8, 16(s7)
-; RV64IZCMP-SR-NEXT: sw s6, %lo(var+12)(s1)
-; RV64IZCMP-SR-NEXT: sw s5, %lo(var+8)(s1)
-; RV64IZCMP-SR-NEXT: sw s4, %lo(var+4)(s1)
-; RV64IZCMP-SR-NEXT: sw s3, %lo(var)(s1)
+; RV64IZCMP-SR-NEXT: sw s7, 16(s1)
+; RV64IZCMP-SR-NEXT: sw s6, 12(s1)
+; RV64IZCMP-SR-NEXT: sw s5, 8(s1)
+; RV64IZCMP-SR-NEXT: sw s4, 4(s1)
+; RV64IZCMP-SR-NEXT: sw s3, 0(s1)
; RV64IZCMP-SR-NEXT: mv a0, s2
; RV64IZCMP-SR-NEXT: addi sp, s0, -80
; RV64IZCMP-SR-NEXT: .cfi_def_cfa sp, 80
-; RV64IZCMP-SR-NEXT: cm.pop {ra, s0-s8}, 80
+; RV64IZCMP-SR-NEXT: cm.pop {ra, s0-s7}, 80
; RV64IZCMP-SR-NEXT: .cfi_restore ra
; RV64IZCMP-SR-NEXT: .cfi_restore s0
; RV64IZCMP-SR-NEXT: .cfi_restore s1
@@ -990,7 +983,6 @@ define i32 @nocompress(i32 signext %size) {
; RV64IZCMP-SR-NEXT: .cfi_restore s5
; RV64IZCMP-SR-NEXT: .cfi_restore s6
; RV64IZCMP-SR-NEXT: .cfi_restore s7
-; RV64IZCMP-SR-NEXT: .cfi_restore s8
; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 0
; RV64IZCMP-SR-NEXT: tail callee
;
@@ -1007,7 +999,6 @@ define i32 @nocompress(i32 signext %size) {
; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
@@ -1017,7 +1008,6 @@ define i32 @nocompress(i32 signext %size) {
; RV32I-NEXT: .cfi_offset s5, -28
; RV32I-NEXT: .cfi_offset s6, -32
; RV32I-NEXT: .cfi_offset s7, -36
-; RV32I-NEXT: .cfi_offset s8, -40
; RV32I-NEXT: addi s0, sp, 48
; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: addi a0, a0, 15
@@ -1025,19 +1015,19 @@ define i32 @nocompress(i32 signext %size) {
; RV32I-NEXT: sub s1, sp, a0
; RV32I-NEXT: mv sp, s1
; RV32I-NEXT: lui s2, %hi(var)
-; RV32I-NEXT: lw s3, %lo(var)(s2)
-; RV32I-NEXT: lw s4, %lo(var+4)(s2)
-; RV32I-NEXT: lw s5, %lo(var+8)(s2)
-; RV32I-NEXT: lw s6, %lo(var+12)(s2)
-; RV32I-NEXT: addi s7, s2, %lo(var)
-; RV32I-NEXT: lw s8, 16(s7)
+; RV32I-NEXT: addi s2, s2, %lo(var)
+; RV32I-NEXT: lw s3, 0(s2)
+; RV32I-NEXT: lw s4, 4(s2)
+; RV32I-NEXT: lw s5, 8(s2)
+; RV32I-NEXT: lw s6, 12(s2)
+; RV32I-NEXT: lw s7, 16(s2)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call callee_void
-; RV32I-NEXT: sw s8, 16(s7)
-; RV32I-NEXT: sw s6, %lo(var+12)(s2)
-; RV32I-NEXT: sw s5, %lo(var+8)(s2)
-; RV32I-NEXT: sw s4, %lo(var+4)(s2)
-; RV32I-NEXT: sw s3, %lo(var)(s2)
+; RV32I-NEXT: sw s7, 16(s2)
+; RV32I-NEXT: sw s6, 12(s2)
+; RV32I-NEXT: sw s5, 8(s2)
+; RV32I-NEXT: sw s4, 4(s2)
+; RV32I-NEXT: sw s3, 0(s2)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: addi sp, s0, -48
; RV32I-NEXT: .cfi_def_cfa sp, 48
@@ -1050,7 +1040,6 @@ define i32 @nocompress(i32 signext %size) {
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
@@ -1060,7 +1049,6 @@ define i32 @nocompress(i32 signext %size) {
; RV32I-NEXT: .cfi_restore s5
; RV32I-NEXT: .cfi_restore s6
; RV32I-NEXT: .cfi_restore s7
-; RV32I-NEXT: .cfi_restore s8
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: tail callee
@@ -1078,7 +1066,6 @@ define i32 @nocompress(i32 signext %size) {
; RV64I-NEXT: sd s5, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s6, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s8, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
@@ -1088,7 +1075,6 @@ define i32 @nocompress(i32 signext %size) {
; RV64I-NEXT: .cfi_offset s5, -56
; RV64I-NEXT: .cfi_offset s6, -64
; RV64I-NEXT: .cfi_offset s7, -72
-; RV64I-NEXT: .cfi_offset s8, -80
; RV64I-NEXT: addi s0, sp, 80
; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: slli a0, a0, 32
@@ -1098,19 +1084,19 @@ define i32 @nocompress(i32 signext %size) {
; RV64I-NEXT: sub s1, sp, a0
; RV64I-NEXT: mv sp, s1
; RV64I-NEXT: lui s2, %hi(var)
-; RV64I-NEXT: lw s3, %lo(var)(s2)
-; RV64I-NEXT: lw s4, %lo(var+4)(s2)
-; RV64I-NEXT: lw s5, %lo(var+8)(s2)
-; RV64I-NEXT: lw s6, %lo(var+12)(s2)
-; RV64I-NEXT: addi s7, s2, %lo(var)
-; RV64I-NEXT: lw s8, 16(s7)
+; RV64I-NEXT: addi s2, s2, %lo(var)
+; RV64I-NEXT: lw s3, 0(s2)
+; RV64I-NEXT: lw s4, 4(s2)
+; RV64I-NEXT: lw s5, 8(s2)
+; RV64I-NEXT: lw s6, 12(s2)
+; RV64I-NEXT: lw s7, 16(s2)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call callee_void
-; RV64I-NEXT: sw s8, 16(s7)
-; RV64I-NEXT: sw s6, %lo(var+12)(s2)
-; RV64I-NEXT: sw s5, %lo(var+8)(s2)
-; RV64I-NEXT: sw s4, %lo(var+4)(s2)
-; RV64I-NEXT: sw s3, %lo(var)(s2)
+; RV64I-NEXT: sw s7, 16(s2)
+; RV64I-NEXT: sw s6, 12(s2)
+; RV64I-NEXT: sw s5, 8(s2)
+; RV64I-NEXT: sw s4, 4(s2)
+; RV64I-NEXT: sw s3, 0(s2)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: addi sp, s0, -80
; RV64I-NEXT: .cfi_def_cfa sp, 80
@@ -1123,7 +1109,6 @@ define i32 @nocompress(i32 signext %size) {
; RV64I-NEXT: ld s5, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s6, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s8, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
@@ -1133,7 +1118,6 @@ define i32 @nocompress(i32 signext %size) {
; RV64I-NEXT: .cfi_restore s5
; RV64I-NEXT: .cfi_restore s6
; RV64I-NEXT: .cfi_restore s7
-; RV64I-NEXT: .cfi_restore s8
; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: tail callee
@@ -1274,329 +1258,317 @@ define i32 @varargs(ptr %fmt, ...) {
define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV32IZCMP-LABEL: many_args:
; RV32IZCMP: # %bb.0: # %entry
-; RV32IZCMP-NEXT: cm.push {ra, s0-s4}, -32
+; RV32IZCMP-NEXT: cm.push {ra, s0-s3}, -32
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 32
-; RV32IZCMP-NEXT: .cfi_offset s0, -20
-; RV32IZCMP-NEXT: .cfi_offset s1, -16
-; RV32IZCMP-NEXT: .cfi_offset s2, -12
-; RV32IZCMP-NEXT: .cfi_offset s3, -8
-; RV32IZCMP-NEXT: .cfi_offset s4, -4
+; RV32IZCMP-NEXT: .cfi_offset s0, -16
+; RV32IZCMP-NEXT: .cfi_offset s1, -12
+; RV32IZCMP-NEXT: .cfi_offset s2, -8
+; RV32IZCMP-NEXT: .cfi_offset s3, -4
; RV32IZCMP-NEXT: lui a0, %hi(var0)
-; RV32IZCMP-NEXT: lw a6, %lo(var0)(a0)
-; RV32IZCMP-NEXT: lw a7, %lo(var0+4)(a0)
-; RV32IZCMP-NEXT: lw t0, %lo(var0+8)(a0)
-; RV32IZCMP-NEXT: lw t1, %lo(var0+12)(a0)
-; RV32IZCMP-NEXT: addi a5, a0, %lo(var0)
-; RV32IZCMP-NEXT: lw t2, 16(a5)
-; RV32IZCMP-NEXT: lw t3, 20(a5)
-; RV32IZCMP-NEXT: lw t4, 24(a5)
-; RV32IZCMP-NEXT: lw t5, 28(a5)
-; RV32IZCMP-NEXT: lw t6, 48(a5)
-; RV32IZCMP-NEXT: lw s2, 52(a5)
-; RV32IZCMP-NEXT: lw a3, 56(a5)
-; RV32IZCMP-NEXT: lw a4, 60(a5)
-; RV32IZCMP-NEXT: lw a1, 64(a5)
-; RV32IZCMP-NEXT: lw s0, 68(a5)
-; RV32IZCMP-NEXT: lw s3, 32(a5)
-; RV32IZCMP-NEXT: lw s4, 36(a5)
-; RV32IZCMP-NEXT: lw s1, 40(a5)
-; RV32IZCMP-NEXT: lw a2, 44(a5)
-; RV32IZCMP-NEXT: sw s0, 68(a5)
-; RV32IZCMP-NEXT: sw a1, 64(a5)
-; RV32IZCMP-NEXT: sw a4, 60(a5)
-; RV32IZCMP-NEXT: sw a3, 56(a5)
-; RV32IZCMP-NEXT: sw s2, 52(a5)
-; RV32IZCMP-NEXT: sw t6, 48(a5)
-; RV32IZCMP-NEXT: sw a2, 44(a5)
-; RV32IZCMP-NEXT: sw s1, 40(a5)
-; RV32IZCMP-NEXT: sw s4, 36(a5)
-; RV32IZCMP-NEXT: sw s3, 32(a5)
-; RV32IZCMP-NEXT: sw t5, 28(a5)
-; RV32IZCMP-NEXT: sw t4, 24(a5)
-; RV32IZCMP-NEXT: sw t3, 20(a5)
-; RV32IZCMP-NEXT: sw t2, 16(a5)
-; RV32IZCMP-NEXT: sw t1, %lo(var0+12)(a0)
-; RV32IZCMP-NEXT: sw t0, %lo(var0+8)(a0)
-; RV32IZCMP-NEXT: sw a7, %lo(var0+4)(a0)
-; RV32IZCMP-NEXT: sw a6, %lo(var0)(a0)
-; RV32IZCMP-NEXT: cm.popret {ra, s0-s4}, 32
+; RV32IZCMP-NEXT: addi a0, a0, %lo(var0)
+; RV32IZCMP-NEXT: lw a6, 0(a0)
+; RV32IZCMP-NEXT: lw a7, 4(a0)
+; RV32IZCMP-NEXT: lw t0, 8(a0)
+; RV32IZCMP-NEXT: lw t1, 12(a0)
+; RV32IZCMP-NEXT: lw t2, 16(a0)
+; RV32IZCMP-NEXT: lw t3, 20(a0)
+; RV32IZCMP-NEXT: lw t4, 24(a0)
+; RV32IZCMP-NEXT: lw t5, 28(a0)
+; RV32IZCMP-NEXT: lw t6, 48(a0)
+; RV32IZCMP-NEXT: lw s2, 52(a0)
+; RV32IZCMP-NEXT: lw a1, 56(a0)
+; RV32IZCMP-NEXT: lw a2, 60(a0)
+; RV32IZCMP-NEXT: lw a3, 64(a0)
+; RV32IZCMP-NEXT: lw a4, 68(a0)
+; RV32IZCMP-NEXT: lw s3, 32(a0)
+; RV32IZCMP-NEXT: lw s1, 36(a0)
+; RV32IZCMP-NEXT: lw a5, 40(a0)
+; RV32IZCMP-NEXT: lw s0, 44(a0)
+; RV32IZCMP-NEXT: sw a4, 68(a0)
+; RV32IZCMP-NEXT: sw a3, 64(a0)
+; RV32IZCMP-NEXT: sw a2, 60(a0)
+; RV32IZCMP-NEXT: sw a1, 56(a0)
+; RV32IZCMP-NEXT: sw s2, 52(a0)
+; RV32IZCMP-NEXT: sw t6, 48(a0)
+; RV32IZCMP-NEXT: sw s0, 44(a0)
+; RV32IZCMP-NEXT: sw a5, 40(a0)
+; RV32IZCMP-NEXT: sw s1, 36(a0)
+; RV32IZCMP-NEXT: sw s3, 32(a0)
+; RV32IZCMP-NEXT: sw t5, 28(a0)
+; RV32IZCMP-NEXT: sw t4, 24(a0)
+; RV32IZCMP-NEXT: sw t3, 20(a0)
+; RV32IZCMP-NEXT: sw t2, 16(a0)
+; RV32IZCMP-NEXT: sw t1, 12(a0)
+; RV32IZCMP-NEXT: sw t0, 8(a0)
+; RV32IZCMP-NEXT: sw a7, 4(a0)
+; RV32IZCMP-NEXT: sw a6, 0(a0)
+; RV32IZCMP-NEXT: cm.popret {ra, s0-s3}, 32
;
; RV64IZCMP-LABEL: many_args:
; RV64IZCMP: # %bb.0: # %entry
-; RV64IZCMP-NEXT: cm.push {ra, s0-s4}, -48
+; RV64IZCMP-NEXT: cm.push {ra, s0-s3}, -48
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 48
-; RV64IZCMP-NEXT: .cfi_offset s0, -40
-; RV64IZCMP-NEXT: .cfi_offset s1, -32
-; RV64IZCMP-NEXT: .cfi_offset s2, -24
-; RV64IZCMP-NEXT: .cfi_offset s3, -16
-; RV64IZCMP-NEXT: .cfi_offset s4, -8
+; RV64IZCMP-NEXT: .cfi_offset s0, -32
+; RV64IZCMP-NEXT: .cfi_offset s1, -24
+; RV64IZCMP-NEXT: .cfi_offset s2, -16
+; RV64IZCMP-NEXT: .cfi_offset s3, -8
; RV64IZCMP-NEXT: lui a0, %hi(var0)
-; RV64IZCMP-NEXT: lw a6, %lo(var0)(a0)
-; RV64IZCMP-NEXT: lw a7, %lo(var0+4)(a0)
-; RV64IZCMP-NEXT: lw t0, %lo(var0+8)(a0)
-; RV64IZCMP-NEXT: lw t1, %lo(var0+12)(a0)
-; RV64IZCMP-NEXT: addi a5, a0, %lo(var0)
-; RV64IZCMP-NEXT: lw t2, 16(a5)
-; RV64IZCMP-NEXT: lw t3, 20(a5)
-; RV64IZCMP-NEXT: lw t4, 24(a5)
-; RV64IZCMP-NEXT: lw t5, 28(a5)
-; RV64IZCMP-NEXT: lw t6, 48(a5)
-; RV64IZCMP-NEXT: lw s2, 52(a5)
-; RV64IZCMP-NEXT: lw a3, 56(a5)
-; RV64IZCMP-NEXT: lw a4, 60(a5)
-; RV64IZCMP-NEXT: lw a1, 64(a5)
-; RV64IZCMP-NEXT: lw s0, 68(a5)
-; RV64IZCMP-NEXT: lw s3, 32(a5)
-; RV64IZCMP-NEXT: lw s4, 36(a5)
-; RV64IZCMP-NEXT: lw s1, 40(a5)
-; RV64IZCMP-NEXT: lw a2, 44(a5)
-; RV64IZCMP-NEXT: sw s0, 68(a5)
-; RV64IZCMP-NEXT: sw a1, 64(a5)
-; RV64IZCMP-NEXT: sw a4, 60(a5)
-; RV64IZCMP-NEXT: sw a3, 56(a5)
-; RV64IZCMP-NEXT: sw s2, 52(a5)
-; RV64IZCMP-NEXT: sw t6, 48(a5)
-; RV64IZCMP-NEXT: sw a2, 44(a5)
-; RV64IZCMP-NEXT: sw s1, 40(a5)
-; RV64IZCMP-NEXT: sw s4, 36(a5)
-; RV64IZCMP-NEXT: sw s3, 32(a5)
-; RV64IZCMP-NEXT: sw t5, 28(a5)
-; RV64IZCMP-NEXT: sw t4, 24(a5)
-; RV64IZCMP-NEXT: sw t3, 20(a5)
-; RV64IZCMP-NEXT: sw t2, 16(a5)
-; RV64IZCMP-NEXT: sw t1, %lo(var0+12)(a0)
-; RV64IZCMP-NEXT: sw t0, %lo(var0+8)(a0)
-; RV64IZCMP-NEXT: sw a7, %lo(var0+4)(a0)
-; RV64IZCMP-NEXT: sw a6, %lo(var0)(a0)
-; RV64IZCMP-NEXT: cm.popret {ra, s0-s4}, 48
+; RV64IZCMP-NEXT: addi a0, a0, %lo(var0)
+; RV64IZCMP-NEXT: lw a6, 0(a0)
+; RV64IZCMP-NEXT: lw a7, 4(a0)
+; RV64IZCMP-NEXT: lw t0, 8(a0)
+; RV64IZCMP-NEXT: lw t1, 12(a0)
+; RV64IZCMP-NEXT: lw t2, 16(a0)
+; RV64IZCMP-NEXT: lw t3, 20(a0)
+; RV64IZCMP-NEXT: lw t4, 24(a0)
+; RV64IZCMP-NEXT: lw t5, 28(a0)
+; RV64IZCMP-NEXT: lw t6, 48(a0)
+; RV64IZCMP-NEXT: lw s2, 52(a0)
+; RV64IZCMP-NEXT: lw a1, 56(a0)
+; RV64IZCMP-NEXT: lw a2, 60(a0)
+; RV64IZCMP-NEXT: lw a3, 64(a0)
+; RV64IZCMP-NEXT: lw a4, 68(a0)
+; RV64IZCMP-NEXT: lw s3, 32(a0)
+; RV64IZCMP-NEXT: lw s1, 36(a0)
+; RV64IZCMP-NEXT: lw a5, 40(a0)
+; RV64IZCMP-NEXT: lw s0, 44(a0)
+; RV64IZCMP-NEXT: sw a4, 68(a0)
+; RV64IZCMP-NEXT: sw a3, 64(a0)
+; RV64IZCMP-NEXT: sw a2, 60(a0)
+; RV64IZCMP-NEXT: sw a1, 56(a0)
+; RV64IZCMP-NEXT: sw s2, 52(a0)
+; RV64IZCMP-NEXT: sw t6, 48(a0)
+; RV64IZCMP-NEXT: sw s0, 44(a0)
+; RV64IZCMP-NEXT: sw a5, 40(a0)
+; RV64IZCMP-NEXT: sw s1, 36(a0)
+; RV64IZCMP-NEXT: sw s3, 32(a0)
+; RV64IZCMP-NEXT: sw t5, 28(a0)
+; RV64IZCMP-NEXT: sw t4, 24(a0)
+; RV64IZCMP-NEXT: sw t3, 20(a0)
+; RV64IZCMP-NEXT: sw t2, 16(a0)
+; RV64IZCMP-NEXT: sw t1, 12(a0)
+; RV64IZCMP-NEXT: sw t0, 8(a0)
+; RV64IZCMP-NEXT: sw a7, 4(a0)
+; RV64IZCMP-NEXT: sw a6, 0(a0)
+; RV64IZCMP-NEXT: cm.popret {ra, s0-s3}, 48
;
; RV32IZCMP-SR-LABEL: many_args:
; RV32IZCMP-SR: # %bb.0: # %entry
-; RV32IZCMP-SR-NEXT: cm.push {ra, s0-s4}, -32
+; RV32IZCMP-SR-NEXT: cm.push {ra, s0-s3}, -32
; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 32
-; RV32IZCMP-SR-NEXT: .cfi_offset s0, -20
-; RV32IZCMP-SR-NEXT: .cfi_offset s1, -16
-; RV32IZCMP-SR-NEXT: .cfi_offset s2, -12
-; RV32IZCMP-SR-NEXT: .cfi_offset s3, -8
-; RV32IZCMP-SR-NEXT: .cfi_offset s4, -4
+; RV32IZCMP-SR-NEXT: .cfi_offset s0, -16
+; RV32IZCMP-SR-NEXT: .cfi_offset s1, -12
+; RV32IZCMP-SR-NEXT: .cfi_offset s2, -8
+; RV32IZCMP-SR-NEXT: .cfi_offset s3, -4
; RV32IZCMP-SR-NEXT: lui a0, %hi(var0)
-; RV32IZCMP-SR-NEXT: lw a6, %lo(var0)(a0)
-; RV32IZCMP-SR-NEXT: lw a7, %lo(var0+4)(a0)
-; RV32IZCMP-SR-NEXT: lw t0, %lo(var0+8)(a0)
-; RV32IZCMP-SR-NEXT: lw t1, %lo(var0+12)(a0)
-; RV32IZCMP-SR-NEXT: addi a5, a0, %lo(var0)
-; RV32IZCMP-SR-NEXT: lw t2, 16(a5)
-; RV32IZCMP-SR-NEXT: lw t3, 20(a5)
-; RV32IZCMP-SR-NEXT: lw t4, 24(a5)
-; RV32IZCMP-SR-NEXT: lw t5, 28(a5)
-; RV32IZCMP-SR-NEXT: lw t6, 48(a5)
-; RV32IZCMP-SR-NEXT: lw s2, 52(a5)
-; RV32IZCMP-SR-NEXT: lw a3, 56(a5)
-; RV32IZCMP-SR-NEXT: lw a4, 60(a5)
-; RV32IZCMP-SR-NEXT: lw a1, 64(a5)
-; RV32IZCMP-SR-NEXT: lw s0, 68(a5)
-; RV32IZCMP-SR-NEXT: lw s3, 32(a5)
-; RV32IZCMP-SR-NEXT: lw s4, 36(a5)
-; RV32IZCMP-SR-NEXT: lw s1, 40(a5)
-; RV32IZCMP-SR-NEXT: lw a2, 44(a5)
-; RV32IZCMP-SR-NEXT: sw s0, 68(a5)
-; RV32IZCMP-SR-NEXT: sw a1, 64(a5)
-; RV32IZCMP-SR-NEXT: sw a4, 60(a5)
-; RV32IZCMP-SR-NEXT: sw a3, 56(a5)
-; RV32IZCMP-SR-NEXT: sw s2, 52(a5)
-; RV32IZCMP-SR-NEXT: sw t6, 48(a5)
-; RV32IZCMP-SR-NEXT: sw a2, 44(a5)
-; RV32IZCMP-SR-NEXT: sw s1, 40(a5)
-; RV32IZCMP-SR-NEXT: sw s4, 36(a5)
-; RV32IZCMP-SR-NEXT: sw s3, 32(a5)
-; RV32IZCMP-SR-NEXT: sw t5, 28(a5)
-; RV32IZCMP-SR-NEXT: sw t4, 24(a5)
-; RV32IZCMP-SR-NEXT: sw t3, 20(a5)
-; RV32IZCMP-SR-NEXT: sw t2, 16(a5)
-; RV32IZCMP-SR-NEXT: sw t1, %lo(var0+12)(a0)
-; RV32IZCMP-SR-NEXT: sw t0, %lo(var0+8)(a0)
-; RV32IZCMP-SR-NEXT: sw a7, %lo(var0+4)(a0)
-; RV32IZCMP-SR-NEXT: sw a6, %lo(var0)(a0)
-; RV32IZCMP-SR-NEXT: cm.popret {ra, s0-s4}, 32
+; RV32IZCMP-SR-NEXT: addi a0, a0, %lo(var0)
+; RV32IZCMP-SR-NEXT: lw a6, 0(a0)
+; RV32IZCMP-SR-NEXT: lw a7, 4(a0)
+; RV32IZCMP-SR-NEXT: lw t0, 8(a0)
+; RV32IZCMP-SR-NEXT: lw t1, 12(a0)
+; RV32IZCMP-SR-NEXT: lw t2, 16(a0)
+; RV32IZCMP-SR-NEXT: lw t3, 20(a0)
+; RV32IZCMP-SR-NEXT: lw t4, 24(a0)
+; RV32IZCMP-SR-NEXT: lw t5, 28(a0)
+; RV32IZCMP-SR-NEXT: lw t6, 48(a0)
+; RV32IZCMP-SR-NEXT: lw s2, 52(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 56(a0)
+; RV32IZCMP-SR-NEXT: lw a2, 60(a0)
+; RV32IZCMP-SR-NEXT: lw a3, 64(a0)
+; RV32IZCMP-SR-NEXT: lw a4, 68(a0)
+; RV32IZCMP-SR-NEXT: lw s3, 32(a0)
+; RV32IZCMP-SR-NEXT: lw s1, 36(a0)
+; RV32IZCMP-SR-NEXT: lw a5, 40(a0)
+; RV32IZCMP-SR-NEXT: lw s0, 44(a0)
+; RV32IZCMP-SR-NEXT: sw a4, 68(a0)
+; RV32IZCMP-SR-NEXT: sw a3, 64(a0)
+; RV32IZCMP-SR-NEXT: sw a2, 60(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 56(a0)
+; RV32IZCMP-SR-NEXT: sw s2, 52(a0)
+; RV32IZCMP-SR-NEXT: sw t6, 48(a0)
+; RV32IZCMP-SR-NEXT: sw s0, 44(a0)
+; RV32IZCMP-SR-NEXT: sw a5, 40(a0)
+; RV32IZCMP-SR-NEXT: sw s1, 36(a0)
+; RV32IZCMP-SR-NEXT: sw s3, 32(a0)
+; RV32IZCMP-SR-NEXT: sw t5, 28(a0)
+; RV32IZCMP-SR-NEXT: sw t4, 24(a0)
+; RV32IZCMP-SR-NEXT: sw t3, 20(a0)
+; RV32IZCMP-SR-NEXT: sw t2, 16(a0)
+; RV32IZCMP-SR-NEXT: sw t1, 12(a0)
+; RV32IZCMP-SR-NEXT: sw t0, 8(a0)
+; RV32IZCMP-SR-NEXT: sw a7, 4(a0)
+; RV32IZCMP-SR-NEXT: sw a6, 0(a0)
+; RV32IZCMP-SR-NEXT: cm.popret {ra, s0-s3}, 32
;
; RV64IZCMP-SR-LABEL: many_args:
; RV64IZCMP-SR: # %bb.0: # %entry
-; RV64IZCMP-SR-NEXT: cm.push {ra, s0-s4}, -48
+; RV64IZCMP-SR-NEXT: cm.push {ra, s0-s3}, -48
; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 48
-; RV64IZCMP-SR-NEXT: .cfi_offset s0, -40
-; RV64IZCMP-SR-NEXT: .cfi_offset s1, -32
-; RV64IZCMP-SR-NEXT: .cfi_offset s2, -24
-; RV64IZCMP-SR-NEXT: .cfi_offset s3, -16
-; RV64IZCMP-SR-NEXT: .cfi_offset s4, -8
+; RV64IZCMP-SR-NEXT: .cfi_offset s0, -32
+; RV64IZCMP-SR-NEXT: .cfi_offset s1, -24
+; RV64IZCMP-SR-NEXT: .cfi_offset s2, -16
+; RV64IZCMP-SR-NEXT: .cfi_offset s3, -8
; RV64IZCMP-SR-NEXT: lui a0, %hi(var0)
-; RV64IZCMP-SR-NEXT: lw a6, %lo(var0)(a0)
-; RV64IZCMP-SR-NEXT: lw a7, %lo(var0+4)(a0)
-; RV64IZCMP-SR-NEXT: lw t0, %lo(var0+8)(a0)
-; RV64IZCMP-SR-NEXT: lw t1, %lo(var0+12)(a0)
-; RV64IZCMP-SR-NEXT: addi a5, a0, %lo(var0)
-; RV64IZCMP-SR-NEXT: lw t2, 16(a5)
-; RV64IZCMP-SR-NEXT: lw t3, 20(a5)
-; RV64IZCMP-SR-NEXT: lw t4, 24(a5)
-; RV64IZCMP-SR-NEXT: lw t5, 28(a5)
-; RV64IZCMP-SR-NEXT: lw t6, 48(a5)
-; RV64IZCMP-SR-NEXT: lw s2, 52(a5)
-; RV64IZCMP-SR-NEXT: lw a3, 56(a5)
-; RV64IZCMP-SR-NEXT: lw a4, 60(a5)
-; RV64IZCMP-SR-NEXT: lw a1, 64(a5)
-; RV64IZCMP-SR-NEXT: lw s0, 68(a5)
-; RV64IZCMP-SR-NEXT: lw s3, 32(a5)
-; RV64IZCMP-SR-NEXT: lw s4, 36(a5)
-; RV64IZCMP-SR-NEXT: lw s1, 40(a5)
-; RV64IZCMP-SR-NEXT: lw a2, 44(a5)
-; RV64IZCMP-SR-NEXT: sw s0, 68(a5)
-; RV64IZCMP-SR-NEXT: sw a1, 64(a5)
-; RV64IZCMP-SR-NEXT: sw a4, 60(a5)
-; RV64IZCMP-SR-NEXT: sw a3, 56(a5)
-; RV64IZCMP-SR-NEXT: sw s2, 52(a5)
-; RV64IZCMP-SR-NEXT: sw t6, 48(a5)
-; RV64IZCMP-SR-NEXT: sw a2, 44(a5)
-; RV64IZCMP-SR-NEXT: sw s1, 40(a5)
-; RV64IZCMP-SR-NEXT: sw s4, 36(a5)
-; RV64IZCMP-SR-NEXT: sw s3, 32(a5)
-; RV64IZCMP-SR-NEXT: sw t5, 28(a5)
-; RV64IZCMP-SR-NEXT: sw t4, 24(a5)
-; RV64IZCMP-SR-NEXT: sw t3, 20(a5)
-; RV64IZCMP-SR-NEXT: sw t2, 16(a5)
-; RV64IZCMP-SR-NEXT: sw t1, %lo(var0+12)(a0)
-; RV64IZCMP-SR-NEXT: sw t0, %lo(var0+8)(a0)
-; RV64IZCMP-SR-NEXT: sw a7, %lo(var0+4)(a0)
-; RV64IZCMP-SR-NEXT: sw a6, %lo(var0)(a0)
-; RV64IZCMP-SR-NEXT: cm.popret {ra, s0-s4}, 48
+; RV64IZCMP-SR-NEXT: addi a0, a0, %lo(var0)
+; RV64IZCMP-SR-NEXT: lw a6, 0(a0)
+; RV64IZCMP-SR-NEXT: lw a7, 4(a0)
+; RV64IZCMP-SR-NEXT: lw t0, 8(a0)
+; RV64IZCMP-SR-NEXT: lw t1, 12(a0)
+; RV64IZCMP-SR-NEXT: lw t2, 16(a0)
+; RV64IZCMP-SR-NEXT: lw t3, 20(a0)
+; RV64IZCMP-SR-NEXT: lw t4, 24(a0)
+; RV64IZCMP-SR-NEXT: lw t5, 28(a0)
+; RV64IZCMP-SR-NEXT: lw t6, 48(a0)
+; RV64IZCMP-SR-NEXT: lw s2, 52(a0)
+; RV64IZCMP-SR-NEXT: lw a1, 56(a0)
+; RV64IZCMP-SR-NEXT: lw a2, 60(a0)
+; RV64IZCMP-SR-NEXT: lw a3, 64(a0)
+; RV64IZCMP-SR-NEXT: lw a4, 68(a0)
+; RV64IZCMP-SR-NEXT: lw s3, 32(a0)
+; RV64IZCMP-SR-NEXT: lw s1, 36(a0)
+; RV64IZCMP-SR-NEXT: lw a5, 40(a0)
+; RV64IZCMP-SR-NEXT: lw s0, 44(a0)
+; RV64IZCMP-SR-NEXT: sw a4, 68(a0)
+; RV64IZCMP-SR-NEXT: sw a3, 64(a0)
+; RV64IZCMP-SR-NEXT: sw a2, 60(a0)
+; RV64IZCMP-SR-NEXT: sw a1, 56(a0)
+; RV64IZCMP-SR-NEXT: sw s2, 52(a0)
+; RV64IZCMP-SR-NEXT: sw t6, 48(a0)
+; RV64IZCMP-SR-NEXT: sw s0, 44(a0)
+; RV64IZCMP-SR-NEXT: sw a5, 40(a0)
+; RV64IZCMP-SR-NEXT: sw s1, 36(a0)
+; RV64IZCMP-SR-NEXT: sw s3, 32(a0)
+; RV64IZCMP-SR-NEXT: sw t5, 28(a0)
+; RV64IZCMP-SR-NEXT: sw t4, 24(a0)
+; RV64IZCMP-SR-NEXT: sw t3, 20(a0)
+; RV64IZCMP-SR-NEXT: sw t2, 16(a0)
+; RV64IZCMP-SR-NEXT: sw t1, 12(a0)
+; RV64IZCMP-SR-NEXT: sw t0, 8(a0)
+; RV64IZCMP-SR-NEXT: sw a7, 4(a0)
+; RV64IZCMP-SR-NEXT: sw a6, 0(a0)
+; RV64IZCMP-SR-NEXT: cm.popret {ra, s0-s3}, 48
;
; RV32I-LABEL: many_args:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: .cfi_def_cfa_offset 32
-; RV32I-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset s0, -4
; RV32I-NEXT: .cfi_offset s1, -8
; RV32I-NEXT: .cfi_offset s2, -12
; RV32I-NEXT: .cfi_offset s3, -16
-; RV32I-NEXT: .cfi_offset s4, -20
; RV32I-NEXT: lui a0, %hi(var0)
-; RV32I-NEXT: lw a1, %lo(var0)(a0)
-; RV32I-NEXT: lw a2, %lo(var0+4)(a0)
-; RV32I-NEXT: lw a3, %lo(var0+8)(a0)
-; RV32I-NEXT: lw a4, %lo(var0+12)(a0)
-; RV32I-NEXT: addi a5, a0, %lo(var0)
-; RV32I-NEXT: lw a6, 16(a5)
-; RV32I-NEXT: lw a7, 20(a5)
-; RV32I-NEXT: lw t0, 24(a5)
-; RV32I-NEXT: lw t1, 28(a5)
-; RV32I-NEXT: lw t2, 48(a5)
-; RV32I-NEXT: lw t3, 52(a5)
-; RV32I-NEXT: lw t4, 56(a5)
-; RV32I-NEXT: lw t5, 60(a5)
-; RV32I-NEXT: lw t6, 64(a5)
-; RV32I-NEXT: lw s0, 68(a5)
-; RV32I-NEXT: lw s1, 32(a5)
-; RV32I-NEXT: lw s2, 36(a5)
-; RV32I-NEXT: lw s3, 40(a5)
-; RV32I-NEXT: lw s4, 44(a5)
-; RV32I-NEXT: sw s0, 68(a5)
-; RV32I-NEXT: sw t6, 64(a5)
-; RV32I-NEXT: sw t5, 60(a5)
-; RV32I-NEXT: sw t4, 56(a5)
-; RV32I-NEXT: sw t3, 52(a5)
-; RV32I-NEXT: sw t2, 48(a5)
-; RV32I-NEXT: sw s4, 44(a5)
-; RV32I-NEXT: sw s3, 40(a5)
-; RV32I-NEXT: sw s2, 36(a5)
-; RV32I-NEXT: sw s1, 32(a5)
-; RV32I-NEXT: sw t1, 28(a5)
-; RV32I-NEXT: sw t0, 24(a5)
-; RV32I-NEXT: sw a7, 20(a5)
-; RV32I-NEXT: sw a6, 16(a5)
-; RV32I-NEXT: sw a4, %lo(var0+12)(a0)
-; RV32I-NEXT: sw a3, %lo(var0+8)(a0)
-; RV32I-NEXT: sw a2, %lo(var0+4)(a0)
-; RV32I-NEXT: sw a1, %lo(var0)(a0)
-; RV32I-NEXT: lw s0, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi a0, a0, %lo(var0)
+; RV32I-NEXT: lw a1, 0(a0)
+; RV32I-NEXT: lw a2, 4(a0)
+; RV32I-NEXT: lw a3, 8(a0)
+; RV32I-NEXT: lw a4, 12(a0)
+; RV32I-NEXT: lw a5, 16(a0)
+; RV32I-NEXT: lw a6, 20(a0)
+; RV32I-NEXT: lw a7, 24(a0)
+; RV32I-NEXT: lw t0, 28(a0)
+; RV32I-NEXT: lw t1, 48(a0)
+; RV32I-NEXT: lw t2, 52(a0)
+; RV32I-NEXT: lw t3, 56(a0)
+; RV32I-NEXT: lw t4, 60(a0)
+; RV32I-NEXT: lw t5, 64(a0)
+; RV32I-NEXT: lw t6, 68(a0)
+; RV32I-NEXT: lw s0, 32(a0)
+; RV32I-NEXT: lw s1, 36(a0)
+; RV32I-NEXT: lw s2, 40(a0)
+; RV32I-NEXT: lw s3, 44(a0)
+; RV32I-NEXT: sw t6, 68(a0)
+; RV32I-NEXT: sw t5, 64(a0)
+; RV32I-NEXT: sw t4, 60(a0)
+; RV32I-NEXT: sw t3, 56(a0)
+; RV32I-NEXT: sw t2, 52(a0)
+; RV32I-NEXT: sw t1, 48(a0)
+; RV32I-NEXT: sw s3, 44(a0)
+; RV32I-NEXT: sw s2, 40(a0)
+; RV32I-NEXT: sw s1, 36(a0)
+; RV32I-NEXT: sw s0, 32(a0)
+; RV32I-NEXT: sw t0, 28(a0)
+; RV32I-NEXT: sw a7, 24(a0)
+; RV32I-NEXT: sw a6, 20(a0)
+; RV32I-NEXT: sw a5, 16(a0)
+; RV32I-NEXT: sw a4, 12(a0)
+; RV32I-NEXT: sw a3, 8(a0)
+; RV32I-NEXT: sw a2, 4(a0)
+; RV32I-NEXT: sw a1, 0(a0)
+; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
-; RV32I-NEXT: .cfi_restore s4
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: many_args:
; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: .cfi_def_cfa_offset 48
-; RV64I-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s4, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: .cfi_def_cfa_offset 32
+; RV64I-NEXT: sd s0, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset s0, -8
; RV64I-NEXT: .cfi_offset s1, -16
; RV64I-NEXT: .cfi_offset s2, -24
; RV64I-NEXT: .cfi_offset s3, -32
-; RV64I-NEXT: .cfi_offset s4, -40
; RV64I-NEXT: lui a0, %hi(var0)
-; RV64I-NEXT: lw a1, %lo(var0)(a0)
-; RV64I-NEXT: lw a2, %lo(var0+4)(a0)
-; RV64I-NEXT: lw a3, %lo(var0+8)(a0)
-; RV64I-NEXT: lw a4, %lo(var0+12)(a0)
-; RV64I-NEXT: addi a5, a0, %lo(var0)
-; RV64I-NEXT: lw a6, 16(a5)
-; RV64I-NEXT: lw a7, 20(a5)
-; RV64I-NEXT: lw t0, 24(a5)
-; RV64I-NEXT: lw t1, 28(a5)
-; RV64I-NEXT: lw t2, 48(a5)
-; RV64I-NEXT: lw t3, 52(a5)
-; RV64I-NEXT: lw t4, 56(a5)
-; RV64I-NEXT: lw t5, 60(a5)
-; RV64I-NEXT: lw t6, 64(a5)
-; RV64I-NEXT: lw s0, 68(a5)
-; RV64I-NEXT: lw s1, 32(a5)
-; RV64I-NEXT: lw s2, 36(a5)
-; RV64I-NEXT: lw s3, 40(a5)
-; RV64I-NEXT: lw s4, 44(a5)
-; RV64I-NEXT: sw s0, 68(a5)
-; RV64I-NEXT: sw t6, 64(a5)
-; RV64I-NEXT: sw t5, 60(a5)
-; RV64I-NEXT: sw t4, 56(a5)
-; RV64I-NEXT: sw t3, 52(a5)
-; RV64I-NEXT: sw t2, 48(a5)
-; RV64I-NEXT: sw s4, 44(a5)
-; RV64I-NEXT: sw s3, 40(a5)
-; RV64I-NEXT: sw s2, 36(a5)
-; RV64I-NEXT: sw s1, 32(a5)
-; RV64I-NEXT: sw t1, 28(a5)
-; RV64I-NEXT: sw t0, 24(a5)
-; RV64I-NEXT: sw a7, 20(a5)
-; RV64I-NEXT: sw a6, 16(a5)
-; RV64I-NEXT: sw a4, %lo(var0+12)(a0)
-; RV64I-NEXT: sw a3, %lo(var0+8)(a0)
-; RV64I-NEXT: sw a2, %lo(var0+4)(a0)
-; RV64I-NEXT: sw a1, %lo(var0)(a0)
-; RV64I-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi a0, a0, %lo(var0)
+; RV64I-NEXT: lw a1, 0(a0)
+; RV64I-NEXT: lw a2, 4(a0)
+; RV64I-NEXT: lw a3, 8(a0)
+; RV64I-NEXT: lw a4, 12(a0)
+; RV64I-NEXT: lw a5, 16(a0)
+; RV64I-NEXT: lw a6, 20(a0)
+; RV64I-NEXT: lw a7, 24(a0)
+; RV64I-NEXT: lw t0, 28(a0)
+; RV64I-NEXT: lw t1, 48(a0)
+; RV64I-NEXT: lw t2, 52(a0)
+; RV64I-NEXT: lw t3, 56(a0)
+; RV64I-NEXT: lw t4, 60(a0)
+; RV64I-NEXT: lw t5, 64(a0)
+; RV64I-NEXT: lw t6, 68(a0)
+; RV64I-NEXT: lw s0, 32(a0)
+; RV64I-NEXT: lw s1, 36(a0)
+; RV64I-NEXT: lw s2, 40(a0)
+; RV64I-NEXT: lw s3, 44(a0)
+; RV64I-NEXT: sw t6, 68(a0)
+; RV64I-NEXT: sw t5, 64(a0)
+; RV64I-NEXT: sw t4, 60(a0)
+; RV64I-NEXT: sw t3, 56(a0)
+; RV64I-NEXT: sw t2, 52(a0)
+; RV64I-NEXT: sw t1, 48(a0)
+; RV64I-NEXT: sw s3, 44(a0)
+; RV64I-NEXT: sw s2, 40(a0)
+; RV64I-NEXT: sw s1, 36(a0)
+; RV64I-NEXT: sw s0, 32(a0)
+; RV64I-NEXT: sw t0, 28(a0)
+; RV64I-NEXT: sw a7, 24(a0)
+; RV64I-NEXT: sw a6, 20(a0)
+; RV64I-NEXT: sw a5, 16(a0)
+; RV64I-NEXT: sw a4, 12(a0)
+; RV64I-NEXT: sw a3, 8(a0)
+; RV64I-NEXT: sw a2, 4(a0)
+; RV64I-NEXT: sw a1, 0(a0)
+; RV64I-NEXT: ld s0, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
-; RV64I-NEXT: .cfi_restore s4
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
entry:
@@ -2299,23 +2271,23 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IZCMP-NEXT: .cfi_offset s9, -12
; RV32IZCMP-NEXT: .cfi_offset s10, -8
; RV32IZCMP-NEXT: .cfi_offset s11, -4
-; RV32IZCMP-NEXT: addi sp, sp, -48
-; RV32IZCMP-NEXT: .cfi_def_cfa_offset 160
-; RV32IZCMP-NEXT: sw t0, 92(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw t1, 88(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw t2, 84(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw a1, 76(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw a2, 72(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw a3, 68(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw a4, 64(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw a5, 60(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw a6, 56(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw a7, 52(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw t3, 48(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw t4, 44(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw t5, 40(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: sw t6, 36(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: addi sp, sp, -32
+; RV32IZCMP-NEXT: .cfi_def_cfa_offset 144
+; RV32IZCMP-NEXT: sw t0, 76(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw t1, 72(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw t2, 68(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw a1, 60(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw a2, 56(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw a3, 52(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw a4, 48(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw a5, 44(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw a6, 40(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw a7, 36(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw t3, 32(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw t4, 28(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw t5, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: sw t6, 20(sp) # 4-byte Folded Spill
; RV32IZCMP-NEXT: .cfi_offset t0, -68
; RV32IZCMP-NEXT: .cfi_offset t1, -72
; RV32IZCMP-NEXT: .cfi_offset t2, -76
@@ -2331,99 +2303,97 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IZCMP-NEXT: .cfi_offset t4, -116
; RV32IZCMP-NEXT: .cfi_offset t5, -120
; RV32IZCMP-NEXT: .cfi_offset t6, -124
-; RV32IZCMP-NEXT: lui t0, %hi(var_test_irq)
-; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV32IZCMP-NEXT: lw a0, 16(a5)
-; RV32IZCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 20(a5)
-; RV32IZCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw t4, 24(a5)
-; RV32IZCMP-NEXT: lw t5, 28(a5)
-; RV32IZCMP-NEXT: lw t6, 32(a5)
-; RV32IZCMP-NEXT: lw s2, 36(a5)
-; RV32IZCMP-NEXT: lw s3, 40(a5)
-; RV32IZCMP-NEXT: lw s4, 44(a5)
-; RV32IZCMP-NEXT: lw s5, 48(a5)
-; RV32IZCMP-NEXT: lw s6, 52(a5)
-; RV32IZCMP-NEXT: lw s7, 56(a5)
-; RV32IZCMP-NEXT: lw s8, 60(a5)
-; RV32IZCMP-NEXT: lw s9, 64(a5)
-; RV32IZCMP-NEXT: lw s10, 68(a5)
-; RV32IZCMP-NEXT: lw s11, 72(a5)
-; RV32IZCMP-NEXT: lw ra, 76(a5)
-; RV32IZCMP-NEXT: lw s1, 80(a5)
-; RV32IZCMP-NEXT: lw t3, 84(a5)
-; RV32IZCMP-NEXT: lw t2, 88(a5)
-; RV32IZCMP-NEXT: lw t1, 92(a5)
-; RV32IZCMP-NEXT: lw a7, 112(a5)
-; RV32IZCMP-NEXT: lw s0, 116(a5)
-; RV32IZCMP-NEXT: lw a3, 120(a5)
-; RV32IZCMP-NEXT: lw a0, 124(a5)
-; RV32IZCMP-NEXT: lw a6, 96(a5)
-; RV32IZCMP-NEXT: lw a4, 100(a5)
-; RV32IZCMP-NEXT: lw a2, 104(a5)
-; RV32IZCMP-NEXT: lw a1, 108(a5)
-; RV32IZCMP-NEXT: sw a0, 124(a5)
-; RV32IZCMP-NEXT: sw a3, 120(a5)
-; RV32IZCMP-NEXT: sw s0, 116(a5)
-; RV32IZCMP-NEXT: sw a7, 112(a5)
-; RV32IZCMP-NEXT: sw a1, 108(a5)
-; RV32IZCMP-NEXT: sw a2, 104(a5)
-; RV32IZCMP-NEXT: sw a4, 100(a5)
-; RV32IZCMP-NEXT: sw a6, 96(a5)
-; RV32IZCMP-NEXT: sw t1, 92(a5)
-; RV32IZCMP-NEXT: sw t2, 88(a5)
-; RV32IZCMP-NEXT: sw t3, 84(a5)
-; RV32IZCMP-NEXT: sw s1, 80(a5)
-; RV32IZCMP-NEXT: sw ra, 76(a5)
-; RV32IZCMP-NEXT: sw s11, 72(a5)
-; RV32IZCMP-NEXT: sw s10, 68(a5)
-; RV32IZCMP-NEXT: sw s9, 64(a5)
-; RV32IZCMP-NEXT: sw s8, 60(a5)
-; RV32IZCMP-NEXT: sw s7, 56(a5)
-; RV32IZCMP-NEXT: sw s6, 52(a5)
-; RV32IZCMP-NEXT: sw s5, 48(a5)
-; RV32IZCMP-NEXT: sw s4, 44(a5)
-; RV32IZCMP-NEXT: sw s3, 40(a5)
-; RV32IZCMP-NEXT: sw s2, 36(a5)
-; RV32IZCMP-NEXT: sw t6, 32(a5)
-; RV32IZCMP-NEXT: sw t5, 28(a5)
-; RV32IZCMP-NEXT: sw t4, 24(a5)
-; RV32IZCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 20(a5)
-; RV32IZCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 16(a5)
-; RV32IZCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-NEXT: lw t0, 92(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw t1, 88(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw t2, 84(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw a1, 76(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw a2, 72(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw a3, 68(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw a4, 64(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw a5, 60(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw a6, 56(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw a7, 52(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw t3, 48(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw t4, 44(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw t5, 40(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: lw t6, 36(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lui a0, %hi(var_test_irq)
+; RV32IZCMP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32IZCMP-NEXT: lw a1, 0(a0)
+; RV32IZCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 4(a0)
+; RV32IZCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 8(a0)
+; RV32IZCMP-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 12(a0)
+; RV32IZCMP-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 16(a0)
+; RV32IZCMP-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw t3, 20(a0)
+; RV32IZCMP-NEXT: lw t4, 24(a0)
+; RV32IZCMP-NEXT: lw t5, 28(a0)
+; RV32IZCMP-NEXT: lw t6, 32(a0)
+; RV32IZCMP-NEXT: lw s2, 36(a0)
+; RV32IZCMP-NEXT: lw s3, 40(a0)
+; RV32IZCMP-NEXT: lw s4, 44(a0)
+; RV32IZCMP-NEXT: lw s5, 48(a0)
+; RV32IZCMP-NEXT: lw s6, 52(a0)
+; RV32IZCMP-NEXT: lw s7, 56(a0)
+; RV32IZCMP-NEXT: lw s8, 60(a0)
+; RV32IZCMP-NEXT: lw s9, 64(a0)
+; RV32IZCMP-NEXT: lw s10, 68(a0)
+; RV32IZCMP-NEXT: lw s11, 72(a0)
+; RV32IZCMP-NEXT: lw ra, 76(a0)
+; RV32IZCMP-NEXT: lw t2, 80(a0)
+; RV32IZCMP-NEXT: lw s0, 84(a0)
+; RV32IZCMP-NEXT: lw s1, 88(a0)
+; RV32IZCMP-NEXT: lw t1, 92(a0)
+; RV32IZCMP-NEXT: lw t0, 112(a0)
+; RV32IZCMP-NEXT: lw a5, 116(a0)
+; RV32IZCMP-NEXT: lw a3, 120(a0)
+; RV32IZCMP-NEXT: lw a1, 124(a0)
+; RV32IZCMP-NEXT: lw a7, 96(a0)
+; RV32IZCMP-NEXT: lw a6, 100(a0)
+; RV32IZCMP-NEXT: lw a4, 104(a0)
+; RV32IZCMP-NEXT: lw a2, 108(a0)
+; RV32IZCMP-NEXT: sw a1, 124(a0)
+; RV32IZCMP-NEXT: sw a3, 120(a0)
+; RV32IZCMP-NEXT: sw a5, 116(a0)
+; RV32IZCMP-NEXT: sw t0, 112(a0)
+; RV32IZCMP-NEXT: sw a2, 108(a0)
+; RV32IZCMP-NEXT: sw a4, 104(a0)
+; RV32IZCMP-NEXT: sw a6, 100(a0)
+; RV32IZCMP-NEXT: sw a7, 96(a0)
+; RV32IZCMP-NEXT: sw t1, 92(a0)
+; RV32IZCMP-NEXT: sw s1, 88(a0)
+; RV32IZCMP-NEXT: sw s0, 84(a0)
+; RV32IZCMP-NEXT: sw t2, 80(a0)
+; RV32IZCMP-NEXT: sw ra, 76(a0)
+; RV32IZCMP-NEXT: sw s11, 72(a0)
+; RV32IZCMP-NEXT: sw s10, 68(a0)
+; RV32IZCMP-NEXT: sw s9, 64(a0)
+; RV32IZCMP-NEXT: sw s8, 60(a0)
+; RV32IZCMP-NEXT: sw s7, 56(a0)
+; RV32IZCMP-NEXT: sw s6, 52(a0)
+; RV32IZCMP-NEXT: sw s5, 48(a0)
+; RV32IZCMP-NEXT: sw s4, 44(a0)
+; RV32IZCMP-NEXT: sw s3, 40(a0)
+; RV32IZCMP-NEXT: sw s2, 36(a0)
+; RV32IZCMP-NEXT: sw t6, 32(a0)
+; RV32IZCMP-NEXT: sw t5, 28(a0)
+; RV32IZCMP-NEXT: sw t4, 24(a0)
+; RV32IZCMP-NEXT: sw t3, 20(a0)
+; RV32IZCMP-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 16(a0)
+; RV32IZCMP-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 12(a0)
+; RV32IZCMP-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 8(a0)
+; RV32IZCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 4(a0)
+; RV32IZCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 0(a0)
+; RV32IZCMP-NEXT: lw t0, 76(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw t1, 72(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw t2, 68(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw a1, 60(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw a2, 56(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw a3, 52(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw a4, 48(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw a5, 44(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw a6, 40(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw a7, 36(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw t3, 32(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw t4, 28(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw t5, 24(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: lw t6, 20(sp) # 4-byte Folded Reload
; RV32IZCMP-NEXT: .cfi_restore t0
; RV32IZCMP-NEXT: .cfi_restore t1
; RV32IZCMP-NEXT: .cfi_restore t2
@@ -2439,7 +2409,7 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IZCMP-NEXT: .cfi_restore t4
; RV32IZCMP-NEXT: .cfi_restore t5
; RV32IZCMP-NEXT: .cfi_restore t6
-; RV32IZCMP-NEXT: addi sp, sp, 48
+; RV32IZCMP-NEXT: addi sp, sp, 32
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 112
; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 112
; RV32IZCMP-NEXT: .cfi_restore ra
@@ -2475,23 +2445,23 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IZCMP-NEXT: .cfi_offset s9, -24
; RV64IZCMP-NEXT: .cfi_offset s10, -16
; RV64IZCMP-NEXT: .cfi_offset s11, -8
-; RV64IZCMP-NEXT: addi sp, sp, -128
-; RV64IZCMP-NEXT: .cfi_def_cfa_offset 288
-; RV64IZCMP-NEXT: sd t0, 168(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd t1, 160(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd t2, 152(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd a1, 136(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd a2, 128(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd a3, 120(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd a4, 112(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd a5, 104(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd a6, 96(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd a7, 88(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd t3, 80(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd t4, 72(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd t5, 64(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: sd t6, 56(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: addi sp, sp, -112
+; RV64IZCMP-NEXT: .cfi_def_cfa_offset 272
+; RV64IZCMP-NEXT: sd t0, 152(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd t1, 144(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd t2, 136(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd a1, 120(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd a2, 112(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd a3, 104(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd a4, 96(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd a5, 88(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd a6, 80(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd a7, 72(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd t3, 64(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd t4, 56(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd t5, 48(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: sd t6, 40(sp) # 8-byte Folded Spill
; RV64IZCMP-NEXT: .cfi_offset t0, -120
; RV64IZCMP-NEXT: .cfi_offset t1, -128
; RV64IZCMP-NEXT: .cfi_offset t2, -136
@@ -2507,99 +2477,97 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IZCMP-NEXT: .cfi_offset t4, -216
; RV64IZCMP-NEXT: .cfi_offset t5, -224
; RV64IZCMP-NEXT: .cfi_offset t6, -232
-; RV64IZCMP-NEXT: lui t0, %hi(var_test_irq)
-; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV64IZCMP-NEXT: lw a0, 16(a5)
-; RV64IZCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 20(a5)
-; RV64IZCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw t4, 24(a5)
-; RV64IZCMP-NEXT: lw t5, 28(a5)
-; RV64IZCMP-NEXT: lw t6, 32(a5)
-; RV64IZCMP-NEXT: lw s2, 36(a5)
-; RV64IZCMP-NEXT: lw s3, 40(a5)
-; RV64IZCMP-NEXT: lw s4, 44(a5)
-; RV64IZCMP-NEXT: lw s5, 48(a5)
-; RV64IZCMP-NEXT: lw s6, 52(a5)
-; RV64IZCMP-NEXT: lw s7, 56(a5)
-; RV64IZCMP-NEXT: lw s8, 60(a5)
-; RV64IZCMP-NEXT: lw s9, 64(a5)
-; RV64IZCMP-NEXT: lw s10, 68(a5)
-; RV64IZCMP-NEXT: lw s11, 72(a5)
-; RV64IZCMP-NEXT: lw ra, 76(a5)
-; RV64IZCMP-NEXT: lw s1, 80(a5)
-; RV64IZCMP-NEXT: lw t3, 84(a5)
-; RV64IZCMP-NEXT: lw t2, 88(a5)
-; RV64IZCMP-NEXT: lw t1, 92(a5)
-; RV64IZCMP-NEXT: lw a7, 112(a5)
-; RV64IZCMP-NEXT: lw s0, 116(a5)
-; RV64IZCMP-NEXT: lw a3, 120(a5)
-; RV64IZCMP-NEXT: lw a0, 124(a5)
-; RV64IZCMP-NEXT: lw a6, 96(a5)
-; RV64IZCMP-NEXT: lw a4, 100(a5)
-; RV64IZCMP-NEXT: lw a2, 104(a5)
-; RV64IZCMP-NEXT: lw a1, 108(a5)
-; RV64IZCMP-NEXT: sw a0, 124(a5)
-; RV64IZCMP-NEXT: sw a3, 120(a5)
-; RV64IZCMP-NEXT: sw s0, 116(a5)
-; RV64IZCMP-NEXT: sw a7, 112(a5)
-; RV64IZCMP-NEXT: sw a1, 108(a5)
-; RV64IZCMP-NEXT: sw a2, 104(a5)
-; RV64IZCMP-NEXT: sw a4, 100(a5)
-; RV64IZCMP-NEXT: sw a6, 96(a5)
-; RV64IZCMP-NEXT: sw t1, 92(a5)
-; RV64IZCMP-NEXT: sw t2, 88(a5)
-; RV64IZCMP-NEXT: sw t3, 84(a5)
-; RV64IZCMP-NEXT: sw s1, 80(a5)
-; RV64IZCMP-NEXT: sw ra, 76(a5)
-; RV64IZCMP-NEXT: sw s11, 72(a5)
-; RV64IZCMP-NEXT: sw s10, 68(a5)
-; RV64IZCMP-NEXT: sw s9, 64(a5)
-; RV64IZCMP-NEXT: sw s8, 60(a5)
-; RV64IZCMP-NEXT: sw s7, 56(a5)
-; RV64IZCMP-NEXT: sw s6, 52(a5)
-; RV64IZCMP-NEXT: sw s5, 48(a5)
-; RV64IZCMP-NEXT: sw s4, 44(a5)
-; RV64IZCMP-NEXT: sw s3, 40(a5)
-; RV64IZCMP-NEXT: sw s2, 36(a5)
-; RV64IZCMP-NEXT: sw t6, 32(a5)
-; RV64IZCMP-NEXT: sw t5, 28(a5)
-; RV64IZCMP-NEXT: sw t4, 24(a5)
-; RV64IZCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 20(a5)
-; RV64IZCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 16(a5)
-; RV64IZCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-NEXT: ld t0, 168(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld t1, 160(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld t2, 152(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld a0, 144(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld a1, 136(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld a2, 128(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld a3, 120(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld a4, 112(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld a5, 104(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld a6, 96(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld a7, 88(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld t3, 80(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld t4, 72(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld t5, 64(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: ld t6, 56(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: lui a0, %hi(var_test_irq)
+; RV64IZCMP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64IZCMP-NEXT: lw a1, 0(a0)
+; RV64IZCMP-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 4(a0)
+; RV64IZCMP-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 8(a0)
+; RV64IZCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 12(a0)
+; RV64IZCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 16(a0)
+; RV64IZCMP-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw t3, 20(a0)
+; RV64IZCMP-NEXT: lw t4, 24(a0)
+; RV64IZCMP-NEXT: lw t5, 28(a0)
+; RV64IZCMP-NEXT: lw t6, 32(a0)
+; RV64IZCMP-NEXT: lw s2, 36(a0)
+; RV64IZCMP-NEXT: lw s3, 40(a0)
+; RV64IZCMP-NEXT: lw s4, 44(a0)
+; RV64IZCMP-NEXT: lw s5, 48(a0)
+; RV64IZCMP-NEXT: lw s6, 52(a0)
+; RV64IZCMP-NEXT: lw s7, 56(a0)
+; RV64IZCMP-NEXT: lw s8, 60(a0)
+; RV64IZCMP-NEXT: lw s9, 64(a0)
+; RV64IZCMP-NEXT: lw s10, 68(a0)
+; RV64IZCMP-NEXT: lw s11, 72(a0)
+; RV64IZCMP-NEXT: lw ra, 76(a0)
+; RV64IZCMP-NEXT: lw t2, 80(a0)
+; RV64IZCMP-NEXT: lw s0, 84(a0)
+; RV64IZCMP-NEXT: lw s1, 88(a0)
+; RV64IZCMP-NEXT: lw t1, 92(a0)
+; RV64IZCMP-NEXT: lw t0, 112(a0)
+; RV64IZCMP-NEXT: lw a5, 116(a0)
+; RV64IZCMP-NEXT: lw a3, 120(a0)
+; RV64IZCMP-NEXT: lw a1, 124(a0)
+; RV64IZCMP-NEXT: lw a7, 96(a0)
+; RV64IZCMP-NEXT: lw a6, 100(a0)
+; RV64IZCMP-NEXT: lw a4, 104(a0)
+; RV64IZCMP-NEXT: lw a2, 108(a0)
+; RV64IZCMP-NEXT: sw a1, 124(a0)
+; RV64IZCMP-NEXT: sw a3, 120(a0)
+; RV64IZCMP-NEXT: sw a5, 116(a0)
+; RV64IZCMP-NEXT: sw t0, 112(a0)
+; RV64IZCMP-NEXT: sw a2, 108(a0)
+; RV64IZCMP-NEXT: sw a4, 104(a0)
+; RV64IZCMP-NEXT: sw a6, 100(a0)
+; RV64IZCMP-NEXT: sw a7, 96(a0)
+; RV64IZCMP-NEXT: sw t1, 92(a0)
+; RV64IZCMP-NEXT: sw s1, 88(a0)
+; RV64IZCMP-NEXT: sw s0, 84(a0)
+; RV64IZCMP-NEXT: sw t2, 80(a0)
+; RV64IZCMP-NEXT: sw ra, 76(a0)
+; RV64IZCMP-NEXT: sw s11, 72(a0)
+; RV64IZCMP-NEXT: sw s10, 68(a0)
+; RV64IZCMP-NEXT: sw s9, 64(a0)
+; RV64IZCMP-NEXT: sw s8, 60(a0)
+; RV64IZCMP-NEXT: sw s7, 56(a0)
+; RV64IZCMP-NEXT: sw s6, 52(a0)
+; RV64IZCMP-NEXT: sw s5, 48(a0)
+; RV64IZCMP-NEXT: sw s4, 44(a0)
+; RV64IZCMP-NEXT: sw s3, 40(a0)
+; RV64IZCMP-NEXT: sw s2, 36(a0)
+; RV64IZCMP-NEXT: sw t6, 32(a0)
+; RV64IZCMP-NEXT: sw t5, 28(a0)
+; RV64IZCMP-NEXT: sw t4, 24(a0)
+; RV64IZCMP-NEXT: sw t3, 20(a0)
+; RV64IZCMP-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 16(a0)
+; RV64IZCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 12(a0)
+; RV64IZCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 8(a0)
+; RV64IZCMP-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 4(a0)
+; RV64IZCMP-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 0(a0)
+; RV64IZCMP-NEXT: ld t0, 152(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld t1, 144(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld t2, 136(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld a0, 128(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld a1, 120(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld a2, 112(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld a3, 104(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld a4, 96(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld a5, 88(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld a6, 80(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld a7, 72(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld t3, 64(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld t4, 56(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld t5, 48(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: ld t6, 40(sp) # 8-byte Folded Reload
; RV64IZCMP-NEXT: .cfi_restore t0
; RV64IZCMP-NEXT: .cfi_restore t1
; RV64IZCMP-NEXT: .cfi_restore t2
@@ -2615,7 +2583,7 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IZCMP-NEXT: .cfi_restore t4
; RV64IZCMP-NEXT: .cfi_restore t5
; RV64IZCMP-NEXT: .cfi_restore t6
-; RV64IZCMP-NEXT: addi sp, sp, 128
+; RV64IZCMP-NEXT: addi sp, sp, 112
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 160
; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 160
; RV64IZCMP-NEXT: .cfi_restore ra
@@ -2651,23 +2619,23 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IZCMP-SR-NEXT: .cfi_offset s9, -12
; RV32IZCMP-SR-NEXT: .cfi_offset s10, -8
; RV32IZCMP-SR-NEXT: .cfi_offset s11, -4
-; RV32IZCMP-SR-NEXT: addi sp, sp, -48
-; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 160
-; RV32IZCMP-SR-NEXT: sw t0, 92(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw t1, 88(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw t2, 84(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw a1, 76(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw a2, 72(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw a3, 68(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw a4, 64(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw a5, 60(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw a6, 56(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw a7, 52(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw t3, 48(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw t4, 44(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw t5, 40(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: sw t6, 36(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: addi sp, sp, -32
+; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 144
+; RV32IZCMP-SR-NEXT: sw t0, 76(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw t1, 72(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw t2, 68(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw a1, 60(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw a2, 56(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw a3, 52(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw a4, 48(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw a5, 44(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw a6, 40(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw a7, 36(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw t3, 32(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw t4, 28(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw t5, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: sw t6, 20(sp) # 4-byte Folded Spill
; RV32IZCMP-SR-NEXT: .cfi_offset t0, -68
; RV32IZCMP-SR-NEXT: .cfi_offset t1, -72
; RV32IZCMP-SR-NEXT: .cfi_offset t2, -76
@@ -2683,99 +2651,97 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IZCMP-SR-NEXT: .cfi_offset t4, -116
; RV32IZCMP-SR-NEXT: .cfi_offset t5, -120
; RV32IZCMP-SR-NEXT: .cfi_offset t6, -124
-; RV32IZCMP-SR-NEXT: lui t0, %hi(var_test_irq)
-; RV32IZCMP-SR-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-SR-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-SR-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-SR-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-SR-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV32IZCMP-SR-NEXT: lw a0, 16(a5)
-; RV32IZCMP-SR-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw a0, 20(a5)
-; RV32IZCMP-SR-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw t4, 24(a5)
-; RV32IZCMP-SR-NEXT: lw t5, 28(a5)
-; RV32IZCMP-SR-NEXT: lw t6, 32(a5)
-; RV32IZCMP-SR-NEXT: lw s2, 36(a5)
-; RV32IZCMP-SR-NEXT: lw s3, 40(a5)
-; RV32IZCMP-SR-NEXT: lw s4, 44(a5)
-; RV32IZCMP-SR-NEXT: lw s5, 48(a5)
-; RV32IZCMP-SR-NEXT: lw s6, 52(a5)
-; RV32IZCMP-SR-NEXT: lw s7, 56(a5)
-; RV32IZCMP-SR-NEXT: lw s8, 60(a5)
-; RV32IZCMP-SR-NEXT: lw s9, 64(a5)
-; RV32IZCMP-SR-NEXT: lw s10, 68(a5)
-; RV32IZCMP-SR-NEXT: lw s11, 72(a5)
-; RV32IZCMP-SR-NEXT: lw ra, 76(a5)
-; RV32IZCMP-SR-NEXT: lw s1, 80(a5)
-; RV32IZCMP-SR-NEXT: lw t3, 84(a5)
-; RV32IZCMP-SR-NEXT: lw t2, 88(a5)
-; RV32IZCMP-SR-NEXT: lw t1, 92(a5)
-; RV32IZCMP-SR-NEXT: lw a7, 112(a5)
-; RV32IZCMP-SR-NEXT: lw s0, 116(a5)
-; RV32IZCMP-SR-NEXT: lw a3, 120(a5)
-; RV32IZCMP-SR-NEXT: lw a0, 124(a5)
-; RV32IZCMP-SR-NEXT: lw a6, 96(a5)
-; RV32IZCMP-SR-NEXT: lw a4, 100(a5)
-; RV32IZCMP-SR-NEXT: lw a2, 104(a5)
-; RV32IZCMP-SR-NEXT: lw a1, 108(a5)
-; RV32IZCMP-SR-NEXT: sw a0, 124(a5)
-; RV32IZCMP-SR-NEXT: sw a3, 120(a5)
-; RV32IZCMP-SR-NEXT: sw s0, 116(a5)
-; RV32IZCMP-SR-NEXT: sw a7, 112(a5)
-; RV32IZCMP-SR-NEXT: sw a1, 108(a5)
-; RV32IZCMP-SR-NEXT: sw a2, 104(a5)
-; RV32IZCMP-SR-NEXT: sw a4, 100(a5)
-; RV32IZCMP-SR-NEXT: sw a6, 96(a5)
-; RV32IZCMP-SR-NEXT: sw t1, 92(a5)
-; RV32IZCMP-SR-NEXT: sw t2, 88(a5)
-; RV32IZCMP-SR-NEXT: sw t3, 84(a5)
-; RV32IZCMP-SR-NEXT: sw s1, 80(a5)
-; RV32IZCMP-SR-NEXT: sw ra, 76(a5)
-; RV32IZCMP-SR-NEXT: sw s11, 72(a5)
-; RV32IZCMP-SR-NEXT: sw s10, 68(a5)
-; RV32IZCMP-SR-NEXT: sw s9, 64(a5)
-; RV32IZCMP-SR-NEXT: sw s8, 60(a5)
-; RV32IZCMP-SR-NEXT: sw s7, 56(a5)
-; RV32IZCMP-SR-NEXT: sw s6, 52(a5)
-; RV32IZCMP-SR-NEXT: sw s5, 48(a5)
-; RV32IZCMP-SR-NEXT: sw s4, 44(a5)
-; RV32IZCMP-SR-NEXT: sw s3, 40(a5)
-; RV32IZCMP-SR-NEXT: sw s2, 36(a5)
-; RV32IZCMP-SR-NEXT: sw t6, 32(a5)
-; RV32IZCMP-SR-NEXT: sw t5, 28(a5)
-; RV32IZCMP-SR-NEXT: sw t4, 24(a5)
-; RV32IZCMP-SR-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, 20(a5)
-; RV32IZCMP-SR-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, 16(a5)
-; RV32IZCMP-SR-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-SR-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-SR-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-SR-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-SR-NEXT: lw t0, 92(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw t1, 88(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw t2, 84(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw a1, 76(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw a2, 72(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw a3, 68(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw a4, 64(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw a5, 60(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw a6, 56(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw a7, 52(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw t3, 48(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw t4, 44(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw t5, 40(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: lw t6, 36(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lui a0, %hi(var_test_irq)
+; RV32IZCMP-SR-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32IZCMP-SR-NEXT: lw a1, 0(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: lw a1, 4(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: lw a1, 8(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: lw a1, 12(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: lw a1, 16(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: lw t3, 20(a0)
+; RV32IZCMP-SR-NEXT: lw t4, 24(a0)
+; RV32IZCMP-SR-NEXT: lw t5, 28(a0)
+; RV32IZCMP-SR-NEXT: lw t6, 32(a0)
+; RV32IZCMP-SR-NEXT: lw s2, 36(a0)
+; RV32IZCMP-SR-NEXT: lw s3, 40(a0)
+; RV32IZCMP-SR-NEXT: lw s4, 44(a0)
+; RV32IZCMP-SR-NEXT: lw s5, 48(a0)
+; RV32IZCMP-SR-NEXT: lw s6, 52(a0)
+; RV32IZCMP-SR-NEXT: lw s7, 56(a0)
+; RV32IZCMP-SR-NEXT: lw s8, 60(a0)
+; RV32IZCMP-SR-NEXT: lw s9, 64(a0)
+; RV32IZCMP-SR-NEXT: lw s10, 68(a0)
+; RV32IZCMP-SR-NEXT: lw s11, 72(a0)
+; RV32IZCMP-SR-NEXT: lw ra, 76(a0)
+; RV32IZCMP-SR-NEXT: lw t2, 80(a0)
+; RV32IZCMP-SR-NEXT: lw s0, 84(a0)
+; RV32IZCMP-SR-NEXT: lw s1, 88(a0)
+; RV32IZCMP-SR-NEXT: lw t1, 92(a0)
+; RV32IZCMP-SR-NEXT: lw t0, 112(a0)
+; RV32IZCMP-SR-NEXT: lw a5, 116(a0)
+; RV32IZCMP-SR-NEXT: lw a3, 120(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 124(a0)
+; RV32IZCMP-SR-NEXT: lw a7, 96(a0)
+; RV32IZCMP-SR-NEXT: lw a6, 100(a0)
+; RV32IZCMP-SR-NEXT: lw a4, 104(a0)
+; RV32IZCMP-SR-NEXT: lw a2, 108(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 124(a0)
+; RV32IZCMP-SR-NEXT: sw a3, 120(a0)
+; RV32IZCMP-SR-NEXT: sw a5, 116(a0)
+; RV32IZCMP-SR-NEXT: sw t0, 112(a0)
+; RV32IZCMP-SR-NEXT: sw a2, 108(a0)
+; RV32IZCMP-SR-NEXT: sw a4, 104(a0)
+; RV32IZCMP-SR-NEXT: sw a6, 100(a0)
+; RV32IZCMP-SR-NEXT: sw a7, 96(a0)
+; RV32IZCMP-SR-NEXT: sw t1, 92(a0)
+; RV32IZCMP-SR-NEXT: sw s1, 88(a0)
+; RV32IZCMP-SR-NEXT: sw s0, 84(a0)
+; RV32IZCMP-SR-NEXT: sw t2, 80(a0)
+; RV32IZCMP-SR-NEXT: sw ra, 76(a0)
+; RV32IZCMP-SR-NEXT: sw s11, 72(a0)
+; RV32IZCMP-SR-NEXT: sw s10, 68(a0)
+; RV32IZCMP-SR-NEXT: sw s9, 64(a0)
+; RV32IZCMP-SR-NEXT: sw s8, 60(a0)
+; RV32IZCMP-SR-NEXT: sw s7, 56(a0)
+; RV32IZCMP-SR-NEXT: sw s6, 52(a0)
+; RV32IZCMP-SR-NEXT: sw s5, 48(a0)
+; RV32IZCMP-SR-NEXT: sw s4, 44(a0)
+; RV32IZCMP-SR-NEXT: sw s3, 40(a0)
+; RV32IZCMP-SR-NEXT: sw s2, 36(a0)
+; RV32IZCMP-SR-NEXT: sw t6, 32(a0)
+; RV32IZCMP-SR-NEXT: sw t5, 28(a0)
+; RV32IZCMP-SR-NEXT: sw t4, 24(a0)
+; RV32IZCMP-SR-NEXT: sw t3, 20(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: sw a1, 16(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: sw a1, 12(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: sw a1, 8(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: sw a1, 4(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: sw a1, 0(a0)
+; RV32IZCMP-SR-NEXT: lw t0, 76(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw t1, 72(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw t2, 68(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw a1, 60(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw a2, 56(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw a3, 52(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw a4, 48(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw a5, 44(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw a6, 40(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw a7, 36(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw t3, 32(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw t4, 28(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw t5, 24(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: lw t6, 20(sp) # 4-byte Folded Reload
; RV32IZCMP-SR-NEXT: .cfi_restore t0
; RV32IZCMP-SR-NEXT: .cfi_restore t1
; RV32IZCMP-SR-NEXT: .cfi_restore t2
@@ -2791,7 +2757,7 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IZCMP-SR-NEXT: .cfi_restore t4
; RV32IZCMP-SR-NEXT: .cfi_restore t5
; RV32IZCMP-SR-NEXT: .cfi_restore t6
-; RV32IZCMP-SR-NEXT: addi sp, sp, 48
+; RV32IZCMP-SR-NEXT: addi sp, sp, 32
; RV32IZCMP-SR-NEXT: .cfi_def_cfa_offset 112
; RV32IZCMP-SR-NEXT: cm.pop {ra, s0-s11}, 112
; RV32IZCMP-SR-NEXT: .cfi_restore ra
@@ -2827,23 +2793,23 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IZCMP-SR-NEXT: .cfi_offset s9, -24
; RV64IZCMP-SR-NEXT: .cfi_offset s10, -16
; RV64IZCMP-SR-NEXT: .cfi_offset s11, -8
-; RV64IZCMP-SR-NEXT: addi sp, sp, -128
-; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 288
-; RV64IZCMP-SR-NEXT: sd t0, 168(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd t1, 160(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd t2, 152(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd a1, 136(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd a2, 128(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd a3, 120(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd a4, 112(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd a5, 104(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd a6, 96(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd a7, 88(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd t3, 80(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd t4, 72(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd t5, 64(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: sd t6, 56(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: addi sp, sp, -112
+; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 272
+; RV64IZCMP-SR-NEXT: sd t0, 152(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd t1, 144(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd t2, 136(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd a1, 120(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd a2, 112(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd a3, 104(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd a4, 96(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd a5, 88(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd a6, 80(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd a7, 72(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd t3, 64(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd t4, 56(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd t5, 48(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: sd t6, 40(sp) # 8-byte Folded Spill
; RV64IZCMP-SR-NEXT: .cfi_offset t0, -120
; RV64IZCMP-SR-NEXT: .cfi_offset t1, -128
; RV64IZCMP-SR-NEXT: .cfi_offset t2, -136
@@ -2859,99 +2825,97 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IZCMP-SR-NEXT: .cfi_offset t4, -216
; RV64IZCMP-SR-NEXT: .cfi_offset t5, -224
; RV64IZCMP-SR-NEXT: .cfi_offset t6, -232
-; RV64IZCMP-SR-NEXT: lui t0, %hi(var_test_irq)
-; RV64IZCMP-SR-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-SR-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-SR-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-SR-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-SR-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV64IZCMP-SR-NEXT: lw a0, 16(a5)
-; RV64IZCMP-SR-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw a0, 20(a5)
-; RV64IZCMP-SR-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw t4, 24(a5)
-; RV64IZCMP-SR-NEXT: lw t5, 28(a5)
-; RV64IZCMP-SR-NEXT: lw t6, 32(a5)
-; RV64IZCMP-SR-NEXT: lw s2, 36(a5)
-; RV64IZCMP-SR-NEXT: lw s3, 40(a5)
-; RV64IZCMP-SR-NEXT: lw s4, 44(a5)
-; RV64IZCMP-SR-NEXT: lw s5, 48(a5)
-; RV64IZCMP-SR-NEXT: lw s6, 52(a5)
-; RV64IZCMP-SR-NEXT: lw s7, 56(a5)
-; RV64IZCMP-SR-NEXT: lw s8, 60(a5)
-; RV64IZCMP-SR-NEXT: lw s9, 64(a5)
-; RV64IZCMP-SR-NEXT: lw s10, 68(a5)
-; RV64IZCMP-SR-NEXT: lw s11, 72(a5)
-; RV64IZCMP-SR-NEXT: lw ra, 76(a5)
-; RV64IZCMP-SR-NEXT: lw s1, 80(a5)
-; RV64IZCMP-SR-NEXT: lw t3, 84(a5)
-; RV64IZCMP-SR-NEXT: lw t2, 88(a5)
-; RV64IZCMP-SR-NEXT: lw t1, 92(a5)
-; RV64IZCMP-SR-NEXT: lw a7, 112(a5)
-; RV64IZCMP-SR-NEXT: lw s0, 116(a5)
-; RV64IZCMP-SR-NEXT: lw a3, 120(a5)
-; RV64IZCMP-SR-NEXT: lw a0, 124(a5)
-; RV64IZCMP-SR-NEXT: lw a6, 96(a5)
-; RV64IZCMP-SR-NEXT: lw a4, 100(a5)
-; RV64IZCMP-SR-NEXT: lw a2, 104(a5)
-; RV64IZCMP-SR-NEXT: lw a1, 108(a5)
-; RV64IZCMP-SR-NEXT: sw a0, 124(a5)
-; RV64IZCMP-SR-NEXT: sw a3, 120(a5)
-; RV64IZCMP-SR-NEXT: sw s0, 116(a5)
-; RV64IZCMP-SR-NEXT: sw a7, 112(a5)
-; RV64IZCMP-SR-NEXT: sw a1, 108(a5)
-; RV64IZCMP-SR-NEXT: sw a2, 104(a5)
-; RV64IZCMP-SR-NEXT: sw a4, 100(a5)
-; RV64IZCMP-SR-NEXT: sw a6, 96(a5)
-; RV64IZCMP-SR-NEXT: sw t1, 92(a5)
-; RV64IZCMP-SR-NEXT: sw t2, 88(a5)
-; RV64IZCMP-SR-NEXT: sw t3, 84(a5)
-; RV64IZCMP-SR-NEXT: sw s1, 80(a5)
-; RV64IZCMP-SR-NEXT: sw ra, 76(a5)
-; RV64IZCMP-SR-NEXT: sw s11, 72(a5)
-; RV64IZCMP-SR-NEXT: sw s10, 68(a5)
-; RV64IZCMP-SR-NEXT: sw s9, 64(a5)
-; RV64IZCMP-SR-NEXT: sw s8, 60(a5)
-; RV64IZCMP-SR-NEXT: sw s7, 56(a5)
-; RV64IZCMP-SR-NEXT: sw s6, 52(a5)
-; RV64IZCMP-SR-NEXT: sw s5, 48(a5)
-; RV64IZCMP-SR-NEXT: sw s4, 44(a5)
-; RV64IZCMP-SR-NEXT: sw s3, 40(a5)
-; RV64IZCMP-SR-NEXT: sw s2, 36(a5)
-; RV64IZCMP-SR-NEXT: sw t6, 32(a5)
-; RV64IZCMP-SR-NEXT: sw t5, 28(a5)
-; RV64IZCMP-SR-NEXT: sw t4, 24(a5)
-; RV64IZCMP-SR-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, 20(a5)
-; RV64IZCMP-SR-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, 16(a5)
-; RV64IZCMP-SR-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-SR-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-SR-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-SR-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-SR-NEXT: ld t0, 168(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld t1, 160(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld t2, 152(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld a0, 144(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld a1, 136(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld a2, 128(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld a3, 120(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld a4, 112(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld a5, 104(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld a6, 96(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld a7, 88(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld t3, 80(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld t4, 72(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld t5, 64(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: ld t6, 56(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: lui a0, %hi(var_test_irq)
+; RV64IZCMP-SR-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64IZCMP-SR-NEXT: lw a1, 0(a0)
+; RV64IZCMP-SR-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: lw a1, 4(a0)
+; RV64IZCMP-SR-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: lw a1, 8(a0)
+; RV64IZCMP-SR-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: lw a1, 12(a0)
+; RV64IZCMP-SR-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: lw a1, 16(a0)
+; RV64IZCMP-SR-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: lw t3, 20(a0)
+; RV64IZCMP-SR-NEXT: lw t4, 24(a0)
+; RV64IZCMP-SR-NEXT: lw t5, 28(a0)
+; RV64IZCMP-SR-NEXT: lw t6, 32(a0)
+; RV64IZCMP-SR-NEXT: lw s2, 36(a0)
+; RV64IZCMP-SR-NEXT: lw s3, 40(a0)
+; RV64IZCMP-SR-NEXT: lw s4, 44(a0)
+; RV64IZCMP-SR-NEXT: lw s5, 48(a0)
+; RV64IZCMP-SR-NEXT: lw s6, 52(a0)
+; RV64IZCMP-SR-NEXT: lw s7, 56(a0)
+; RV64IZCMP-SR-NEXT: lw s8, 60(a0)
+; RV64IZCMP-SR-NEXT: lw s9, 64(a0)
+; RV64IZCMP-SR-NEXT: lw s10, 68(a0)
+; RV64IZCMP-SR-NEXT: lw s11, 72(a0)
+; RV64IZCMP-SR-NEXT: lw ra, 76(a0)
+; RV64IZCMP-SR-NEXT: lw t2, 80(a0)
+; RV64IZCMP-SR-NEXT: lw s0, 84(a0)
+; RV64IZCMP-SR-NEXT: lw s1, 88(a0)
+; RV64IZCMP-SR-NEXT: lw t1, 92(a0)
+; RV64IZCMP-SR-NEXT: lw t0, 112(a0)
+; RV64IZCMP-SR-NEXT: lw a5, 116(a0)
+; RV64IZCMP-SR-NEXT: lw a3, 120(a0)
+; RV64IZCMP-SR-NEXT: lw a1, 124(a0)
+; RV64IZCMP-SR-NEXT: lw a7, 96(a0)
+; RV64IZCMP-SR-NEXT: lw a6, 100(a0)
+; RV64IZCMP-SR-NEXT: lw a4, 104(a0)
+; RV64IZCMP-SR-NEXT: lw a2, 108(a0)
+; RV64IZCMP-SR-NEXT: sw a1, 124(a0)
+; RV64IZCMP-SR-NEXT: sw a3, 120(a0)
+; RV64IZCMP-SR-NEXT: sw a5, 116(a0)
+; RV64IZCMP-SR-NEXT: sw t0, 112(a0)
+; RV64IZCMP-SR-NEXT: sw a2, 108(a0)
+; RV64IZCMP-SR-NEXT: sw a4, 104(a0)
+; RV64IZCMP-SR-NEXT: sw a6, 100(a0)
+; RV64IZCMP-SR-NEXT: sw a7, 96(a0)
+; RV64IZCMP-SR-NEXT: sw t1, 92(a0)
+; RV64IZCMP-SR-NEXT: sw s1, 88(a0)
+; RV64IZCMP-SR-NEXT: sw s0, 84(a0)
+; RV64IZCMP-SR-NEXT: sw t2, 80(a0)
+; RV64IZCMP-SR-NEXT: sw ra, 76(a0)
+; RV64IZCMP-SR-NEXT: sw s11, 72(a0)
+; RV64IZCMP-SR-NEXT: sw s10, 68(a0)
+; RV64IZCMP-SR-NEXT: sw s9, 64(a0)
+; RV64IZCMP-SR-NEXT: sw s8, 60(a0)
+; RV64IZCMP-SR-NEXT: sw s7, 56(a0)
+; RV64IZCMP-SR-NEXT: sw s6, 52(a0)
+; RV64IZCMP-SR-NEXT: sw s5, 48(a0)
+; RV64IZCMP-SR-NEXT: sw s4, 44(a0)
+; RV64IZCMP-SR-NEXT: sw s3, 40(a0)
+; RV64IZCMP-SR-NEXT: sw s2, 36(a0)
+; RV64IZCMP-SR-NEXT: sw t6, 32(a0)
+; RV64IZCMP-SR-NEXT: sw t5, 28(a0)
+; RV64IZCMP-SR-NEXT: sw t4, 24(a0)
+; RV64IZCMP-SR-NEXT: sw t3, 20(a0)
+; RV64IZCMP-SR-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: sw a1, 16(a0)
+; RV64IZCMP-SR-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: sw a1, 12(a0)
+; RV64IZCMP-SR-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: sw a1, 8(a0)
+; RV64IZCMP-SR-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: sw a1, 4(a0)
+; RV64IZCMP-SR-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: sw a1, 0(a0)
+; RV64IZCMP-SR-NEXT: ld t0, 152(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld t1, 144(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld t2, 136(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld a0, 128(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld a1, 120(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld a2, 112(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld a3, 104(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld a4, 96(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld a5, 88(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld a6, 80(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld a7, 72(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld t3, 64(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld t4, 56(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld t5, 48(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: ld t6, 40(sp) # 8-byte Folded Reload
; RV64IZCMP-SR-NEXT: .cfi_restore t0
; RV64IZCMP-SR-NEXT: .cfi_restore t1
; RV64IZCMP-SR-NEXT: .cfi_restore t2
@@ -2967,7 +2931,7 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IZCMP-SR-NEXT: .cfi_restore t4
; RV64IZCMP-SR-NEXT: .cfi_restore t5
; RV64IZCMP-SR-NEXT: .cfi_restore t6
-; RV64IZCMP-SR-NEXT: addi sp, sp, 128
+; RV64IZCMP-SR-NEXT: addi sp, sp, 112
; RV64IZCMP-SR-NEXT: .cfi_def_cfa_offset 160
; RV64IZCMP-SR-NEXT: cm.pop {ra, s0-s11}, 160
; RV64IZCMP-SR-NEXT: .cfi_restore ra
@@ -3046,84 +3010,82 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32I-NEXT: .cfi_offset t4, -104
; RV32I-NEXT: .cfi_offset t5, -108
; RV32I-NEXT: .cfi_offset t6, -112
-; RV32I-NEXT: lui a7, %hi(var_test_irq)
-; RV32I-NEXT: lw a0, %lo(var_test_irq)(a7)
-; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var_test_irq+4)(a7)
-; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var_test_irq+8)(a7)
-; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var_test_irq+12)(a7)
-; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi a5, a7, %lo(var_test_irq)
-; RV32I-NEXT: lw a0, 16(a5)
-; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 20(a5)
-; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t0, 24(a5)
-; RV32I-NEXT: lw t1, 28(a5)
-; RV32I-NEXT: lw t2, 32(a5)
-; RV32I-NEXT: lw t3, 36(a5)
-; RV32I-NEXT: lw t4, 40(a5)
-; RV32I-NEXT: lw t5, 44(a5)
-; RV32I-NEXT: lw t6, 48(a5)
-; RV32I-NEXT: lw s0, 52(a5)
-; RV32I-NEXT: lw s1, 56(a5)
-; RV32I-NEXT: lw s2, 60(a5)
-; RV32I-NEXT: lw s3, 64(a5)
-; RV32I-NEXT: lw s4, 68(a5)
-; RV32I-NEXT: lw s5, 72(a5)
-; RV32I-NEXT: lw s6, 76(a5)
-; RV32I-NEXT: lw s7, 80(a5)
-; RV32I-NEXT: lw s8, 84(a5)
-; RV32I-NEXT: lw s9, 88(a5)
-; RV32I-NEXT: lw s10, 92(a5)
-; RV32I-NEXT: lw s11, 112(a5)
-; RV32I-NEXT: lw ra, 116(a5)
-; RV32I-NEXT: lw a3, 120(a5)
-; RV32I-NEXT: lw a0, 124(a5)
-; RV32I-NEXT: lw a6, 96(a5)
-; RV32I-NEXT: lw a4, 100(a5)
-; RV32I-NEXT: lw a2, 104(a5)
-; RV32I-NEXT: lw a1, 108(a5)
-; RV32I-NEXT: sw a0, 124(a5)
-; RV32I-NEXT: sw a3, 120(a5)
-; RV32I-NEXT: sw ra, 116(a5)
-; RV32I-NEXT: sw s11, 112(a5)
-; RV32I-NEXT: sw a1, 108(a5)
-; RV32I-NEXT: sw a2, 104(a5)
-; RV32I-NEXT: sw a4, 100(a5)
-; RV32I-NEXT: sw a6, 96(a5)
-; RV32I-NEXT: sw s10, 92(a5)
-; RV32I-NEXT: sw s9, 88(a5)
-; RV32I-NEXT: sw s8, 84(a5)
-; RV32I-NEXT: sw s7, 80(a5)
-; RV32I-NEXT: sw s6, 76(a5)
-; RV32I-NEXT: sw s5, 72(a5)
-; RV32I-NEXT: sw s4, 68(a5)
-; RV32I-NEXT: sw s3, 64(a5)
-; RV32I-NEXT: sw s2, 60(a5)
-; RV32I-NEXT: sw s1, 56(a5)
-; RV32I-NEXT: sw s0, 52(a5)
-; RV32I-NEXT: sw t6, 48(a5)
-; RV32I-NEXT: sw t5, 44(a5)
-; RV32I-NEXT: sw t4, 40(a5)
-; RV32I-NEXT: sw t3, 36(a5)
-; RV32I-NEXT: sw t2, 32(a5)
-; RV32I-NEXT: sw t1, 28(a5)
-; RV32I-NEXT: sw t0, 24(a5)
-; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 20(a5)
-; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 16(a5)
-; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var_test_irq+12)(a7)
-; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var_test_irq+8)(a7)
-; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var_test_irq+4)(a7)
-; RV32I-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var_test_irq)(a7)
+; RV32I-NEXT: lui a0, %hi(var_test_irq)
+; RV32I-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32I-NEXT: lw a1, 0(a0)
+; RV32I-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 4(a0)
+; RV32I-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 8(a0)
+; RV32I-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 12(a0)
+; RV32I-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 16(a0)
+; RV32I-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a6, 20(a0)
+; RV32I-NEXT: lw a7, 24(a0)
+; RV32I-NEXT: lw t0, 28(a0)
+; RV32I-NEXT: lw t1, 32(a0)
+; RV32I-NEXT: lw t2, 36(a0)
+; RV32I-NEXT: lw t3, 40(a0)
+; RV32I-NEXT: lw t4, 44(a0)
+; RV32I-NEXT: lw t5, 48(a0)
+; RV32I-NEXT: lw t6, 52(a0)
+; RV32I-NEXT: lw s0, 56(a0)
+; RV32I-NEXT: lw s1, 60(a0)
+; RV32I-NEXT: lw s2, 64(a0)
+; RV32I-NEXT: lw s3, 68(a0)
+; RV32I-NEXT: lw s4, 72(a0)
+; RV32I-NEXT: lw s5, 76(a0)
+; RV32I-NEXT: lw s6, 80(a0)
+; RV32I-NEXT: lw s7, 84(a0)
+; RV32I-NEXT: lw s8, 88(a0)
+; RV32I-NEXT: lw s9, 92(a0)
+; RV32I-NEXT: lw s10, 112(a0)
+; RV32I-NEXT: lw s11, 116(a0)
+; RV32I-NEXT: lw ra, 120(a0)
+; RV32I-NEXT: lw a1, 124(a0)
+; RV32I-NEXT: lw a5, 96(a0)
+; RV32I-NEXT: lw a4, 100(a0)
+; RV32I-NEXT: lw a3, 104(a0)
+; RV32I-NEXT: lw a2, 108(a0)
+; RV32I-NEXT: sw a1, 124(a0)
+; RV32I-NEXT: sw ra, 120(a0)
+; RV32I-NEXT: sw s11, 116(a0)
+; RV32I-NEXT: sw s10, 112(a0)
+; RV32I-NEXT: sw a2, 108(a0)
+; RV32I-NEXT: sw a3, 104(a0)
+; RV32I-NEXT: sw a4, 100(a0)
+; RV32I-NEXT: sw a5, 96(a0)
+; RV32I-NEXT: sw s9, 92(a0)
+; RV32I-NEXT: sw s8, 88(a0)
+; RV32I-NEXT: sw s7, 84(a0)
+; RV32I-NEXT: sw s6, 80(a0)
+; RV32I-NEXT: sw s5, 76(a0)
+; RV32I-NEXT: sw s4, 72(a0)
+; RV32I-NEXT: sw s3, 68(a0)
+; RV32I-NEXT: sw s2, 64(a0)
+; RV32I-NEXT: sw s1, 60(a0)
+; RV32I-NEXT: sw s0, 56(a0)
+; RV32I-NEXT: sw t6, 52(a0)
+; RV32I-NEXT: sw t5, 48(a0)
+; RV32I-NEXT: sw t4, 44(a0)
+; RV32I-NEXT: sw t3, 40(a0)
+; RV32I-NEXT: sw t2, 36(a0)
+; RV32I-NEXT: sw t1, 32(a0)
+; RV32I-NEXT: sw t0, 28(a0)
+; RV32I-NEXT: sw a7, 24(a0)
+; RV32I-NEXT: sw a6, 20(a0)
+; RV32I-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 16(a0)
+; RV32I-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 12(a0)
+; RV32I-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 8(a0)
+; RV32I-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw t0, 136(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw t1, 132(sp) # 4-byte Folded Reload
@@ -3244,84 +3206,82 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64I-NEXT: .cfi_offset t4, -208
; RV64I-NEXT: .cfi_offset t5, -216
; RV64I-NEXT: .cfi_offset t6, -224
-; RV64I-NEXT: lui a7, %hi(var_test_irq)
-; RV64I-NEXT: lw a0, %lo(var_test_irq)(a7)
-; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var_test_irq+4)(a7)
-; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var_test_irq+8)(a7)
-; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var_test_irq+12)(a7)
-; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addi a5, a7, %lo(var_test_irq)
-; RV64I-NEXT: lw a0, 16(a5)
-; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 20(a5)
-; RV64I-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw t0, 24(a5)
-; RV64I-NEXT: lw t1, 28(a5)
-; RV64I-NEXT: lw t2, 32(a5)
-; RV64I-NEXT: lw t3, 36(a5)
-; RV64I-NEXT: lw t4, 40(a5)
-; RV64I-NEXT: lw t5, 44(a5)
-; RV64I-NEXT: lw t6, 48(a5)
-; RV64I-NEXT: lw s0, 52(a5)
-; RV64I-NEXT: lw s1, 56(a5)
-; RV64I-NEXT: lw s2, 60(a5)
-; RV64I-NEXT: lw s3, 64(a5)
-; RV64I-NEXT: lw s4, 68(a5)
-; RV64I-NEXT: lw s5, 72(a5)
-; RV64I-NEXT: lw s6, 76(a5)
-; RV64I-NEXT: lw s7, 80(a5)
-; RV64I-NEXT: lw s8, 84(a5)
-; RV64I-NEXT: lw s9, 88(a5)
-; RV64I-NEXT: lw s10, 92(a5)
-; RV64I-NEXT: lw s11, 112(a5)
-; RV64I-NEXT: lw ra, 116(a5)
-; RV64I-NEXT: lw a3, 120(a5)
-; RV64I-NEXT: lw a0, 124(a5)
-; RV64I-NEXT: lw a6, 96(a5)
-; RV64I-NEXT: lw a4, 100(a5)
-; RV64I-NEXT: lw a2, 104(a5)
-; RV64I-NEXT: lw a1, 108(a5)
-; RV64I-NEXT: sw a0, 124(a5)
-; RV64I-NEXT: sw a3, 120(a5)
-; RV64I-NEXT: sw ra, 116(a5)
-; RV64I-NEXT: sw s11, 112(a5)
-; RV64I-NEXT: sw a1, 108(a5)
-; RV64I-NEXT: sw a2, 104(a5)
-; RV64I-NEXT: sw a4, 100(a5)
-; RV64I-NEXT: sw a6, 96(a5)
-; RV64I-NEXT: sw s10, 92(a5)
-; RV64I-NEXT: sw s9, 88(a5)
-; RV64I-NEXT: sw s8, 84(a5)
-; RV64I-NEXT: sw s7, 80(a5)
-; RV64I-NEXT: sw s6, 76(a5)
-; RV64I-NEXT: sw s5, 72(a5)
-; RV64I-NEXT: sw s4, 68(a5)
-; RV64I-NEXT: sw s3, 64(a5)
-; RV64I-NEXT: sw s2, 60(a5)
-; RV64I-NEXT: sw s1, 56(a5)
-; RV64I-NEXT: sw s0, 52(a5)
-; RV64I-NEXT: sw t6, 48(a5)
-; RV64I-NEXT: sw t5, 44(a5)
-; RV64I-NEXT: sw t4, 40(a5)
-; RV64I-NEXT: sw t3, 36(a5)
-; RV64I-NEXT: sw t2, 32(a5)
-; RV64I-NEXT: sw t1, 28(a5)
-; RV64I-NEXT: sw t0, 24(a5)
-; RV64I-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 20(a5)
-; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 16(a5)
-; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var_test_irq+12)(a7)
-; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var_test_irq+8)(a7)
-; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var_test_irq+4)(a7)
-; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var_test_irq)(a7)
+; RV64I-NEXT: lui a0, %hi(var_test_irq)
+; RV64I-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64I-NEXT: lw a1, 0(a0)
+; RV64I-NEXT: sd a1, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 4(a0)
+; RV64I-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 8(a0)
+; RV64I-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 12(a0)
+; RV64I-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 16(a0)
+; RV64I-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a6, 20(a0)
+; RV64I-NEXT: lw a7, 24(a0)
+; RV64I-NEXT: lw t0, 28(a0)
+; RV64I-NEXT: lw t1, 32(a0)
+; RV64I-NEXT: lw t2, 36(a0)
+; RV64I-NEXT: lw t3, 40(a0)
+; RV64I-NEXT: lw t4, 44(a0)
+; RV64I-NEXT: lw t5, 48(a0)
+; RV64I-NEXT: lw t6, 52(a0)
+; RV64I-NEXT: lw s0, 56(a0)
+; RV64I-NEXT: lw s1, 60(a0)
+; RV64I-NEXT: lw s2, 64(a0)
+; RV64I-NEXT: lw s3, 68(a0)
+; RV64I-NEXT: lw s4, 72(a0)
+; RV64I-NEXT: lw s5, 76(a0)
+; RV64I-NEXT: lw s6, 80(a0)
+; RV64I-NEXT: lw s7, 84(a0)
+; RV64I-NEXT: lw s8, 88(a0)
+; RV64I-NEXT: lw s9, 92(a0)
+; RV64I-NEXT: lw s10, 112(a0)
+; RV64I-NEXT: lw s11, 116(a0)
+; RV64I-NEXT: lw ra, 120(a0)
+; RV64I-NEXT: lw a1, 124(a0)
+; RV64I-NEXT: lw a5, 96(a0)
+; RV64I-NEXT: lw a4, 100(a0)
+; RV64I-NEXT: lw a3, 104(a0)
+; RV64I-NEXT: lw a2, 108(a0)
+; RV64I-NEXT: sw a1, 124(a0)
+; RV64I-NEXT: sw ra, 120(a0)
+; RV64I-NEXT: sw s11, 116(a0)
+; RV64I-NEXT: sw s10, 112(a0)
+; RV64I-NEXT: sw a2, 108(a0)
+; RV64I-NEXT: sw a3, 104(a0)
+; RV64I-NEXT: sw a4, 100(a0)
+; RV64I-NEXT: sw a5, 96(a0)
+; RV64I-NEXT: sw s9, 92(a0)
+; RV64I-NEXT: sw s8, 88(a0)
+; RV64I-NEXT: sw s7, 84(a0)
+; RV64I-NEXT: sw s6, 80(a0)
+; RV64I-NEXT: sw s5, 76(a0)
+; RV64I-NEXT: sw s4, 72(a0)
+; RV64I-NEXT: sw s3, 68(a0)
+; RV64I-NEXT: sw s2, 64(a0)
+; RV64I-NEXT: sw s1, 60(a0)
+; RV64I-NEXT: sw s0, 56(a0)
+; RV64I-NEXT: sw t6, 52(a0)
+; RV64I-NEXT: sw t5, 48(a0)
+; RV64I-NEXT: sw t4, 44(a0)
+; RV64I-NEXT: sw t3, 40(a0)
+; RV64I-NEXT: sw t2, 36(a0)
+; RV64I-NEXT: sw t1, 32(a0)
+; RV64I-NEXT: sw t0, 28(a0)
+; RV64I-NEXT: sw a7, 24(a0)
+; RV64I-NEXT: sw a6, 20(a0)
+; RV64I-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 16(a0)
+; RV64I-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 12(a0)
+; RV64I-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 8(a0)
+; RV64I-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 4(a0)
+; RV64I-NEXT: ld a1, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 0(a0)
; RV64I-NEXT: ld ra, 264(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld t0, 256(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld t1, 248(sp) # 8-byte Folded Reload
@@ -3404,84 +3364,82 @@ define void @callee_no_irq() {
; RV32IZCMP-NEXT: .cfi_offset s9, -12
; RV32IZCMP-NEXT: .cfi_offset s10, -8
; RV32IZCMP-NEXT: .cfi_offset s11, -4
-; RV32IZCMP-NEXT: lui t0, %hi(var_test_irq)
-; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV32IZCMP-NEXT: lw a0, 16(a5)
-; RV32IZCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw a0, 20(a5)
-; RV32IZCMP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw t4, 24(a5)
-; RV32IZCMP-NEXT: lw t5, 28(a5)
-; RV32IZCMP-NEXT: lw t6, 32(a5)
-; RV32IZCMP-NEXT: lw s2, 36(a5)
-; RV32IZCMP-NEXT: lw s3, 40(a5)
-; RV32IZCMP-NEXT: lw s4, 44(a5)
-; RV32IZCMP-NEXT: lw s5, 48(a5)
-; RV32IZCMP-NEXT: lw s6, 52(a5)
-; RV32IZCMP-NEXT: lw s7, 56(a5)
-; RV32IZCMP-NEXT: lw s8, 60(a5)
-; RV32IZCMP-NEXT: lw s9, 64(a5)
-; RV32IZCMP-NEXT: lw s10, 68(a5)
-; RV32IZCMP-NEXT: lw s11, 72(a5)
-; RV32IZCMP-NEXT: lw ra, 76(a5)
-; RV32IZCMP-NEXT: lw s1, 80(a5)
-; RV32IZCMP-NEXT: lw t3, 84(a5)
-; RV32IZCMP-NEXT: lw t2, 88(a5)
-; RV32IZCMP-NEXT: lw t1, 92(a5)
-; RV32IZCMP-NEXT: lw a7, 112(a5)
-; RV32IZCMP-NEXT: lw s0, 116(a5)
-; RV32IZCMP-NEXT: lw a3, 120(a5)
-; RV32IZCMP-NEXT: lw a0, 124(a5)
-; RV32IZCMP-NEXT: lw a6, 96(a5)
-; RV32IZCMP-NEXT: lw a4, 100(a5)
-; RV32IZCMP-NEXT: lw a2, 104(a5)
-; RV32IZCMP-NEXT: lw a1, 108(a5)
-; RV32IZCMP-NEXT: sw a0, 124(a5)
-; RV32IZCMP-NEXT: sw a3, 120(a5)
-; RV32IZCMP-NEXT: sw s0, 116(a5)
-; RV32IZCMP-NEXT: sw a7, 112(a5)
-; RV32IZCMP-NEXT: sw a1, 108(a5)
-; RV32IZCMP-NEXT: sw a2, 104(a5)
-; RV32IZCMP-NEXT: sw a4, 100(a5)
-; RV32IZCMP-NEXT: sw a6, 96(a5)
-; RV32IZCMP-NEXT: sw t1, 92(a5)
-; RV32IZCMP-NEXT: sw t2, 88(a5)
-; RV32IZCMP-NEXT: sw t3, 84(a5)
-; RV32IZCMP-NEXT: sw s1, 80(a5)
-; RV32IZCMP-NEXT: sw ra, 76(a5)
-; RV32IZCMP-NEXT: sw s11, 72(a5)
-; RV32IZCMP-NEXT: sw s10, 68(a5)
-; RV32IZCMP-NEXT: sw s9, 64(a5)
-; RV32IZCMP-NEXT: sw s8, 60(a5)
-; RV32IZCMP-NEXT: sw s7, 56(a5)
-; RV32IZCMP-NEXT: sw s6, 52(a5)
-; RV32IZCMP-NEXT: sw s5, 48(a5)
-; RV32IZCMP-NEXT: sw s4, 44(a5)
-; RV32IZCMP-NEXT: sw s3, 40(a5)
-; RV32IZCMP-NEXT: sw s2, 36(a5)
-; RV32IZCMP-NEXT: sw t6, 32(a5)
-; RV32IZCMP-NEXT: sw t5, 28(a5)
-; RV32IZCMP-NEXT: sw t4, 24(a5)
-; RV32IZCMP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 20(a5)
-; RV32IZCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, 16(a5)
-; RV32IZCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq)(t0)
+; RV32IZCMP-NEXT: lui a0, %hi(var_test_irq)
+; RV32IZCMP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32IZCMP-NEXT: lw a1, 0(a0)
+; RV32IZCMP-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 4(a0)
+; RV32IZCMP-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 8(a0)
+; RV32IZCMP-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 12(a0)
+; RV32IZCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw a1, 16(a0)
+; RV32IZCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-NEXT: lw t3, 20(a0)
+; RV32IZCMP-NEXT: lw t4, 24(a0)
+; RV32IZCMP-NEXT: lw t5, 28(a0)
+; RV32IZCMP-NEXT: lw t6, 32(a0)
+; RV32IZCMP-NEXT: lw s2, 36(a0)
+; RV32IZCMP-NEXT: lw s3, 40(a0)
+; RV32IZCMP-NEXT: lw s4, 44(a0)
+; RV32IZCMP-NEXT: lw s5, 48(a0)
+; RV32IZCMP-NEXT: lw s6, 52(a0)
+; RV32IZCMP-NEXT: lw s7, 56(a0)
+; RV32IZCMP-NEXT: lw s8, 60(a0)
+; RV32IZCMP-NEXT: lw s9, 64(a0)
+; RV32IZCMP-NEXT: lw s10, 68(a0)
+; RV32IZCMP-NEXT: lw s11, 72(a0)
+; RV32IZCMP-NEXT: lw ra, 76(a0)
+; RV32IZCMP-NEXT: lw t2, 80(a0)
+; RV32IZCMP-NEXT: lw s0, 84(a0)
+; RV32IZCMP-NEXT: lw s1, 88(a0)
+; RV32IZCMP-NEXT: lw t1, 92(a0)
+; RV32IZCMP-NEXT: lw t0, 112(a0)
+; RV32IZCMP-NEXT: lw a5, 116(a0)
+; RV32IZCMP-NEXT: lw a3, 120(a0)
+; RV32IZCMP-NEXT: lw a1, 124(a0)
+; RV32IZCMP-NEXT: lw a7, 96(a0)
+; RV32IZCMP-NEXT: lw a6, 100(a0)
+; RV32IZCMP-NEXT: lw a4, 104(a0)
+; RV32IZCMP-NEXT: lw a2, 108(a0)
+; RV32IZCMP-NEXT: sw a1, 124(a0)
+; RV32IZCMP-NEXT: sw a3, 120(a0)
+; RV32IZCMP-NEXT: sw a5, 116(a0)
+; RV32IZCMP-NEXT: sw t0, 112(a0)
+; RV32IZCMP-NEXT: sw a2, 108(a0)
+; RV32IZCMP-NEXT: sw a4, 104(a0)
+; RV32IZCMP-NEXT: sw a6, 100(a0)
+; RV32IZCMP-NEXT: sw a7, 96(a0)
+; RV32IZCMP-NEXT: sw t1, 92(a0)
+; RV32IZCMP-NEXT: sw s1, 88(a0)
+; RV32IZCMP-NEXT: sw s0, 84(a0)
+; RV32IZCMP-NEXT: sw t2, 80(a0)
+; RV32IZCMP-NEXT: sw ra, 76(a0)
+; RV32IZCMP-NEXT: sw s11, 72(a0)
+; RV32IZCMP-NEXT: sw s10, 68(a0)
+; RV32IZCMP-NEXT: sw s9, 64(a0)
+; RV32IZCMP-NEXT: sw s8, 60(a0)
+; RV32IZCMP-NEXT: sw s7, 56(a0)
+; RV32IZCMP-NEXT: sw s6, 52(a0)
+; RV32IZCMP-NEXT: sw s5, 48(a0)
+; RV32IZCMP-NEXT: sw s4, 44(a0)
+; RV32IZCMP-NEXT: sw s3, 40(a0)
+; RV32IZCMP-NEXT: sw s2, 36(a0)
+; RV32IZCMP-NEXT: sw t6, 32(a0)
+; RV32IZCMP-NEXT: sw t5, 28(a0)
+; RV32IZCMP-NEXT: sw t4, 24(a0)
+; RV32IZCMP-NEXT: sw t3, 20(a0)
+; RV32IZCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 16(a0)
+; RV32IZCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 12(a0)
+; RV32IZCMP-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 8(a0)
+; RV32IZCMP-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 4(a0)
+; RV32IZCMP-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; RV32IZCMP-NEXT: sw a1, 0(a0)
; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 96
;
; RV64IZCMP-LABEL: callee_no_irq:
@@ -3501,84 +3459,82 @@ define void @callee_no_irq() {
; RV64IZCMP-NEXT: .cfi_offset s9, -24
; RV64IZCMP-NEXT: .cfi_offset s10, -16
; RV64IZCMP-NEXT: .cfi_offset s11, -8
-; RV64IZCMP-NEXT: lui t0, %hi(var_test_irq)
-; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV64IZCMP-NEXT: lw a0, 16(a5)
-; RV64IZCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw a0, 20(a5)
-; RV64IZCMP-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw t4, 24(a5)
-; RV64IZCMP-NEXT: lw t5, 28(a5)
-; RV64IZCMP-NEXT: lw t6, 32(a5)
-; RV64IZCMP-NEXT: lw s2, 36(a5)
-; RV64IZCMP-NEXT: lw s3, 40(a5)
-; RV64IZCMP-NEXT: lw s4, 44(a5)
-; RV64IZCMP-NEXT: lw s5, 48(a5)
-; RV64IZCMP-NEXT: lw s6, 52(a5)
-; RV64IZCMP-NEXT: lw s7, 56(a5)
-; RV64IZCMP-NEXT: lw s8, 60(a5)
-; RV64IZCMP-NEXT: lw s9, 64(a5)
-; RV64IZCMP-NEXT: lw s10, 68(a5)
-; RV64IZCMP-NEXT: lw s11, 72(a5)
-; RV64IZCMP-NEXT: lw ra, 76(a5)
-; RV64IZCMP-NEXT: lw s1, 80(a5)
-; RV64IZCMP-NEXT: lw t3, 84(a5)
-; RV64IZCMP-NEXT: lw t2, 88(a5)
-; RV64IZCMP-NEXT: lw t1, 92(a5)
-; RV64IZCMP-NEXT: lw a7, 112(a5)
-; RV64IZCMP-NEXT: lw s0, 116(a5)
-; RV64IZCMP-NEXT: lw a3, 120(a5)
-; RV64IZCMP-NEXT: lw a0, 124(a5)
-; RV64IZCMP-NEXT: lw a6, 96(a5)
-; RV64IZCMP-NEXT: lw a4, 100(a5)
-; RV64IZCMP-NEXT: lw a2, 104(a5)
-; RV64IZCMP-NEXT: lw a1, 108(a5)
-; RV64IZCMP-NEXT: sw a0, 124(a5)
-; RV64IZCMP-NEXT: sw a3, 120(a5)
-; RV64IZCMP-NEXT: sw s0, 116(a5)
-; RV64IZCMP-NEXT: sw a7, 112(a5)
-; RV64IZCMP-NEXT: sw a1, 108(a5)
-; RV64IZCMP-NEXT: sw a2, 104(a5)
-; RV64IZCMP-NEXT: sw a4, 100(a5)
-; RV64IZCMP-NEXT: sw a6, 96(a5)
-; RV64IZCMP-NEXT: sw t1, 92(a5)
-; RV64IZCMP-NEXT: sw t2, 88(a5)
-; RV64IZCMP-NEXT: sw t3, 84(a5)
-; RV64IZCMP-NEXT: sw s1, 80(a5)
-; RV64IZCMP-NEXT: sw ra, 76(a5)
-; RV64IZCMP-NEXT: sw s11, 72(a5)
-; RV64IZCMP-NEXT: sw s10, 68(a5)
-; RV64IZCMP-NEXT: sw s9, 64(a5)
-; RV64IZCMP-NEXT: sw s8, 60(a5)
-; RV64IZCMP-NEXT: sw s7, 56(a5)
-; RV64IZCMP-NEXT: sw s6, 52(a5)
-; RV64IZCMP-NEXT: sw s5, 48(a5)
-; RV64IZCMP-NEXT: sw s4, 44(a5)
-; RV64IZCMP-NEXT: sw s3, 40(a5)
-; RV64IZCMP-NEXT: sw s2, 36(a5)
-; RV64IZCMP-NEXT: sw t6, 32(a5)
-; RV64IZCMP-NEXT: sw t5, 28(a5)
-; RV64IZCMP-NEXT: sw t4, 24(a5)
-; RV64IZCMP-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 20(a5)
-; RV64IZCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, 16(a5)
-; RV64IZCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq)(t0)
+; RV64IZCMP-NEXT: lui a0, %hi(var_test_irq)
+; RV64IZCMP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64IZCMP-NEXT: lw a1, 0(a0)
+; RV64IZCMP-NEXT: sd a1, 40(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 4(a0)
+; RV64IZCMP-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 8(a0)
+; RV64IZCMP-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 12(a0)
+; RV64IZCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw a1, 16(a0)
+; RV64IZCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-NEXT: lw t3, 20(a0)
+; RV64IZCMP-NEXT: lw t4, 24(a0)
+; RV64IZCMP-NEXT: lw t5, 28(a0)
+; RV64IZCMP-NEXT: lw t6, 32(a0)
+; RV64IZCMP-NEXT: lw s2, 36(a0)
+; RV64IZCMP-NEXT: lw s3, 40(a0)
+; RV64IZCMP-NEXT: lw s4, 44(a0)
+; RV64IZCMP-NEXT: lw s5, 48(a0)
+; RV64IZCMP-NEXT: lw s6, 52(a0)
+; RV64IZCMP-NEXT: lw s7, 56(a0)
+; RV64IZCMP-NEXT: lw s8, 60(a0)
+; RV64IZCMP-NEXT: lw s9, 64(a0)
+; RV64IZCMP-NEXT: lw s10, 68(a0)
+; RV64IZCMP-NEXT: lw s11, 72(a0)
+; RV64IZCMP-NEXT: lw ra, 76(a0)
+; RV64IZCMP-NEXT: lw t2, 80(a0)
+; RV64IZCMP-NEXT: lw s0, 84(a0)
+; RV64IZCMP-NEXT: lw s1, 88(a0)
+; RV64IZCMP-NEXT: lw t1, 92(a0)
+; RV64IZCMP-NEXT: lw t0, 112(a0)
+; RV64IZCMP-NEXT: lw a5, 116(a0)
+; RV64IZCMP-NEXT: lw a3, 120(a0)
+; RV64IZCMP-NEXT: lw a1, 124(a0)
+; RV64IZCMP-NEXT: lw a7, 96(a0)
+; RV64IZCMP-NEXT: lw a6, 100(a0)
+; RV64IZCMP-NEXT: lw a4, 104(a0)
+; RV64IZCMP-NEXT: lw a2, 108(a0)
+; RV64IZCMP-NEXT: sw a1, 124(a0)
+; RV64IZCMP-NEXT: sw a3, 120(a0)
+; RV64IZCMP-NEXT: sw a5, 116(a0)
+; RV64IZCMP-NEXT: sw t0, 112(a0)
+; RV64IZCMP-NEXT: sw a2, 108(a0)
+; RV64IZCMP-NEXT: sw a4, 104(a0)
+; RV64IZCMP-NEXT: sw a6, 100(a0)
+; RV64IZCMP-NEXT: sw a7, 96(a0)
+; RV64IZCMP-NEXT: sw t1, 92(a0)
+; RV64IZCMP-NEXT: sw s1, 88(a0)
+; RV64IZCMP-NEXT: sw s0, 84(a0)
+; RV64IZCMP-NEXT: sw t2, 80(a0)
+; RV64IZCMP-NEXT: sw ra, 76(a0)
+; RV64IZCMP-NEXT: sw s11, 72(a0)
+; RV64IZCMP-NEXT: sw s10, 68(a0)
+; RV64IZCMP-NEXT: sw s9, 64(a0)
+; RV64IZCMP-NEXT: sw s8, 60(a0)
+; RV64IZCMP-NEXT: sw s7, 56(a0)
+; RV64IZCMP-NEXT: sw s6, 52(a0)
+; RV64IZCMP-NEXT: sw s5, 48(a0)
+; RV64IZCMP-NEXT: sw s4, 44(a0)
+; RV64IZCMP-NEXT: sw s3, 40(a0)
+; RV64IZCMP-NEXT: sw s2, 36(a0)
+; RV64IZCMP-NEXT: sw t6, 32(a0)
+; RV64IZCMP-NEXT: sw t5, 28(a0)
+; RV64IZCMP-NEXT: sw t4, 24(a0)
+; RV64IZCMP-NEXT: sw t3, 20(a0)
+; RV64IZCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 16(a0)
+; RV64IZCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 12(a0)
+; RV64IZCMP-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 8(a0)
+; RV64IZCMP-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 4(a0)
+; RV64IZCMP-NEXT: ld a1, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-NEXT: sw a1, 0(a0)
; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 160
;
; RV32IZCMP-SR-LABEL: callee_no_irq:
@@ -3598,84 +3554,82 @@ define void @callee_no_irq() {
; RV32IZCMP-SR-NEXT: .cfi_offset s9, -12
; RV32IZCMP-SR-NEXT: .cfi_offset s10, -8
; RV32IZCMP-SR-NEXT: .cfi_offset s11, -4
-; RV32IZCMP-SR-NEXT: lui t0, %hi(var_test_irq)
-; RV32IZCMP-SR-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV32IZCMP-SR-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-SR-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-SR-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-SR-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV32IZCMP-SR-NEXT: lw a0, 16(a5)
-; RV32IZCMP-SR-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw a0, 20(a5)
-; RV32IZCMP-SR-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw t4, 24(a5)
-; RV32IZCMP-SR-NEXT: lw t5, 28(a5)
-; RV32IZCMP-SR-NEXT: lw t6, 32(a5)
-; RV32IZCMP-SR-NEXT: lw s2, 36(a5)
-; RV32IZCMP-SR-NEXT: lw s3, 40(a5)
-; RV32IZCMP-SR-NEXT: lw s4, 44(a5)
-; RV32IZCMP-SR-NEXT: lw s5, 48(a5)
-; RV32IZCMP-SR-NEXT: lw s6, 52(a5)
-; RV32IZCMP-SR-NEXT: lw s7, 56(a5)
-; RV32IZCMP-SR-NEXT: lw s8, 60(a5)
-; RV32IZCMP-SR-NEXT: lw s9, 64(a5)
-; RV32IZCMP-SR-NEXT: lw s10, 68(a5)
-; RV32IZCMP-SR-NEXT: lw s11, 72(a5)
-; RV32IZCMP-SR-NEXT: lw ra, 76(a5)
-; RV32IZCMP-SR-NEXT: lw s1, 80(a5)
-; RV32IZCMP-SR-NEXT: lw t3, 84(a5)
-; RV32IZCMP-SR-NEXT: lw t2, 88(a5)
-; RV32IZCMP-SR-NEXT: lw t1, 92(a5)
-; RV32IZCMP-SR-NEXT: lw a7, 112(a5)
-; RV32IZCMP-SR-NEXT: lw s0, 116(a5)
-; RV32IZCMP-SR-NEXT: lw a3, 120(a5)
-; RV32IZCMP-SR-NEXT: lw a0, 124(a5)
-; RV32IZCMP-SR-NEXT: lw a6, 96(a5)
-; RV32IZCMP-SR-NEXT: lw a4, 100(a5)
-; RV32IZCMP-SR-NEXT: lw a2, 104(a5)
-; RV32IZCMP-SR-NEXT: lw a1, 108(a5)
-; RV32IZCMP-SR-NEXT: sw a0, 124(a5)
-; RV32IZCMP-SR-NEXT: sw a3, 120(a5)
-; RV32IZCMP-SR-NEXT: sw s0, 116(a5)
-; RV32IZCMP-SR-NEXT: sw a7, 112(a5)
-; RV32IZCMP-SR-NEXT: sw a1, 108(a5)
-; RV32IZCMP-SR-NEXT: sw a2, 104(a5)
-; RV32IZCMP-SR-NEXT: sw a4, 100(a5)
-; RV32IZCMP-SR-NEXT: sw a6, 96(a5)
-; RV32IZCMP-SR-NEXT: sw t1, 92(a5)
-; RV32IZCMP-SR-NEXT: sw t2, 88(a5)
-; RV32IZCMP-SR-NEXT: sw t3, 84(a5)
-; RV32IZCMP-SR-NEXT: sw s1, 80(a5)
-; RV32IZCMP-SR-NEXT: sw ra, 76(a5)
-; RV32IZCMP-SR-NEXT: sw s11, 72(a5)
-; RV32IZCMP-SR-NEXT: sw s10, 68(a5)
-; RV32IZCMP-SR-NEXT: sw s9, 64(a5)
-; RV32IZCMP-SR-NEXT: sw s8, 60(a5)
-; RV32IZCMP-SR-NEXT: sw s7, 56(a5)
-; RV32IZCMP-SR-NEXT: sw s6, 52(a5)
-; RV32IZCMP-SR-NEXT: sw s5, 48(a5)
-; RV32IZCMP-SR-NEXT: sw s4, 44(a5)
-; RV32IZCMP-SR-NEXT: sw s3, 40(a5)
-; RV32IZCMP-SR-NEXT: sw s2, 36(a5)
-; RV32IZCMP-SR-NEXT: sw t6, 32(a5)
-; RV32IZCMP-SR-NEXT: sw t5, 28(a5)
-; RV32IZCMP-SR-NEXT: sw t4, 24(a5)
-; RV32IZCMP-SR-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, 20(a5)
-; RV32IZCMP-SR-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, 16(a5)
-; RV32IZCMP-SR-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV32IZCMP-SR-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV32IZCMP-SR-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV32IZCMP-SR-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IZCMP-SR-NEXT: sw a0, %lo(var_test_irq)(t0)
+; RV32IZCMP-SR-NEXT: lui a0, %hi(var_test_irq)
+; RV32IZCMP-SR-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32IZCMP-SR-NEXT: lw a1, 0(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: lw a1, 4(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: lw a1, 8(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: lw a1, 12(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: lw a1, 16(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-SR-NEXT: lw t3, 20(a0)
+; RV32IZCMP-SR-NEXT: lw t4, 24(a0)
+; RV32IZCMP-SR-NEXT: lw t5, 28(a0)
+; RV32IZCMP-SR-NEXT: lw t6, 32(a0)
+; RV32IZCMP-SR-NEXT: lw s2, 36(a0)
+; RV32IZCMP-SR-NEXT: lw s3, 40(a0)
+; RV32IZCMP-SR-NEXT: lw s4, 44(a0)
+; RV32IZCMP-SR-NEXT: lw s5, 48(a0)
+; RV32IZCMP-SR-NEXT: lw s6, 52(a0)
+; RV32IZCMP-SR-NEXT: lw s7, 56(a0)
+; RV32IZCMP-SR-NEXT: lw s8, 60(a0)
+; RV32IZCMP-SR-NEXT: lw s9, 64(a0)
+; RV32IZCMP-SR-NEXT: lw s10, 68(a0)
+; RV32IZCMP-SR-NEXT: lw s11, 72(a0)
+; RV32IZCMP-SR-NEXT: lw ra, 76(a0)
+; RV32IZCMP-SR-NEXT: lw t2, 80(a0)
+; RV32IZCMP-SR-NEXT: lw s0, 84(a0)
+; RV32IZCMP-SR-NEXT: lw s1, 88(a0)
+; RV32IZCMP-SR-NEXT: lw t1, 92(a0)
+; RV32IZCMP-SR-NEXT: lw t0, 112(a0)
+; RV32IZCMP-SR-NEXT: lw a5, 116(a0)
+; RV32IZCMP-SR-NEXT: lw a3, 120(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 124(a0)
+; RV32IZCMP-SR-NEXT: lw a7, 96(a0)
+; RV32IZCMP-SR-NEXT: lw a6, 100(a0)
+; RV32IZCMP-SR-NEXT: lw a4, 104(a0)
+; RV32IZCMP-SR-NEXT: lw a2, 108(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 124(a0)
+; RV32IZCMP-SR-NEXT: sw a3, 120(a0)
+; RV32IZCMP-SR-NEXT: sw a5, 116(a0)
+; RV32IZCMP-SR-NEXT: sw t0, 112(a0)
+; RV32IZCMP-SR-NEXT: sw a2, 108(a0)
+; RV32IZCMP-SR-NEXT: sw a4, 104(a0)
+; RV32IZCMP-SR-NEXT: sw a6, 100(a0)
+; RV32IZCMP-SR-NEXT: sw a7, 96(a0)
+; RV32IZCMP-SR-NEXT: sw t1, 92(a0)
+; RV32IZCMP-SR-NEXT: sw s1, 88(a0)
+; RV32IZCMP-SR-NEXT: sw s0, 84(a0)
+; RV32IZCMP-SR-NEXT: sw t2, 80(a0)
+; RV32IZCMP-SR-NEXT: sw ra, 76(a0)
+; RV32IZCMP-SR-NEXT: sw s11, 72(a0)
+; RV32IZCMP-SR-NEXT: sw s10, 68(a0)
+; RV32IZCMP-SR-NEXT: sw s9, 64(a0)
+; RV32IZCMP-SR-NEXT: sw s8, 60(a0)
+; RV32IZCMP-SR-NEXT: sw s7, 56(a0)
+; RV32IZCMP-SR-NEXT: sw s6, 52(a0)
+; RV32IZCMP-SR-NEXT: sw s5, 48(a0)
+; RV32IZCMP-SR-NEXT: sw s4, 44(a0)
+; RV32IZCMP-SR-NEXT: sw s3, 40(a0)
+; RV32IZCMP-SR-NEXT: sw s2, 36(a0)
+; RV32IZCMP-SR-NEXT: sw t6, 32(a0)
+; RV32IZCMP-SR-NEXT: sw t5, 28(a0)
+; RV32IZCMP-SR-NEXT: sw t4, 24(a0)
+; RV32IZCMP-SR-NEXT: sw t3, 20(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: sw a1, 16(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: sw a1, 12(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: sw a1, 8(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: sw a1, 4(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; RV32IZCMP-SR-NEXT: sw a1, 0(a0)
; RV32IZCMP-SR-NEXT: cm.popret {ra, s0-s11}, 96
;
; RV64IZCMP-SR-LABEL: callee_no_irq:
@@ -3695,84 +3649,82 @@ define void @callee_no_irq() {
; RV64IZCMP-SR-NEXT: .cfi_offset s9, -24
; RV64IZCMP-SR-NEXT: .cfi_offset s10, -16
; RV64IZCMP-SR-NEXT: .cfi_offset s11, -8
-; RV64IZCMP-SR-NEXT: lui t0, %hi(var_test_irq)
-; RV64IZCMP-SR-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV64IZCMP-SR-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-SR-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-SR-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-SR-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV64IZCMP-SR-NEXT: lw a0, 16(a5)
-; RV64IZCMP-SR-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw a0, 20(a5)
-; RV64IZCMP-SR-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw t4, 24(a5)
-; RV64IZCMP-SR-NEXT: lw t5, 28(a5)
-; RV64IZCMP-SR-NEXT: lw t6, 32(a5)
-; RV64IZCMP-SR-NEXT: lw s2, 36(a5)
-; RV64IZCMP-SR-NEXT: lw s3, 40(a5)
-; RV64IZCMP-SR-NEXT: lw s4, 44(a5)
-; RV64IZCMP-SR-NEXT: lw s5, 48(a5)
-; RV64IZCMP-SR-NEXT: lw s6, 52(a5)
-; RV64IZCMP-SR-NEXT: lw s7, 56(a5)
-; RV64IZCMP-SR-NEXT: lw s8, 60(a5)
-; RV64IZCMP-SR-NEXT: lw s9, 64(a5)
-; RV64IZCMP-SR-NEXT: lw s10, 68(a5)
-; RV64IZCMP-SR-NEXT: lw s11, 72(a5)
-; RV64IZCMP-SR-NEXT: lw ra, 76(a5)
-; RV64IZCMP-SR-NEXT: lw s1, 80(a5)
-; RV64IZCMP-SR-NEXT: lw t3, 84(a5)
-; RV64IZCMP-SR-NEXT: lw t2, 88(a5)
-; RV64IZCMP-SR-NEXT: lw t1, 92(a5)
-; RV64IZCMP-SR-NEXT: lw a7, 112(a5)
-; RV64IZCMP-SR-NEXT: lw s0, 116(a5)
-; RV64IZCMP-SR-NEXT: lw a3, 120(a5)
-; RV64IZCMP-SR-NEXT: lw a0, 124(a5)
-; RV64IZCMP-SR-NEXT: lw a6, 96(a5)
-; RV64IZCMP-SR-NEXT: lw a4, 100(a5)
-; RV64IZCMP-SR-NEXT: lw a2, 104(a5)
-; RV64IZCMP-SR-NEXT: lw a1, 108(a5)
-; RV64IZCMP-SR-NEXT: sw a0, 124(a5)
-; RV64IZCMP-SR-NEXT: sw a3, 120(a5)
-; RV64IZCMP-SR-NEXT: sw s0, 116(a5)
-; RV64IZCMP-SR-NEXT: sw a7, 112(a5)
-; RV64IZCMP-SR-NEXT: sw a1, 108(a5)
-; RV64IZCMP-SR-NEXT: sw a2, 104(a5)
-; RV64IZCMP-SR-NEXT: sw a4, 100(a5)
-; RV64IZCMP-SR-NEXT: sw a6, 96(a5)
-; RV64IZCMP-SR-NEXT: sw t1, 92(a5)
-; RV64IZCMP-SR-NEXT: sw t2, 88(a5)
-; RV64IZCMP-SR-NEXT: sw t3, 84(a5)
-; RV64IZCMP-SR-NEXT: sw s1, 80(a5)
-; RV64IZCMP-SR-NEXT: sw ra, 76(a5)
-; RV64IZCMP-SR-NEXT: sw s11, 72(a5)
-; RV64IZCMP-SR-NEXT: sw s10, 68(a5)
-; RV64IZCMP-SR-NEXT: sw s9, 64(a5)
-; RV64IZCMP-SR-NEXT: sw s8, 60(a5)
-; RV64IZCMP-SR-NEXT: sw s7, 56(a5)
-; RV64IZCMP-SR-NEXT: sw s6, 52(a5)
-; RV64IZCMP-SR-NEXT: sw s5, 48(a5)
-; RV64IZCMP-SR-NEXT: sw s4, 44(a5)
-; RV64IZCMP-SR-NEXT: sw s3, 40(a5)
-; RV64IZCMP-SR-NEXT: sw s2, 36(a5)
-; RV64IZCMP-SR-NEXT: sw t6, 32(a5)
-; RV64IZCMP-SR-NEXT: sw t5, 28(a5)
-; RV64IZCMP-SR-NEXT: sw t4, 24(a5)
-; RV64IZCMP-SR-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, 20(a5)
-; RV64IZCMP-SR-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, 16(a5)
-; RV64IZCMP-SR-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV64IZCMP-SR-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV64IZCMP-SR-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV64IZCMP-SR-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IZCMP-SR-NEXT: sw a0, %lo(var_test_irq)(t0)
+; RV64IZCMP-SR-NEXT: lui a0, %hi(var_test_irq)
+; RV64IZCMP-SR-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64IZCMP-SR-NEXT: lw a1, 0(a0)
+; RV64IZCMP-SR-NEXT: sd a1, 40(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: lw a1, 4(a0)
+; RV64IZCMP-SR-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: lw a1, 8(a0)
+; RV64IZCMP-SR-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: lw a1, 12(a0)
+; RV64IZCMP-SR-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: lw a1, 16(a0)
+; RV64IZCMP-SR-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-SR-NEXT: lw t3, 20(a0)
+; RV64IZCMP-SR-NEXT: lw t4, 24(a0)
+; RV64IZCMP-SR-NEXT: lw t5, 28(a0)
+; RV64IZCMP-SR-NEXT: lw t6, 32(a0)
+; RV64IZCMP-SR-NEXT: lw s2, 36(a0)
+; RV64IZCMP-SR-NEXT: lw s3, 40(a0)
+; RV64IZCMP-SR-NEXT: lw s4, 44(a0)
+; RV64IZCMP-SR-NEXT: lw s5, 48(a0)
+; RV64IZCMP-SR-NEXT: lw s6, 52(a0)
+; RV64IZCMP-SR-NEXT: lw s7, 56(a0)
+; RV64IZCMP-SR-NEXT: lw s8, 60(a0)
+; RV64IZCMP-SR-NEXT: lw s9, 64(a0)
+; RV64IZCMP-SR-NEXT: lw s10, 68(a0)
+; RV64IZCMP-SR-NEXT: lw s11, 72(a0)
+; RV64IZCMP-SR-NEXT: lw ra, 76(a0)
+; RV64IZCMP-SR-NEXT: lw t2, 80(a0)
+; RV64IZCMP-SR-NEXT: lw s0, 84(a0)
+; RV64IZCMP-SR-NEXT: lw s1, 88(a0)
+; RV64IZCMP-SR-NEXT: lw t1, 92(a0)
+; RV64IZCMP-SR-NEXT: lw t0, 112(a0)
+; RV64IZCMP-SR-NEXT: lw a5, 116(a0)
+; RV64IZCMP-SR-NEXT: lw a3, 120(a0)
+; RV64IZCMP-SR-NEXT: lw a1, 124(a0)
+; RV64IZCMP-SR-NEXT: lw a7, 96(a0)
+; RV64IZCMP-SR-NEXT: lw a6, 100(a0)
+; RV64IZCMP-SR-NEXT: lw a4, 104(a0)
+; RV64IZCMP-SR-NEXT: lw a2, 108(a0)
+; RV64IZCMP-SR-NEXT: sw a1, 124(a0)
+; RV64IZCMP-SR-NEXT: sw a3, 120(a0)
+; RV64IZCMP-SR-NEXT: sw a5, 116(a0)
+; RV64IZCMP-SR-NEXT: sw t0, 112(a0)
+; RV64IZCMP-SR-NEXT: sw a2, 108(a0)
+; RV64IZCMP-SR-NEXT: sw a4, 104(a0)
+; RV64IZCMP-SR-NEXT: sw a6, 100(a0)
+; RV64IZCMP-SR-NEXT: sw a7, 96(a0)
+; RV64IZCMP-SR-NEXT: sw t1, 92(a0)
+; RV64IZCMP-SR-NEXT: sw s1, 88(a0)
+; RV64IZCMP-SR-NEXT: sw s0, 84(a0)
+; RV64IZCMP-SR-NEXT: sw t2, 80(a0)
+; RV64IZCMP-SR-NEXT: sw ra, 76(a0)
+; RV64IZCMP-SR-NEXT: sw s11, 72(a0)
+; RV64IZCMP-SR-NEXT: sw s10, 68(a0)
+; RV64IZCMP-SR-NEXT: sw s9, 64(a0)
+; RV64IZCMP-SR-NEXT: sw s8, 60(a0)
+; RV64IZCMP-SR-NEXT: sw s7, 56(a0)
+; RV64IZCMP-SR-NEXT: sw s6, 52(a0)
+; RV64IZCMP-SR-NEXT: sw s5, 48(a0)
+; RV64IZCMP-SR-NEXT: sw s4, 44(a0)
+; RV64IZCMP-SR-NEXT: sw s3, 40(a0)
+; RV64IZCMP-SR-NEXT: sw s2, 36(a0)
+; RV64IZCMP-SR-NEXT: sw t6, 32(a0)
+; RV64IZCMP-SR-NEXT: sw t5, 28(a0)
+; RV64IZCMP-SR-NEXT: sw t4, 24(a0)
+; RV64IZCMP-SR-NEXT: sw t3, 20(a0)
+; RV64IZCMP-SR-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: sw a1, 16(a0)
+; RV64IZCMP-SR-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: sw a1, 12(a0)
+; RV64IZCMP-SR-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: sw a1, 8(a0)
+; RV64IZCMP-SR-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: sw a1, 4(a0)
+; RV64IZCMP-SR-NEXT: ld a1, 40(sp) # 8-byte Folded Reload
+; RV64IZCMP-SR-NEXT: sw a1, 0(a0)
; RV64IZCMP-SR-NEXT: cm.popret {ra, s0-s11}, 160
;
; RV32I-LABEL: callee_no_irq:
@@ -3805,84 +3757,82 @@ define void @callee_no_irq() {
; RV32I-NEXT: .cfi_offset s9, -44
; RV32I-NEXT: .cfi_offset s10, -48
; RV32I-NEXT: .cfi_offset s11, -52
-; RV32I-NEXT: lui a7, %hi(var_test_irq)
-; RV32I-NEXT: lw a0, %lo(var_test_irq)(a7)
-; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var_test_irq+4)(a7)
-; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var_test_irq+8)(a7)
-; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, %lo(var_test_irq+12)(a7)
-; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: addi a5, a7, %lo(var_test_irq)
-; RV32I-NEXT: lw a0, 16(a5)
-; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw a0, 20(a5)
-; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32I-NEXT: lw t0, 24(a5)
-; RV32I-NEXT: lw t1, 28(a5)
-; RV32I-NEXT: lw t2, 32(a5)
-; RV32I-NEXT: lw t3, 36(a5)
-; RV32I-NEXT: lw t4, 40(a5)
-; RV32I-NEXT: lw t5, 44(a5)
-; RV32I-NEXT: lw t6, 48(a5)
-; RV32I-NEXT: lw s0, 52(a5)
-; RV32I-NEXT: lw s1, 56(a5)
-; RV32I-NEXT: lw s2, 60(a5)
-; RV32I-NEXT: lw s3, 64(a5)
-; RV32I-NEXT: lw s4, 68(a5)
-; RV32I-NEXT: lw s5, 72(a5)
-; RV32I-NEXT: lw s6, 76(a5)
-; RV32I-NEXT: lw s7, 80(a5)
-; RV32I-NEXT: lw s8, 84(a5)
-; RV32I-NEXT: lw s9, 88(a5)
-; RV32I-NEXT: lw s10, 92(a5)
-; RV32I-NEXT: lw s11, 112(a5)
-; RV32I-NEXT: lw ra, 116(a5)
-; RV32I-NEXT: lw a3, 120(a5)
-; RV32I-NEXT: lw a0, 124(a5)
-; RV32I-NEXT: lw a6, 96(a5)
-; RV32I-NEXT: lw a4, 100(a5)
-; RV32I-NEXT: lw a2, 104(a5)
-; RV32I-NEXT: lw a1, 108(a5)
-; RV32I-NEXT: sw a0, 124(a5)
-; RV32I-NEXT: sw a3, 120(a5)
-; RV32I-NEXT: sw ra, 116(a5)
-; RV32I-NEXT: sw s11, 112(a5)
-; RV32I-NEXT: sw a1, 108(a5)
-; RV32I-NEXT: sw a2, 104(a5)
-; RV32I-NEXT: sw a4, 100(a5)
-; RV32I-NEXT: sw a6, 96(a5)
-; RV32I-NEXT: sw s10, 92(a5)
-; RV32I-NEXT: sw s9, 88(a5)
-; RV32I-NEXT: sw s8, 84(a5)
-; RV32I-NEXT: sw s7, 80(a5)
-; RV32I-NEXT: sw s6, 76(a5)
-; RV32I-NEXT: sw s5, 72(a5)
-; RV32I-NEXT: sw s4, 68(a5)
-; RV32I-NEXT: sw s3, 64(a5)
-; RV32I-NEXT: sw s2, 60(a5)
-; RV32I-NEXT: sw s1, 56(a5)
-; RV32I-NEXT: sw s0, 52(a5)
-; RV32I-NEXT: sw t6, 48(a5)
-; RV32I-NEXT: sw t5, 44(a5)
-; RV32I-NEXT: sw t4, 40(a5)
-; RV32I-NEXT: sw t3, 36(a5)
-; RV32I-NEXT: sw t2, 32(a5)
-; RV32I-NEXT: sw t1, 28(a5)
-; RV32I-NEXT: sw t0, 24(a5)
-; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 20(a5)
-; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, 16(a5)
-; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var_test_irq+12)(a7)
-; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var_test_irq+8)(a7)
-; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var_test_irq+4)(a7)
-; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: sw a0, %lo(var_test_irq)(a7)
+; RV32I-NEXT: lui a0, %hi(var_test_irq)
+; RV32I-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32I-NEXT: lw a1, 0(a0)
+; RV32I-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 4(a0)
+; RV32I-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 8(a0)
+; RV32I-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 12(a0)
+; RV32I-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a1, 16(a0)
+; RV32I-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a6, 20(a0)
+; RV32I-NEXT: lw a7, 24(a0)
+; RV32I-NEXT: lw t0, 28(a0)
+; RV32I-NEXT: lw t1, 32(a0)
+; RV32I-NEXT: lw t2, 36(a0)
+; RV32I-NEXT: lw t3, 40(a0)
+; RV32I-NEXT: lw t4, 44(a0)
+; RV32I-NEXT: lw t5, 48(a0)
+; RV32I-NEXT: lw t6, 52(a0)
+; RV32I-NEXT: lw s0, 56(a0)
+; RV32I-NEXT: lw s1, 60(a0)
+; RV32I-NEXT: lw s2, 64(a0)
+; RV32I-NEXT: lw s3, 68(a0)
+; RV32I-NEXT: lw s4, 72(a0)
+; RV32I-NEXT: lw s5, 76(a0)
+; RV32I-NEXT: lw s6, 80(a0)
+; RV32I-NEXT: lw s7, 84(a0)
+; RV32I-NEXT: lw s8, 88(a0)
+; RV32I-NEXT: lw s9, 92(a0)
+; RV32I-NEXT: lw s10, 112(a0)
+; RV32I-NEXT: lw s11, 116(a0)
+; RV32I-NEXT: lw ra, 120(a0)
+; RV32I-NEXT: lw a1, 124(a0)
+; RV32I-NEXT: lw a5, 96(a0)
+; RV32I-NEXT: lw a4, 100(a0)
+; RV32I-NEXT: lw a3, 104(a0)
+; RV32I-NEXT: lw a2, 108(a0)
+; RV32I-NEXT: sw a1, 124(a0)
+; RV32I-NEXT: sw ra, 120(a0)
+; RV32I-NEXT: sw s11, 116(a0)
+; RV32I-NEXT: sw s10, 112(a0)
+; RV32I-NEXT: sw a2, 108(a0)
+; RV32I-NEXT: sw a3, 104(a0)
+; RV32I-NEXT: sw a4, 100(a0)
+; RV32I-NEXT: sw a5, 96(a0)
+; RV32I-NEXT: sw s9, 92(a0)
+; RV32I-NEXT: sw s8, 88(a0)
+; RV32I-NEXT: sw s7, 84(a0)
+; RV32I-NEXT: sw s6, 80(a0)
+; RV32I-NEXT: sw s5, 76(a0)
+; RV32I-NEXT: sw s4, 72(a0)
+; RV32I-NEXT: sw s3, 68(a0)
+; RV32I-NEXT: sw s2, 64(a0)
+; RV32I-NEXT: sw s1, 60(a0)
+; RV32I-NEXT: sw s0, 56(a0)
+; RV32I-NEXT: sw t6, 52(a0)
+; RV32I-NEXT: sw t5, 48(a0)
+; RV32I-NEXT: sw t4, 44(a0)
+; RV32I-NEXT: sw t3, 40(a0)
+; RV32I-NEXT: sw t2, 36(a0)
+; RV32I-NEXT: sw t1, 32(a0)
+; RV32I-NEXT: sw t0, 28(a0)
+; RV32I-NEXT: sw a7, 24(a0)
+; RV32I-NEXT: sw a6, 20(a0)
+; RV32I-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 16(a0)
+; RV32I-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 12(a0)
+; RV32I-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 8(a0)
+; RV32I-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 4(a0)
+; RV32I-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 68(sp) # 4-byte Folded Reload
@@ -3915,21 +3865,21 @@ define void @callee_no_irq() {
;
; RV64I-LABEL: callee_no_irq:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -160
-; RV64I-NEXT: .cfi_def_cfa_offset 160
-; RV64I-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 144(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 136(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 128(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 120(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s4, 112(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s5, 104(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s6, 96(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s7, 88(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s8, 80(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s9, 72(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s10, 64(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s11, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -144
+; RV64I-NEXT: .cfi_def_cfa_offset 144
+; RV64I-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 128(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 120(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 112(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 104(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 96(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s5, 88(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s6, 80(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s7, 72(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s8, 64(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s9, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s10, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s11, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
@@ -3943,97 +3893,95 @@ define void @callee_no_irq() {
; RV64I-NEXT: .cfi_offset s9, -88
; RV64I-NEXT: .cfi_offset s10, -96
; RV64I-NEXT: .cfi_offset s11, -104
-; RV64I-NEXT: lui a7, %hi(var_test_irq)
-; RV64I-NEXT: lw a0, %lo(var_test_irq)(a7)
-; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var_test_irq+4)(a7)
-; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var_test_irq+8)(a7)
-; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, %lo(var_test_irq+12)(a7)
-; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: addi a5, a7, %lo(var_test_irq)
-; RV64I-NEXT: lw a0, 16(a5)
-; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw a0, 20(a5)
-; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: lw t0, 24(a5)
-; RV64I-NEXT: lw t1, 28(a5)
-; RV64I-NEXT: lw t2, 32(a5)
-; RV64I-NEXT: lw t3, 36(a5)
-; RV64I-NEXT: lw t4, 40(a5)
-; RV64I-NEXT: lw t5, 44(a5)
-; RV64I-NEXT: lw t6, 48(a5)
-; RV64I-NEXT: lw s0, 52(a5)
-; RV64I-NEXT: lw s1, 56(a5)
-; RV64I-NEXT: lw s2, 60(a5)
-; RV64I-NEXT: lw s3, 64(a5)
-; RV64I-NEXT: lw s4, 68(a5)
-; RV64I-NEXT: lw s5, 72(a5)
-; RV64I-NEXT: lw s6, 76(a5)
-; RV64I-NEXT: lw s7, 80(a5)
-; RV64I-NEXT: lw s8, 84(a5)
-; RV64I-NEXT: lw s9, 88(a5)
-; RV64I-NEXT: lw s10, 92(a5)
-; RV64I-NEXT: lw s11, 112(a5)
-; RV64I-NEXT: lw ra, 116(a5)
-; RV64I-NEXT: lw a3, 120(a5)
-; RV64I-NEXT: lw a0, 124(a5)
-; RV64I-NEXT: lw a6, 96(a5)
-; RV64I-NEXT: lw a4, 100(a5)
-; RV64I-NEXT: lw a2, 104(a5)
-; RV64I-NEXT: lw a1, 108(a5)
-; RV64I-NEXT: sw a0, 124(a5)
-; RV64I-NEXT: sw a3, 120(a5)
-; RV64I-NEXT: sw ra, 116(a5)
-; RV64I-NEXT: sw s11, 112(a5)
-; RV64I-NEXT: sw a1, 108(a5)
-; RV64I-NEXT: sw a2, 104(a5)
-; RV64I-NEXT: sw a4, 100(a5)
-; RV64I-NEXT: sw a6, 96(a5)
-; RV64I-NEXT: sw s10, 92(a5)
-; RV64I-NEXT: sw s9, 88(a5)
-; RV64I-NEXT: sw s8, 84(a5)
-; RV64I-NEXT: sw s7, 80(a5)
-; RV64I-NEXT: sw s6, 76(a5)
-; RV64I-NEXT: sw s5, 72(a5)
-; RV64I-NEXT: sw s4, 68(a5)
-; RV64I-NEXT: sw s3, 64(a5)
-; RV64I-NEXT: sw s2, 60(a5)
-; RV64I-NEXT: sw s1, 56(a5)
-; RV64I-NEXT: sw s0, 52(a5)
-; RV64I-NEXT: sw t6, 48(a5)
-; RV64I-NEXT: sw t5, 44(a5)
-; RV64I-NEXT: sw t4, 40(a5)
-; RV64I-NEXT: sw t3, 36(a5)
-; RV64I-NEXT: sw t2, 32(a5)
-; RV64I-NEXT: sw t1, 28(a5)
-; RV64I-NEXT: sw t0, 24(a5)
-; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 20(a5)
-; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, 16(a5)
-; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var_test_irq+12)(a7)
-; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var_test_irq+8)(a7)
-; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var_test_irq+4)(a7)
-; RV64I-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
-; RV64I-NEXT: sw a0, %lo(var_test_irq)(a7)
-; RV64I-NEXT: ld ra, 152(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 144(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 136(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 128(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 120(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s4, 112(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s5, 104(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s6, 96(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s7, 88(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s8, 80(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s9, 72(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s10, 64(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s11, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: lui a0, %hi(var_test_irq)
+; RV64I-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64I-NEXT: lw a1, 0(a0)
+; RV64I-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 4(a0)
+; RV64I-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 8(a0)
+; RV64I-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 12(a0)
+; RV64I-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a1, 16(a0)
+; RV64I-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw a6, 20(a0)
+; RV64I-NEXT: lw a7, 24(a0)
+; RV64I-NEXT: lw t0, 28(a0)
+; RV64I-NEXT: lw t1, 32(a0)
+; RV64I-NEXT: lw t2, 36(a0)
+; RV64I-NEXT: lw t3, 40(a0)
+; RV64I-NEXT: lw t4, 44(a0)
+; RV64I-NEXT: lw t5, 48(a0)
+; RV64I-NEXT: lw t6, 52(a0)
+; RV64I-NEXT: lw s0, 56(a0)
+; RV64I-NEXT: lw s1, 60(a0)
+; RV64I-NEXT: lw s2, 64(a0)
+; RV64I-NEXT: lw s3, 68(a0)
+; RV64I-NEXT: lw s4, 72(a0)
+; RV64I-NEXT: lw s5, 76(a0)
+; RV64I-NEXT: lw s6, 80(a0)
+; RV64I-NEXT: lw s7, 84(a0)
+; RV64I-NEXT: lw s8, 88(a0)
+; RV64I-NEXT: lw s9, 92(a0)
+; RV64I-NEXT: lw s10, 112(a0)
+; RV64I-NEXT: lw s11, 116(a0)
+; RV64I-NEXT: lw ra, 120(a0)
+; RV64I-NEXT: lw a1, 124(a0)
+; RV64I-NEXT: lw a5, 96(a0)
+; RV64I-NEXT: lw a4, 100(a0)
+; RV64I-NEXT: lw a3, 104(a0)
+; RV64I-NEXT: lw a2, 108(a0)
+; RV64I-NEXT: sw a1, 124(a0)
+; RV64I-NEXT: sw ra, 120(a0)
+; RV64I-NEXT: sw s11, 116(a0)
+; RV64I-NEXT: sw s10, 112(a0)
+; RV64I-NEXT: sw a2, 108(a0)
+; RV64I-NEXT: sw a3, 104(a0)
+; RV64I-NEXT: sw a4, 100(a0)
+; RV64I-NEXT: sw a5, 96(a0)
+; RV64I-NEXT: sw s9, 92(a0)
+; RV64I-NEXT: sw s8, 88(a0)
+; RV64I-NEXT: sw s7, 84(a0)
+; RV64I-NEXT: sw s6, 80(a0)
+; RV64I-NEXT: sw s5, 76(a0)
+; RV64I-NEXT: sw s4, 72(a0)
+; RV64I-NEXT: sw s3, 68(a0)
+; RV64I-NEXT: sw s2, 64(a0)
+; RV64I-NEXT: sw s1, 60(a0)
+; RV64I-NEXT: sw s0, 56(a0)
+; RV64I-NEXT: sw t6, 52(a0)
+; RV64I-NEXT: sw t5, 48(a0)
+; RV64I-NEXT: sw t4, 44(a0)
+; RV64I-NEXT: sw t3, 40(a0)
+; RV64I-NEXT: sw t2, 36(a0)
+; RV64I-NEXT: sw t1, 32(a0)
+; RV64I-NEXT: sw t0, 28(a0)
+; RV64I-NEXT: sw a7, 24(a0)
+; RV64I-NEXT: sw a6, 20(a0)
+; RV64I-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 16(a0)
+; RV64I-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 12(a0)
+; RV64I-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 8(a0)
+; RV64I-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 4(a0)
+; RV64I-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: sw a1, 0(a0)
+; RV64I-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 128(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 120(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 112(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 104(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 96(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s5, 88(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s6, 80(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s7, 72(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s8, 64(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s9, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s10, 48(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s11, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
@@ -4047,7 +3995,7 @@ define void @callee_no_irq() {
; RV64I-NEXT: .cfi_restore s9
; RV64I-NEXT: .cfi_restore s10
; RV64I-NEXT: .cfi_restore s11
-; RV64I-NEXT: addi sp, sp, 160
+; RV64I-NEXT: addi sp, sp, 144
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
%val = load [32 x i32], ptr @var_test_irq
diff --git a/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll b/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
index fc737928319b4..1b736611cbd1e 100644
--- a/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+++ b/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
@@ -1058,19 +1058,19 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-F-NEXT: .cfi_offset t4, -72
; QCI-F-NEXT: .cfi_offset t5, -76
; QCI-F-NEXT: .cfi_offset t6, -80
-; QCI-F-NEXT: addi sp, sp, -80
-; QCI-F-NEXT: .cfi_def_cfa_offset 176
-; QCI-F-NEXT: sw s1, 76(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s2, 72(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s3, 68(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s4, 64(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s5, 60(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s6, 56(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s7, 52(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s8, 48(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s9, 44(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s10, 40(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s11, 36(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: addi sp, sp, -64
+; QCI-F-NEXT: .cfi_def_cfa_offset 160
+; QCI-F-NEXT: sw s1, 60(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s2, 56(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s3, 52(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s4, 48(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s5, 44(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s6, 40(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s7, 36(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s8, 32(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s9, 28(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s10, 24(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s11, 20(sp) # 4-byte Folded Spill
; QCI-F-NEXT: .cfi_offset s1, -100
; QCI-F-NEXT: .cfi_offset s2, -104
; QCI-F-NEXT: .cfi_offset s3, -108
@@ -1082,95 +1082,93 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-F-NEXT: .cfi_offset s9, -132
; QCI-F-NEXT: .cfi_offset s10, -136
; QCI-F-NEXT: .cfi_offset s11, -140
-; QCI-F-NEXT: lui t0, %hi(var)
-; QCI-F-NEXT: lw a0, %lo(var)(t0)
-; QCI-F-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+4)(t0)
-; QCI-F-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+8)(t0)
-; QCI-F-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+12)(t0)
-; QCI-F-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: addi a5, t0, %lo(var)
-; QCI-F-NEXT: lw a0, 16(a5)
-; QCI-F-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 20(a5)
-; QCI-F-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw t4, 24(a5)
-; QCI-F-NEXT: lw t5, 28(a5)
-; QCI-F-NEXT: lw t6, 32(a5)
-; QCI-F-NEXT: lw s2, 36(a5)
-; QCI-F-NEXT: lw s3, 40(a5)
-; QCI-F-NEXT: lw s4, 44(a5)
-; QCI-F-NEXT: lw s5, 48(a5)
-; QCI-F-NEXT: lw s6, 52(a5)
-; QCI-F-NEXT: lw s7, 56(a5)
-; QCI-F-NEXT: lw s8, 60(a5)
-; QCI-F-NEXT: lw s9, 64(a5)
-; QCI-F-NEXT: lw s10, 68(a5)
-; QCI-F-NEXT: lw s11, 72(a5)
-; QCI-F-NEXT: lw ra, 76(a5)
-; QCI-F-NEXT: lw s1, 80(a5)
-; QCI-F-NEXT: lw t3, 84(a5)
-; QCI-F-NEXT: lw t2, 88(a5)
-; QCI-F-NEXT: lw t1, 92(a5)
-; QCI-F-NEXT: lw a7, 112(a5)
-; QCI-F-NEXT: lw s0, 116(a5)
-; QCI-F-NEXT: lw a3, 120(a5)
-; QCI-F-NEXT: lw a0, 124(a5)
-; QCI-F-NEXT: lw a6, 96(a5)
-; QCI-F-NEXT: lw a4, 100(a5)
-; QCI-F-NEXT: lw a2, 104(a5)
-; QCI-F-NEXT: lw a1, 108(a5)
-; QCI-F-NEXT: sw a0, 124(a5)
-; QCI-F-NEXT: sw a3, 120(a5)
-; QCI-F-NEXT: sw s0, 116(a5)
-; QCI-F-NEXT: sw a7, 112(a5)
-; QCI-F-NEXT: sw a1, 108(a5)
-; QCI-F-NEXT: sw a2, 104(a5)
-; QCI-F-NEXT: sw a4, 100(a5)
-; QCI-F-NEXT: sw a6, 96(a5)
-; QCI-F-NEXT: sw t1, 92(a5)
-; QCI-F-NEXT: sw t2, 88(a5)
-; QCI-F-NEXT: sw t3, 84(a5)
-; QCI-F-NEXT: sw s1, 80(a5)
-; QCI-F-NEXT: sw ra, 76(a5)
-; QCI-F-NEXT: sw s11, 72(a5)
-; QCI-F-NEXT: sw s10, 68(a5)
-; QCI-F-NEXT: sw s9, 64(a5)
-; QCI-F-NEXT: sw s8, 60(a5)
-; QCI-F-NEXT: sw s7, 56(a5)
-; QCI-F-NEXT: sw s6, 52(a5)
-; QCI-F-NEXT: sw s5, 48(a5)
-; QCI-F-NEXT: sw s4, 44(a5)
-; QCI-F-NEXT: sw s3, 40(a5)
-; QCI-F-NEXT: sw s2, 36(a5)
-; QCI-F-NEXT: sw t6, 32(a5)
-; QCI-F-NEXT: sw t5, 28(a5)
-; QCI-F-NEXT: sw t4, 24(a5)
-; QCI-F-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 20(a5)
-; QCI-F-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 16(a5)
-; QCI-F-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+12)(t0)
-; QCI-F-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+8)(t0)
-; QCI-F-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+4)(t0)
-; QCI-F-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var)(t0)
-; QCI-F-NEXT: lw s1, 76(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s2, 72(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s3, 68(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s4, 64(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s5, 60(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s6, 56(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s7, 52(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s8, 48(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s9, 44(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s10, 40(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s11, 36(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lui a0, %hi(var)
+; QCI-F-NEXT: addi a0, a0, %lo(var)
+; QCI-F-NEXT: lw a1, 0(a0)
+; QCI-F-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: lw a1, 4(a0)
+; QCI-F-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: lw a1, 8(a0)
+; QCI-F-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: lw a1, 12(a0)
+; QCI-F-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: lw a1, 16(a0)
+; QCI-F-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: lw t3, 20(a0)
+; QCI-F-NEXT: lw t4, 24(a0)
+; QCI-F-NEXT: lw t5, 28(a0)
+; QCI-F-NEXT: lw t6, 32(a0)
+; QCI-F-NEXT: lw s2, 36(a0)
+; QCI-F-NEXT: lw s3, 40(a0)
+; QCI-F-NEXT: lw s4, 44(a0)
+; QCI-F-NEXT: lw s5, 48(a0)
+; QCI-F-NEXT: lw s6, 52(a0)
+; QCI-F-NEXT: lw s7, 56(a0)
+; QCI-F-NEXT: lw s8, 60(a0)
+; QCI-F-NEXT: lw s9, 64(a0)
+; QCI-F-NEXT: lw s10, 68(a0)
+; QCI-F-NEXT: lw s11, 72(a0)
+; QCI-F-NEXT: lw ra, 76(a0)
+; QCI-F-NEXT: lw t2, 80(a0)
+; QCI-F-NEXT: lw s0, 84(a0)
+; QCI-F-NEXT: lw s1, 88(a0)
+; QCI-F-NEXT: lw t1, 92(a0)
+; QCI-F-NEXT: lw t0, 112(a0)
+; QCI-F-NEXT: lw a5, 116(a0)
+; QCI-F-NEXT: lw a3, 120(a0)
+; QCI-F-NEXT: lw a1, 124(a0)
+; QCI-F-NEXT: lw a7, 96(a0)
+; QCI-F-NEXT: lw a6, 100(a0)
+; QCI-F-NEXT: lw a4, 104(a0)
+; QCI-F-NEXT: lw a2, 108(a0)
+; QCI-F-NEXT: sw a1, 124(a0)
+; QCI-F-NEXT: sw a3, 120(a0)
+; QCI-F-NEXT: sw a5, 116(a0)
+; QCI-F-NEXT: sw t0, 112(a0)
+; QCI-F-NEXT: sw a2, 108(a0)
+; QCI-F-NEXT: sw a4, 104(a0)
+; QCI-F-NEXT: sw a6, 100(a0)
+; QCI-F-NEXT: sw a7, 96(a0)
+; QCI-F-NEXT: sw t1, 92(a0)
+; QCI-F-NEXT: sw s1, 88(a0)
+; QCI-F-NEXT: sw s0, 84(a0)
+; QCI-F-NEXT: sw t2, 80(a0)
+; QCI-F-NEXT: sw ra, 76(a0)
+; QCI-F-NEXT: sw s11, 72(a0)
+; QCI-F-NEXT: sw s10, 68(a0)
+; QCI-F-NEXT: sw s9, 64(a0)
+; QCI-F-NEXT: sw s8, 60(a0)
+; QCI-F-NEXT: sw s7, 56(a0)
+; QCI-F-NEXT: sw s6, 52(a0)
+; QCI-F-NEXT: sw s5, 48(a0)
+; QCI-F-NEXT: sw s4, 44(a0)
+; QCI-F-NEXT: sw s3, 40(a0)
+; QCI-F-NEXT: sw s2, 36(a0)
+; QCI-F-NEXT: sw t6, 32(a0)
+; QCI-F-NEXT: sw t5, 28(a0)
+; QCI-F-NEXT: sw t4, 24(a0)
+; QCI-F-NEXT: sw t3, 20(a0)
+; QCI-F-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: sw a1, 16(a0)
+; QCI-F-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: sw a1, 12(a0)
+; QCI-F-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: sw a1, 8(a0)
+; QCI-F-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: sw a1, 4(a0)
+; QCI-F-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: sw a1, 0(a0)
+; QCI-F-NEXT: lw s1, 60(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s2, 56(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s3, 52(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s4, 48(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s5, 44(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s6, 40(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s7, 36(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s8, 32(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s9, 28(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s10, 24(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s11, 20(sp) # 4-byte Folded Reload
; QCI-F-NEXT: .cfi_restore s1
; QCI-F-NEXT: .cfi_restore s2
; QCI-F-NEXT: .cfi_restore s3
@@ -1182,7 +1180,7 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-F-NEXT: .cfi_restore s9
; QCI-F-NEXT: .cfi_restore s10
; QCI-F-NEXT: .cfi_restore s11
-; QCI-F-NEXT: addi sp, sp, 80
+; QCI-F-NEXT: addi sp, sp, 64
; QCI-F-NEXT: .cfi_def_cfa_offset 96
; QCI-F-NEXT: qc.c.mileaveret
;
@@ -1207,19 +1205,19 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-D-NEXT: .cfi_offset t4, -72
; QCI-D-NEXT: .cfi_offset t5, -76
; QCI-D-NEXT: .cfi_offset t6, -80
-; QCI-D-NEXT: addi sp, sp, -80
-; QCI-D-NEXT: .cfi_def_cfa_offset 176
-; QCI-D-NEXT: sw s1, 76(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s2, 72(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s3, 68(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s4, 64(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s5, 60(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s6, 56(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s7, 52(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s8, 48(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s9, 44(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s10, 40(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s11, 36(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: addi sp, sp, -64
+; QCI-D-NEXT: .cfi_def_cfa_offset 160
+; QCI-D-NEXT: sw s1, 60(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s2, 56(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s3, 52(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s4, 48(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s5, 44(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s6, 40(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s7, 36(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s8, 32(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s9, 28(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s10, 24(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s11, 20(sp) # 4-byte Folded Spill
; QCI-D-NEXT: .cfi_offset s1, -100
; QCI-D-NEXT: .cfi_offset s2, -104
; QCI-D-NEXT: .cfi_offset s3, -108
@@ -1231,95 +1229,93 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-D-NEXT: .cfi_offset s9, -132
; QCI-D-NEXT: .cfi_offset s10, -136
; QCI-D-NEXT: .cfi_offset s11, -140
-; QCI-D-NEXT: lui t0, %hi(var)
-; QCI-D-NEXT: lw a0, %lo(var)(t0)
-; QCI-D-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+4)(t0)
-; QCI-D-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+8)(t0)
-; QCI-D-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+12)(t0)
-; QCI-D-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: addi a5, t0, %lo(var)
-; QCI-D-NEXT: lw a0, 16(a5)
-; QCI-D-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 20(a5)
-; QCI-D-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw t4, 24(a5)
-; QCI-D-NEXT: lw t5, 28(a5)
-; QCI-D-NEXT: lw t6, 32(a5)
-; QCI-D-NEXT: lw s2, 36(a5)
-; QCI-D-NEXT: lw s3, 40(a5)
-; QCI-D-NEXT: lw s4, 44(a5)
-; QCI-D-NEXT: lw s5, 48(a5)
-; QCI-D-NEXT: lw s6, 52(a5)
-; QCI-D-NEXT: lw s7, 56(a5)
-; QCI-D-NEXT: lw s8, 60(a5)
-; QCI-D-NEXT: lw s9, 64(a5)
-; QCI-D-NEXT: lw s10, 68(a5)
-; QCI-D-NEXT: lw s11, 72(a5)
-; QCI-D-NEXT: lw ra, 76(a5)
-; QCI-D-NEXT: lw s1, 80(a5)
-; QCI-D-NEXT: lw t3, 84(a5)
-; QCI-D-NEXT: lw t2, 88(a5)
-; QCI-D-NEXT: lw t1, 92(a5)
-; QCI-D-NEXT: lw a7, 112(a5)
-; QCI-D-NEXT: lw s0, 116(a5)
-; QCI-D-NEXT: lw a3, 120(a5)
-; QCI-D-NEXT: lw a0, 124(a5)
-; QCI-D-NEXT: lw a6, 96(a5)
-; QCI-D-NEXT: lw a4, 100(a5)
-; QCI-D-NEXT: lw a2, 104(a5)
-; QCI-D-NEXT: lw a1, 108(a5)
-; QCI-D-NEXT: sw a0, 124(a5)
-; QCI-D-NEXT: sw a3, 120(a5)
-; QCI-D-NEXT: sw s0, 116(a5)
-; QCI-D-NEXT: sw a7, 112(a5)
-; QCI-D-NEXT: sw a1, 108(a5)
-; QCI-D-NEXT: sw a2, 104(a5)
-; QCI-D-NEXT: sw a4, 100(a5)
-; QCI-D-NEXT: sw a6, 96(a5)
-; QCI-D-NEXT: sw t1, 92(a5)
-; QCI-D-NEXT: sw t2, 88(a5)
-; QCI-D-NEXT: sw t3, 84(a5)
-; QCI-D-NEXT: sw s1, 80(a5)
-; QCI-D-NEXT: sw ra, 76(a5)
-; QCI-D-NEXT: sw s11, 72(a5)
-; QCI-D-NEXT: sw s10, 68(a5)
-; QCI-D-NEXT: sw s9, 64(a5)
-; QCI-D-NEXT: sw s8, 60(a5)
-; QCI-D-NEXT: sw s7, 56(a5)
-; QCI-D-NEXT: sw s6, 52(a5)
-; QCI-D-NEXT: sw s5, 48(a5)
-; QCI-D-NEXT: sw s4, 44(a5)
-; QCI-D-NEXT: sw s3, 40(a5)
-; QCI-D-NEXT: sw s2, 36(a5)
-; QCI-D-NEXT: sw t6, 32(a5)
-; QCI-D-NEXT: sw t5, 28(a5)
-; QCI-D-NEXT: sw t4, 24(a5)
-; QCI-D-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 20(a5)
-; QCI-D-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 16(a5)
-; QCI-D-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+12)(t0)
-; QCI-D-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+8)(t0)
-; QCI-D-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+4)(t0)
-; QCI-D-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var)(t0)
-; QCI-D-NEXT: lw s1, 76(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s2, 72(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s3, 68(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s4, 64(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s5, 60(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s6, 56(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s7, 52(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s8, 48(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s9, 44(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s10, 40(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s11, 36(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lui a0, %hi(var)
+; QCI-D-NEXT: addi a0, a0, %lo(var)
+; QCI-D-NEXT: lw a1, 0(a0)
+; QCI-D-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: lw a1, 4(a0)
+; QCI-D-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: lw a1, 8(a0)
+; QCI-D-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: lw a1, 12(a0)
+; QCI-D-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: lw a1, 16(a0)
+; QCI-D-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: lw t3, 20(a0)
+; QCI-D-NEXT: lw t4, 24(a0)
+; QCI-D-NEXT: lw t5, 28(a0)
+; QCI-D-NEXT: lw t6, 32(a0)
+; QCI-D-NEXT: lw s2, 36(a0)
+; QCI-D-NEXT: lw s3, 40(a0)
+; QCI-D-NEXT: lw s4, 44(a0)
+; QCI-D-NEXT: lw s5, 48(a0)
+; QCI-D-NEXT: lw s6, 52(a0)
+; QCI-D-NEXT: lw s7, 56(a0)
+; QCI-D-NEXT: lw s8, 60(a0)
+; QCI-D-NEXT: lw s9, 64(a0)
+; QCI-D-NEXT: lw s10, 68(a0)
+; QCI-D-NEXT: lw s11, 72(a0)
+; QCI-D-NEXT: lw ra, 76(a0)
+; QCI-D-NEXT: lw t2, 80(a0)
+; QCI-D-NEXT: lw s0, 84(a0)
+; QCI-D-NEXT: lw s1, 88(a0)
+; QCI-D-NEXT: lw t1, 92(a0)
+; QCI-D-NEXT: lw t0, 112(a0)
+; QCI-D-NEXT: lw a5, 116(a0)
+; QCI-D-NEXT: lw a3, 120(a0)
+; QCI-D-NEXT: lw a1, 124(a0)
+; QCI-D-NEXT: lw a7, 96(a0)
+; QCI-D-NEXT: lw a6, 100(a0)
+; QCI-D-NEXT: lw a4, 104(a0)
+; QCI-D-NEXT: lw a2, 108(a0)
+; QCI-D-NEXT: sw a1, 124(a0)
+; QCI-D-NEXT: sw a3, 120(a0)
+; QCI-D-NEXT: sw a5, 116(a0)
+; QCI-D-NEXT: sw t0, 112(a0)
+; QCI-D-NEXT: sw a2, 108(a0)
+; QCI-D-NEXT: sw a4, 104(a0)
+; QCI-D-NEXT: sw a6, 100(a0)
+; QCI-D-NEXT: sw a7, 96(a0)
+; QCI-D-NEXT: sw t1, 92(a0)
+; QCI-D-NEXT: sw s1, 88(a0)
+; QCI-D-NEXT: sw s0, 84(a0)
+; QCI-D-NEXT: sw t2, 80(a0)
+; QCI-D-NEXT: sw ra, 76(a0)
+; QCI-D-NEXT: sw s11, 72(a0)
+; QCI-D-NEXT: sw s10, 68(a0)
+; QCI-D-NEXT: sw s9, 64(a0)
+; QCI-D-NEXT: sw s8, 60(a0)
+; QCI-D-NEXT: sw s7, 56(a0)
+; QCI-D-NEXT: sw s6, 52(a0)
+; QCI-D-NEXT: sw s5, 48(a0)
+; QCI-D-NEXT: sw s4, 44(a0)
+; QCI-D-NEXT: sw s3, 40(a0)
+; QCI-D-NEXT: sw s2, 36(a0)
+; QCI-D-NEXT: sw t6, 32(a0)
+; QCI-D-NEXT: sw t5, 28(a0)
+; QCI-D-NEXT: sw t4, 24(a0)
+; QCI-D-NEXT: sw t3, 20(a0)
+; QCI-D-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: sw a1, 16(a0)
+; QCI-D-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: sw a1, 12(a0)
+; QCI-D-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: sw a1, 8(a0)
+; QCI-D-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: sw a1, 4(a0)
+; QCI-D-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: sw a1, 0(a0)
+; QCI-D-NEXT: lw s1, 60(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s2, 56(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s3, 52(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s4, 48(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s5, 44(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s6, 40(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s7, 36(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s8, 32(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s9, 28(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s10, 24(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s11, 20(sp) # 4-byte Folded Reload
; QCI-D-NEXT: .cfi_restore s1
; QCI-D-NEXT: .cfi_restore s2
; QCI-D-NEXT: .cfi_restore s3
@@ -1331,7 +1327,7 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-D-NEXT: .cfi_restore s9
; QCI-D-NEXT: .cfi_restore s10
; QCI-D-NEXT: .cfi_restore s11
-; QCI-D-NEXT: addi sp, sp, 80
+; QCI-D-NEXT: addi sp, sp, 64
; QCI-D-NEXT: .cfi_def_cfa_offset 96
; QCI-D-NEXT: qc.c.mileaveret
%1 = load [32 x i32], ptr @var
@@ -1361,19 +1357,19 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-F-NEXT: .cfi_offset t4, -72
; QCI-F-NEXT: .cfi_offset t5, -76
; QCI-F-NEXT: .cfi_offset t6, -80
-; QCI-F-NEXT: addi sp, sp, -80
-; QCI-F-NEXT: .cfi_def_cfa_offset 176
-; QCI-F-NEXT: sw s1, 76(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s2, 72(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s3, 68(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s4, 64(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s5, 60(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s6, 56(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s7, 52(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s8, 48(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s9, 44(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s10, 40(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: sw s11, 36(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: addi sp, sp, -64
+; QCI-F-NEXT: .cfi_def_cfa_offset 160
+; QCI-F-NEXT: sw s1, 60(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s2, 56(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s3, 52(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s4, 48(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s5, 44(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s6, 40(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s7, 36(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s8, 32(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s9, 28(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s10, 24(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: sw s11, 20(sp) # 4-byte Folded Spill
; QCI-F-NEXT: .cfi_offset s1, -100
; QCI-F-NEXT: .cfi_offset s2, -104
; QCI-F-NEXT: .cfi_offset s3, -108
@@ -1385,95 +1381,93 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-F-NEXT: .cfi_offset s9, -132
; QCI-F-NEXT: .cfi_offset s10, -136
; QCI-F-NEXT: .cfi_offset s11, -140
-; QCI-F-NEXT: lui t0, %hi(var)
-; QCI-F-NEXT: lw a0, %lo(var)(t0)
-; QCI-F-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+4)(t0)
-; QCI-F-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+8)(t0)
-; QCI-F-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+12)(t0)
-; QCI-F-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: addi a5, t0, %lo(var)
-; QCI-F-NEXT: lw a0, 16(a5)
-; QCI-F-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 20(a5)
-; QCI-F-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw t4, 24(a5)
-; QCI-F-NEXT: lw t5, 28(a5)
-; QCI-F-NEXT: lw t6, 32(a5)
-; QCI-F-NEXT: lw s2, 36(a5)
-; QCI-F-NEXT: lw s3, 40(a5)
-; QCI-F-NEXT: lw s4, 44(a5)
-; QCI-F-NEXT: lw s5, 48(a5)
-; QCI-F-NEXT: lw s6, 52(a5)
-; QCI-F-NEXT: lw s7, 56(a5)
-; QCI-F-NEXT: lw s8, 60(a5)
-; QCI-F-NEXT: lw s9, 64(a5)
-; QCI-F-NEXT: lw s10, 68(a5)
-; QCI-F-NEXT: lw s11, 72(a5)
-; QCI-F-NEXT: lw ra, 76(a5)
-; QCI-F-NEXT: lw s1, 80(a5)
-; QCI-F-NEXT: lw t3, 84(a5)
-; QCI-F-NEXT: lw t2, 88(a5)
-; QCI-F-NEXT: lw t1, 92(a5)
-; QCI-F-NEXT: lw a7, 112(a5)
-; QCI-F-NEXT: lw s0, 116(a5)
-; QCI-F-NEXT: lw a3, 120(a5)
-; QCI-F-NEXT: lw a0, 124(a5)
-; QCI-F-NEXT: lw a6, 96(a5)
-; QCI-F-NEXT: lw a4, 100(a5)
-; QCI-F-NEXT: lw a2, 104(a5)
-; QCI-F-NEXT: lw a1, 108(a5)
-; QCI-F-NEXT: sw a0, 124(a5)
-; QCI-F-NEXT: sw a3, 120(a5)
-; QCI-F-NEXT: sw s0, 116(a5)
-; QCI-F-NEXT: sw a7, 112(a5)
-; QCI-F-NEXT: sw a1, 108(a5)
-; QCI-F-NEXT: sw a2, 104(a5)
-; QCI-F-NEXT: sw a4, 100(a5)
-; QCI-F-NEXT: sw a6, 96(a5)
-; QCI-F-NEXT: sw t1, 92(a5)
-; QCI-F-NEXT: sw t2, 88(a5)
-; QCI-F-NEXT: sw t3, 84(a5)
-; QCI-F-NEXT: sw s1, 80(a5)
-; QCI-F-NEXT: sw ra, 76(a5)
-; QCI-F-NEXT: sw s11, 72(a5)
-; QCI-F-NEXT: sw s10, 68(a5)
-; QCI-F-NEXT: sw s9, 64(a5)
-; QCI-F-NEXT: sw s8, 60(a5)
-; QCI-F-NEXT: sw s7, 56(a5)
-; QCI-F-NEXT: sw s6, 52(a5)
-; QCI-F-NEXT: sw s5, 48(a5)
-; QCI-F-NEXT: sw s4, 44(a5)
-; QCI-F-NEXT: sw s3, 40(a5)
-; QCI-F-NEXT: sw s2, 36(a5)
-; QCI-F-NEXT: sw t6, 32(a5)
-; QCI-F-NEXT: sw t5, 28(a5)
-; QCI-F-NEXT: sw t4, 24(a5)
-; QCI-F-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 20(a5)
-; QCI-F-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 16(a5)
-; QCI-F-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+12)(t0)
-; QCI-F-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+8)(t0)
-; QCI-F-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+4)(t0)
-; QCI-F-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var)(t0)
-; QCI-F-NEXT: lw s1, 76(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s2, 72(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s3, 68(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s4, 64(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s5, 60(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s6, 56(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s7, 52(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s8, 48(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s9, 44(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s10, 40(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: lw s11, 36(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lui a0, %hi(var)
+; QCI-F-NEXT: addi a0, a0, %lo(var)
+; QCI-F-NEXT: lw a1, 0(a0)
+; QCI-F-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: lw a1, 4(a0)
+; QCI-F-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: lw a1, 8(a0)
+; QCI-F-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: lw a1, 12(a0)
+; QCI-F-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: lw a1, 16(a0)
+; QCI-F-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; QCI-F-NEXT: lw t3, 20(a0)
+; QCI-F-NEXT: lw t4, 24(a0)
+; QCI-F-NEXT: lw t5, 28(a0)
+; QCI-F-NEXT: lw t6, 32(a0)
+; QCI-F-NEXT: lw s2, 36(a0)
+; QCI-F-NEXT: lw s3, 40(a0)
+; QCI-F-NEXT: lw s4, 44(a0)
+; QCI-F-NEXT: lw s5, 48(a0)
+; QCI-F-NEXT: lw s6, 52(a0)
+; QCI-F-NEXT: lw s7, 56(a0)
+; QCI-F-NEXT: lw s8, 60(a0)
+; QCI-F-NEXT: lw s9, 64(a0)
+; QCI-F-NEXT: lw s10, 68(a0)
+; QCI-F-NEXT: lw s11, 72(a0)
+; QCI-F-NEXT: lw ra, 76(a0)
+; QCI-F-NEXT: lw t2, 80(a0)
+; QCI-F-NEXT: lw s0, 84(a0)
+; QCI-F-NEXT: lw s1, 88(a0)
+; QCI-F-NEXT: lw t1, 92(a0)
+; QCI-F-NEXT: lw t0, 112(a0)
+; QCI-F-NEXT: lw a5, 116(a0)
+; QCI-F-NEXT: lw a3, 120(a0)
+; QCI-F-NEXT: lw a1, 124(a0)
+; QCI-F-NEXT: lw a7, 96(a0)
+; QCI-F-NEXT: lw a6, 100(a0)
+; QCI-F-NEXT: lw a4, 104(a0)
+; QCI-F-NEXT: lw a2, 108(a0)
+; QCI-F-NEXT: sw a1, 124(a0)
+; QCI-F-NEXT: sw a3, 120(a0)
+; QCI-F-NEXT: sw a5, 116(a0)
+; QCI-F-NEXT: sw t0, 112(a0)
+; QCI-F-NEXT: sw a2, 108(a0)
+; QCI-F-NEXT: sw a4, 104(a0)
+; QCI-F-NEXT: sw a6, 100(a0)
+; QCI-F-NEXT: sw a7, 96(a0)
+; QCI-F-NEXT: sw t1, 92(a0)
+; QCI-F-NEXT: sw s1, 88(a0)
+; QCI-F-NEXT: sw s0, 84(a0)
+; QCI-F-NEXT: sw t2, 80(a0)
+; QCI-F-NEXT: sw ra, 76(a0)
+; QCI-F-NEXT: sw s11, 72(a0)
+; QCI-F-NEXT: sw s10, 68(a0)
+; QCI-F-NEXT: sw s9, 64(a0)
+; QCI-F-NEXT: sw s8, 60(a0)
+; QCI-F-NEXT: sw s7, 56(a0)
+; QCI-F-NEXT: sw s6, 52(a0)
+; QCI-F-NEXT: sw s5, 48(a0)
+; QCI-F-NEXT: sw s4, 44(a0)
+; QCI-F-NEXT: sw s3, 40(a0)
+; QCI-F-NEXT: sw s2, 36(a0)
+; QCI-F-NEXT: sw t6, 32(a0)
+; QCI-F-NEXT: sw t5, 28(a0)
+; QCI-F-NEXT: sw t4, 24(a0)
+; QCI-F-NEXT: sw t3, 20(a0)
+; QCI-F-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: sw a1, 16(a0)
+; QCI-F-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: sw a1, 12(a0)
+; QCI-F-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: sw a1, 8(a0)
+; QCI-F-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: sw a1, 4(a0)
+; QCI-F-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: sw a1, 0(a0)
+; QCI-F-NEXT: lw s1, 60(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s2, 56(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s3, 52(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s4, 48(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s5, 44(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s6, 40(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s7, 36(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s8, 32(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s9, 28(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s10, 24(sp) # 4-byte Folded Reload
+; QCI-F-NEXT: lw s11, 20(sp) # 4-byte Folded Reload
; QCI-F-NEXT: .cfi_restore s1
; QCI-F-NEXT: .cfi_restore s2
; QCI-F-NEXT: .cfi_restore s3
@@ -1485,7 +1479,7 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-F-NEXT: .cfi_restore s9
; QCI-F-NEXT: .cfi_restore s10
; QCI-F-NEXT: .cfi_restore s11
-; QCI-F-NEXT: addi sp, sp, 80
+; QCI-F-NEXT: addi sp, sp, 64
; QCI-F-NEXT: .cfi_def_cfa_offset 96
; QCI-F-NEXT: qc.c.mileaveret
;
@@ -1510,19 +1504,19 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-D-NEXT: .cfi_offset t4, -72
; QCI-D-NEXT: .cfi_offset t5, -76
; QCI-D-NEXT: .cfi_offset t6, -80
-; QCI-D-NEXT: addi sp, sp, -80
-; QCI-D-NEXT: .cfi_def_cfa_offset 176
-; QCI-D-NEXT: sw s1, 76(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s2, 72(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s3, 68(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s4, 64(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s5, 60(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s6, 56(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s7, 52(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s8, 48(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s9, 44(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s10, 40(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: sw s11, 36(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: addi sp, sp, -64
+; QCI-D-NEXT: .cfi_def_cfa_offset 160
+; QCI-D-NEXT: sw s1, 60(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s2, 56(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s3, 52(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s4, 48(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s5, 44(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s6, 40(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s7, 36(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s8, 32(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s9, 28(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s10, 24(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: sw s11, 20(sp) # 4-byte Folded Spill
; QCI-D-NEXT: .cfi_offset s1, -100
; QCI-D-NEXT: .cfi_offset s2, -104
; QCI-D-NEXT: .cfi_offset s3, -108
@@ -1534,95 +1528,93 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-D-NEXT: .cfi_offset s9, -132
; QCI-D-NEXT: .cfi_offset s10, -136
; QCI-D-NEXT: .cfi_offset s11, -140
-; QCI-D-NEXT: lui t0, %hi(var)
-; QCI-D-NEXT: lw a0, %lo(var)(t0)
-; QCI-D-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+4)(t0)
-; QCI-D-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+8)(t0)
-; QCI-D-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+12)(t0)
-; QCI-D-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: addi a5, t0, %lo(var)
-; QCI-D-NEXT: lw a0, 16(a5)
-; QCI-D-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 20(a5)
-; QCI-D-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw t4, 24(a5)
-; QCI-D-NEXT: lw t5, 28(a5)
-; QCI-D-NEXT: lw t6, 32(a5)
-; QCI-D-NEXT: lw s2, 36(a5)
-; QCI-D-NEXT: lw s3, 40(a5)
-; QCI-D-NEXT: lw s4, 44(a5)
-; QCI-D-NEXT: lw s5, 48(a5)
-; QCI-D-NEXT: lw s6, 52(a5)
-; QCI-D-NEXT: lw s7, 56(a5)
-; QCI-D-NEXT: lw s8, 60(a5)
-; QCI-D-NEXT: lw s9, 64(a5)
-; QCI-D-NEXT: lw s10, 68(a5)
-; QCI-D-NEXT: lw s11, 72(a5)
-; QCI-D-NEXT: lw ra, 76(a5)
-; QCI-D-NEXT: lw s1, 80(a5)
-; QCI-D-NEXT: lw t3, 84(a5)
-; QCI-D-NEXT: lw t2, 88(a5)
-; QCI-D-NEXT: lw t1, 92(a5)
-; QCI-D-NEXT: lw a7, 112(a5)
-; QCI-D-NEXT: lw s0, 116(a5)
-; QCI-D-NEXT: lw a3, 120(a5)
-; QCI-D-NEXT: lw a0, 124(a5)
-; QCI-D-NEXT: lw a6, 96(a5)
-; QCI-D-NEXT: lw a4, 100(a5)
-; QCI-D-NEXT: lw a2, 104(a5)
-; QCI-D-NEXT: lw a1, 108(a5)
-; QCI-D-NEXT: sw a0, 124(a5)
-; QCI-D-NEXT: sw a3, 120(a5)
-; QCI-D-NEXT: sw s0, 116(a5)
-; QCI-D-NEXT: sw a7, 112(a5)
-; QCI-D-NEXT: sw a1, 108(a5)
-; QCI-D-NEXT: sw a2, 104(a5)
-; QCI-D-NEXT: sw a4, 100(a5)
-; QCI-D-NEXT: sw a6, 96(a5)
-; QCI-D-NEXT: sw t1, 92(a5)
-; QCI-D-NEXT: sw t2, 88(a5)
-; QCI-D-NEXT: sw t3, 84(a5)
-; QCI-D-NEXT: sw s1, 80(a5)
-; QCI-D-NEXT: sw ra, 76(a5)
-; QCI-D-NEXT: sw s11, 72(a5)
-; QCI-D-NEXT: sw s10, 68(a5)
-; QCI-D-NEXT: sw s9, 64(a5)
-; QCI-D-NEXT: sw s8, 60(a5)
-; QCI-D-NEXT: sw s7, 56(a5)
-; QCI-D-NEXT: sw s6, 52(a5)
-; QCI-D-NEXT: sw s5, 48(a5)
-; QCI-D-NEXT: sw s4, 44(a5)
-; QCI-D-NEXT: sw s3, 40(a5)
-; QCI-D-NEXT: sw s2, 36(a5)
-; QCI-D-NEXT: sw t6, 32(a5)
-; QCI-D-NEXT: sw t5, 28(a5)
-; QCI-D-NEXT: sw t4, 24(a5)
-; QCI-D-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 20(a5)
-; QCI-D-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 16(a5)
-; QCI-D-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+12)(t0)
-; QCI-D-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+8)(t0)
-; QCI-D-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+4)(t0)
-; QCI-D-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var)(t0)
-; QCI-D-NEXT: lw s1, 76(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s2, 72(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s3, 68(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s4, 64(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s5, 60(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s6, 56(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s7, 52(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s8, 48(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s9, 44(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s10, 40(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: lw s11, 36(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lui a0, %hi(var)
+; QCI-D-NEXT: addi a0, a0, %lo(var)
+; QCI-D-NEXT: lw a1, 0(a0)
+; QCI-D-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: lw a1, 4(a0)
+; QCI-D-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: lw a1, 8(a0)
+; QCI-D-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: lw a1, 12(a0)
+; QCI-D-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: lw a1, 16(a0)
+; QCI-D-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; QCI-D-NEXT: lw t3, 20(a0)
+; QCI-D-NEXT: lw t4, 24(a0)
+; QCI-D-NEXT: lw t5, 28(a0)
+; QCI-D-NEXT: lw t6, 32(a0)
+; QCI-D-NEXT: lw s2, 36(a0)
+; QCI-D-NEXT: lw s3, 40(a0)
+; QCI-D-NEXT: lw s4, 44(a0)
+; QCI-D-NEXT: lw s5, 48(a0)
+; QCI-D-NEXT: lw s6, 52(a0)
+; QCI-D-NEXT: lw s7, 56(a0)
+; QCI-D-NEXT: lw s8, 60(a0)
+; QCI-D-NEXT: lw s9, 64(a0)
+; QCI-D-NEXT: lw s10, 68(a0)
+; QCI-D-NEXT: lw s11, 72(a0)
+; QCI-D-NEXT: lw ra, 76(a0)
+; QCI-D-NEXT: lw t2, 80(a0)
+; QCI-D-NEXT: lw s0, 84(a0)
+; QCI-D-NEXT: lw s1, 88(a0)
+; QCI-D-NEXT: lw t1, 92(a0)
+; QCI-D-NEXT: lw t0, 112(a0)
+; QCI-D-NEXT: lw a5, 116(a0)
+; QCI-D-NEXT: lw a3, 120(a0)
+; QCI-D-NEXT: lw a1, 124(a0)
+; QCI-D-NEXT: lw a7, 96(a0)
+; QCI-D-NEXT: lw a6, 100(a0)
+; QCI-D-NEXT: lw a4, 104(a0)
+; QCI-D-NEXT: lw a2, 108(a0)
+; QCI-D-NEXT: sw a1, 124(a0)
+; QCI-D-NEXT: sw a3, 120(a0)
+; QCI-D-NEXT: sw a5, 116(a0)
+; QCI-D-NEXT: sw t0, 112(a0)
+; QCI-D-NEXT: sw a2, 108(a0)
+; QCI-D-NEXT: sw a4, 104(a0)
+; QCI-D-NEXT: sw a6, 100(a0)
+; QCI-D-NEXT: sw a7, 96(a0)
+; QCI-D-NEXT: sw t1, 92(a0)
+; QCI-D-NEXT: sw s1, 88(a0)
+; QCI-D-NEXT: sw s0, 84(a0)
+; QCI-D-NEXT: sw t2, 80(a0)
+; QCI-D-NEXT: sw ra, 76(a0)
+; QCI-D-NEXT: sw s11, 72(a0)
+; QCI-D-NEXT: sw s10, 68(a0)
+; QCI-D-NEXT: sw s9, 64(a0)
+; QCI-D-NEXT: sw s8, 60(a0)
+; QCI-D-NEXT: sw s7, 56(a0)
+; QCI-D-NEXT: sw s6, 52(a0)
+; QCI-D-NEXT: sw s5, 48(a0)
+; QCI-D-NEXT: sw s4, 44(a0)
+; QCI-D-NEXT: sw s3, 40(a0)
+; QCI-D-NEXT: sw s2, 36(a0)
+; QCI-D-NEXT: sw t6, 32(a0)
+; QCI-D-NEXT: sw t5, 28(a0)
+; QCI-D-NEXT: sw t4, 24(a0)
+; QCI-D-NEXT: sw t3, 20(a0)
+; QCI-D-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: sw a1, 16(a0)
+; QCI-D-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: sw a1, 12(a0)
+; QCI-D-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: sw a1, 8(a0)
+; QCI-D-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: sw a1, 4(a0)
+; QCI-D-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: sw a1, 0(a0)
+; QCI-D-NEXT: lw s1, 60(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s2, 56(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s3, 52(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s4, 48(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s5, 44(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s6, 40(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s7, 36(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s8, 32(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s9, 28(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s10, 24(sp) # 4-byte Folded Reload
+; QCI-D-NEXT: lw s11, 20(sp) # 4-byte Folded Reload
; QCI-D-NEXT: .cfi_restore s1
; QCI-D-NEXT: .cfi_restore s2
; QCI-D-NEXT: .cfi_restore s3
@@ -1634,7 +1626,7 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-D-NEXT: .cfi_restore s9
; QCI-D-NEXT: .cfi_restore s10
; QCI-D-NEXT: .cfi_restore s11
-; QCI-D-NEXT: addi sp, sp, 80
+; QCI-D-NEXT: addi sp, sp, 64
; QCI-D-NEXT: .cfi_def_cfa_offset 96
; QCI-D-NEXT: qc.c.mileaveret
%1 = load [32 x i32], ptr @var
@@ -1729,61 +1721,61 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-F-NEXT: .cfi_offset ft10, -216
; QCI-F-NEXT: .cfi_offset ft11, -220
; QCI-F-NEXT: lui s0, %hi(var)
-; QCI-F-NEXT: lw a0, %lo(var)(s0)
+; QCI-F-NEXT: addi s0, s0, %lo(var)
+; QCI-F-NEXT: lw a0, 0(s0)
; QCI-F-NEXT: sw a0, 96(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+4)(s0)
+; QCI-F-NEXT: lw a0, 4(s0)
; QCI-F-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+8)(s0)
+; QCI-F-NEXT: lw a0, 8(s0)
; QCI-F-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+12)(s0)
+; QCI-F-NEXT: lw a0, 12(s0)
; QCI-F-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: addi s1, s0, %lo(var)
-; QCI-F-NEXT: lw a0, 16(s1)
+; QCI-F-NEXT: lw a0, 16(s0)
; QCI-F-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 20(s1)
+; QCI-F-NEXT: lw a0, 20(s0)
; QCI-F-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 24(s1)
+; QCI-F-NEXT: lw a0, 24(s0)
; QCI-F-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 28(s1)
+; QCI-F-NEXT: lw a0, 28(s0)
; QCI-F-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 32(s1)
+; QCI-F-NEXT: lw a0, 32(s0)
; QCI-F-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 36(s1)
+; QCI-F-NEXT: lw a0, 36(s0)
; QCI-F-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 40(s1)
+; QCI-F-NEXT: lw a0, 40(s0)
; QCI-F-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 44(s1)
+; QCI-F-NEXT: lw a0, 44(s0)
; QCI-F-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 48(s1)
+; QCI-F-NEXT: lw a0, 48(s0)
; QCI-F-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 52(s1)
+; QCI-F-NEXT: lw a0, 52(s0)
; QCI-F-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 56(s1)
+; QCI-F-NEXT: lw a0, 56(s0)
; QCI-F-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 60(s1)
+; QCI-F-NEXT: lw a0, 60(s0)
; QCI-F-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 64(s1)
+; QCI-F-NEXT: lw a0, 64(s0)
; QCI-F-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 68(s1)
+; QCI-F-NEXT: lw a0, 68(s0)
; QCI-F-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 72(s1)
+; QCI-F-NEXT: lw a0, 72(s0)
; QCI-F-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 76(s1)
+; QCI-F-NEXT: lw a0, 76(s0)
; QCI-F-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 80(s1)
+; QCI-F-NEXT: lw a0, 80(s0)
; QCI-F-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 84(s1)
+; QCI-F-NEXT: lw a0, 84(s0)
; QCI-F-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw s4, 88(s1)
-; QCI-F-NEXT: lw s5, 92(s1)
-; QCI-F-NEXT: lw s6, 96(s1)
-; QCI-F-NEXT: lw s7, 100(s1)
-; QCI-F-NEXT: lw s8, 104(s1)
-; QCI-F-NEXT: lw s9, 108(s1)
-; QCI-F-NEXT: lw s10, 112(s1)
-; QCI-F-NEXT: lw s11, 116(s1)
-; QCI-F-NEXT: lw s2, 120(s1)
-; QCI-F-NEXT: lw s3, 124(s1)
+; QCI-F-NEXT: lw s2, 88(s0)
+; QCI-F-NEXT: lw s3, 92(s0)
+; QCI-F-NEXT: lw s4, 96(s0)
+; QCI-F-NEXT: lw s5, 100(s0)
+; QCI-F-NEXT: lw s6, 104(s0)
+; QCI-F-NEXT: lw s7, 108(s0)
+; QCI-F-NEXT: lw s8, 112(s0)
+; QCI-F-NEXT: lw s9, 116(s0)
+; QCI-F-NEXT: lw s10, 120(s0)
+; QCI-F-NEXT: lw s11, 124(s0)
; QCI-F-NEXT: lui a7, 266496
; QCI-F-NEXT: li t0, 5
; QCI-F-NEXT: lui a0, 260096
@@ -1793,7 +1785,7 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-F-NEXT: lui a1, 264704
; QCI-F-NEXT: lui a6, 265216
; QCI-F-NEXT: fmv.w.x fa0, a0
-; QCI-F-NEXT: lui t1, 265728
+; QCI-F-NEXT: lui s1, 265728
; QCI-F-NEXT: fmv.w.x fa1, a2
; QCI-F-NEXT: lui a3, 266240
; QCI-F-NEXT: fmv.w.x fa2, a4
@@ -1804,7 +1796,7 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-F-NEXT: li a4, 3
; QCI-F-NEXT: fmv.w.x fa5, a6
; QCI-F-NEXT: li a6, 4
-; QCI-F-NEXT: fmv.w.x fa6, t1
+; QCI-F-NEXT: fmv.w.x fa6, s1
; QCI-F-NEXT: fmv.w.x fa7, a3
; QCI-F-NEXT: sw t0, 0(sp)
; QCI-F-NEXT: sw a7, 4(sp)
@@ -1814,60 +1806,60 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-F-NEXT: li a7, 0
; QCI-F-NEXT: call function_with_one_stack_arg
; QCI-F-NEXT: call use_float
-; QCI-F-NEXT: sw s3, 124(s1)
-; QCI-F-NEXT: sw s2, 120(s1)
-; QCI-F-NEXT: sw s11, 116(s1)
-; QCI-F-NEXT: sw s10, 112(s1)
-; QCI-F-NEXT: sw s9, 108(s1)
-; QCI-F-NEXT: sw s8, 104(s1)
-; QCI-F-NEXT: sw s7, 100(s1)
-; QCI-F-NEXT: sw s6, 96(s1)
-; QCI-F-NEXT: sw s5, 92(s1)
-; QCI-F-NEXT: sw s4, 88(s1)
+; QCI-F-NEXT: sw s11, 124(s0)
+; QCI-F-NEXT: sw s10, 120(s0)
+; QCI-F-NEXT: sw s9, 116(s0)
+; QCI-F-NEXT: sw s8, 112(s0)
+; QCI-F-NEXT: sw s7, 108(s0)
+; QCI-F-NEXT: sw s6, 104(s0)
+; QCI-F-NEXT: sw s5, 100(s0)
+; QCI-F-NEXT: sw s4, 96(s0)
+; QCI-F-NEXT: sw s3, 92(s0)
+; QCI-F-NEXT: sw s2, 88(s0)
; QCI-F-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 84(s1)
+; QCI-F-NEXT: sw a0, 84(s0)
; QCI-F-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 80(s1)
+; QCI-F-NEXT: sw a0, 80(s0)
; QCI-F-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 76(s1)
+; QCI-F-NEXT: sw a0, 76(s0)
; QCI-F-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 72(s1)
+; QCI-F-NEXT: sw a0, 72(s0)
; QCI-F-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 68(s1)
+; QCI-F-NEXT: sw a0, 68(s0)
; QCI-F-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 64(s1)
+; QCI-F-NEXT: sw a0, 64(s0)
; QCI-F-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 60(s1)
+; QCI-F-NEXT: sw a0, 60(s0)
; QCI-F-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 56(s1)
+; QCI-F-NEXT: sw a0, 56(s0)
; QCI-F-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 52(s1)
+; QCI-F-NEXT: sw a0, 52(s0)
; QCI-F-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 48(s1)
+; QCI-F-NEXT: sw a0, 48(s0)
; QCI-F-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 44(s1)
+; QCI-F-NEXT: sw a0, 44(s0)
; QCI-F-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 40(s1)
+; QCI-F-NEXT: sw a0, 40(s0)
; QCI-F-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 36(s1)
+; QCI-F-NEXT: sw a0, 36(s0)
; QCI-F-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 32(s1)
+; QCI-F-NEXT: sw a0, 32(s0)
; QCI-F-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 28(s1)
+; QCI-F-NEXT: sw a0, 28(s0)
; QCI-F-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 24(s1)
+; QCI-F-NEXT: sw a0, 24(s0)
; QCI-F-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 20(s1)
+; QCI-F-NEXT: sw a0, 20(s0)
; QCI-F-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 16(s1)
+; QCI-F-NEXT: sw a0, 16(s0)
; QCI-F-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+12)(s0)
+; QCI-F-NEXT: sw a0, 12(s0)
; QCI-F-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+8)(s0)
+; QCI-F-NEXT: sw a0, 8(s0)
; QCI-F-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+4)(s0)
+; QCI-F-NEXT: sw a0, 4(s0)
; QCI-F-NEXT: lw a0, 96(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var)(s0)
+; QCI-F-NEXT: sw a0, 0(s0)
; QCI-F-NEXT: lw s1, 220(sp) # 4-byte Folded Reload
; QCI-F-NEXT: lw s2, 216(sp) # 4-byte Folded Reload
; QCI-F-NEXT: lw s3, 212(sp) # 4-byte Folded Reload
@@ -2020,61 +2012,61 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-D-NEXT: .cfi_offset ft10, -296
; QCI-D-NEXT: .cfi_offset ft11, -304
; QCI-D-NEXT: lui s0, %hi(var)
-; QCI-D-NEXT: lw a0, %lo(var)(s0)
+; QCI-D-NEXT: addi s0, s0, %lo(var)
+; QCI-D-NEXT: lw a0, 0(s0)
; QCI-D-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+4)(s0)
+; QCI-D-NEXT: lw a0, 4(s0)
; QCI-D-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+8)(s0)
+; QCI-D-NEXT: lw a0, 8(s0)
; QCI-D-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+12)(s0)
+; QCI-D-NEXT: lw a0, 12(s0)
; QCI-D-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: addi s1, s0, %lo(var)
-; QCI-D-NEXT: lw a0, 16(s1)
+; QCI-D-NEXT: lw a0, 16(s0)
; QCI-D-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 20(s1)
+; QCI-D-NEXT: lw a0, 20(s0)
; QCI-D-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 24(s1)
+; QCI-D-NEXT: lw a0, 24(s0)
; QCI-D-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 28(s1)
+; QCI-D-NEXT: lw a0, 28(s0)
; QCI-D-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 32(s1)
+; QCI-D-NEXT: lw a0, 32(s0)
; QCI-D-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 36(s1)
+; QCI-D-NEXT: lw a0, 36(s0)
; QCI-D-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 40(s1)
+; QCI-D-NEXT: lw a0, 40(s0)
; QCI-D-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 44(s1)
+; QCI-D-NEXT: lw a0, 44(s0)
; QCI-D-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 48(s1)
+; QCI-D-NEXT: lw a0, 48(s0)
; QCI-D-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 52(s1)
+; QCI-D-NEXT: lw a0, 52(s0)
; QCI-D-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 56(s1)
+; QCI-D-NEXT: lw a0, 56(s0)
; QCI-D-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 60(s1)
+; QCI-D-NEXT: lw a0, 60(s0)
; QCI-D-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 64(s1)
+; QCI-D-NEXT: lw a0, 64(s0)
; QCI-D-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 68(s1)
+; QCI-D-NEXT: lw a0, 68(s0)
; QCI-D-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 72(s1)
+; QCI-D-NEXT: lw a0, 72(s0)
; QCI-D-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 76(s1)
+; QCI-D-NEXT: lw a0, 76(s0)
; QCI-D-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 80(s1)
+; QCI-D-NEXT: lw a0, 80(s0)
; QCI-D-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 84(s1)
+; QCI-D-NEXT: lw a0, 84(s0)
; QCI-D-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw s4, 88(s1)
-; QCI-D-NEXT: lw s5, 92(s1)
-; QCI-D-NEXT: lw s6, 96(s1)
-; QCI-D-NEXT: lw s7, 100(s1)
-; QCI-D-NEXT: lw s8, 104(s1)
-; QCI-D-NEXT: lw s9, 108(s1)
-; QCI-D-NEXT: lw s10, 112(s1)
-; QCI-D-NEXT: lw s11, 116(s1)
-; QCI-D-NEXT: lw s2, 120(s1)
-; QCI-D-NEXT: lw s3, 124(s1)
+; QCI-D-NEXT: lw s2, 88(s0)
+; QCI-D-NEXT: lw s3, 92(s0)
+; QCI-D-NEXT: lw s4, 96(s0)
+; QCI-D-NEXT: lw s5, 100(s0)
+; QCI-D-NEXT: lw s6, 104(s0)
+; QCI-D-NEXT: lw s7, 108(s0)
+; QCI-D-NEXT: lw s8, 112(s0)
+; QCI-D-NEXT: lw s9, 116(s0)
+; QCI-D-NEXT: lw s10, 120(s0)
+; QCI-D-NEXT: lw s11, 124(s0)
; QCI-D-NEXT: lui a7, 266496
; QCI-D-NEXT: li t0, 5
; QCI-D-NEXT: lui a0, 260096
@@ -2084,7 +2076,7 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-D-NEXT: lui a1, 264704
; QCI-D-NEXT: lui a6, 265216
; QCI-D-NEXT: fmv.w.x fa0, a0
-; QCI-D-NEXT: lui t1, 265728
+; QCI-D-NEXT: lui s1, 265728
; QCI-D-NEXT: fmv.w.x fa1, a2
; QCI-D-NEXT: lui a3, 266240
; QCI-D-NEXT: fmv.w.x fa2, a4
@@ -2095,7 +2087,7 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-D-NEXT: li a4, 3
; QCI-D-NEXT: fmv.w.x fa5, a6
; QCI-D-NEXT: li a6, 4
-; QCI-D-NEXT: fmv.w.x fa6, t1
+; QCI-D-NEXT: fmv.w.x fa6, s1
; QCI-D-NEXT: fmv.w.x fa7, a3
; QCI-D-NEXT: sw t0, 0(sp)
; QCI-D-NEXT: sw a7, 4(sp)
@@ -2105,60 +2097,60 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-D-NEXT: li a7, 0
; QCI-D-NEXT: call function_with_one_stack_arg
; QCI-D-NEXT: call use_float
-; QCI-D-NEXT: sw s3, 124(s1)
-; QCI-D-NEXT: sw s2, 120(s1)
-; QCI-D-NEXT: sw s11, 116(s1)
-; QCI-D-NEXT: sw s10, 112(s1)
-; QCI-D-NEXT: sw s9, 108(s1)
-; QCI-D-NEXT: sw s8, 104(s1)
-; QCI-D-NEXT: sw s7, 100(s1)
-; QCI-D-NEXT: sw s6, 96(s1)
-; QCI-D-NEXT: sw s5, 92(s1)
-; QCI-D-NEXT: sw s4, 88(s1)
+; QCI-D-NEXT: sw s11, 124(s0)
+; QCI-D-NEXT: sw s10, 120(s0)
+; QCI-D-NEXT: sw s9, 116(s0)
+; QCI-D-NEXT: sw s8, 112(s0)
+; QCI-D-NEXT: sw s7, 108(s0)
+; QCI-D-NEXT: sw s6, 104(s0)
+; QCI-D-NEXT: sw s5, 100(s0)
+; QCI-D-NEXT: sw s4, 96(s0)
+; QCI-D-NEXT: sw s3, 92(s0)
+; QCI-D-NEXT: sw s2, 88(s0)
; QCI-D-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 84(s1)
+; QCI-D-NEXT: sw a0, 84(s0)
; QCI-D-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 80(s1)
+; QCI-D-NEXT: sw a0, 80(s0)
; QCI-D-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 76(s1)
+; QCI-D-NEXT: sw a0, 76(s0)
; QCI-D-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 72(s1)
+; QCI-D-NEXT: sw a0, 72(s0)
; QCI-D-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 68(s1)
+; QCI-D-NEXT: sw a0, 68(s0)
; QCI-D-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 64(s1)
+; QCI-D-NEXT: sw a0, 64(s0)
; QCI-D-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 60(s1)
+; QCI-D-NEXT: sw a0, 60(s0)
; QCI-D-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 56(s1)
+; QCI-D-NEXT: sw a0, 56(s0)
; QCI-D-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 52(s1)
+; QCI-D-NEXT: sw a0, 52(s0)
; QCI-D-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 48(s1)
+; QCI-D-NEXT: sw a0, 48(s0)
; QCI-D-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 44(s1)
+; QCI-D-NEXT: sw a0, 44(s0)
; QCI-D-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 40(s1)
+; QCI-D-NEXT: sw a0, 40(s0)
; QCI-D-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 36(s1)
+; QCI-D-NEXT: sw a0, 36(s0)
; QCI-D-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 32(s1)
+; QCI-D-NEXT: sw a0, 32(s0)
; QCI-D-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 28(s1)
+; QCI-D-NEXT: sw a0, 28(s0)
; QCI-D-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 24(s1)
+; QCI-D-NEXT: sw a0, 24(s0)
; QCI-D-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 20(s1)
+; QCI-D-NEXT: sw a0, 20(s0)
; QCI-D-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 16(s1)
+; QCI-D-NEXT: sw a0, 16(s0)
; QCI-D-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+12)(s0)
+; QCI-D-NEXT: sw a0, 12(s0)
; QCI-D-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+8)(s0)
+; QCI-D-NEXT: sw a0, 8(s0)
; QCI-D-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+4)(s0)
+; QCI-D-NEXT: sw a0, 4(s0)
; QCI-D-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var)(s0)
+; QCI-D-NEXT: sw a0, 0(s0)
; QCI-D-NEXT: lw s1, 300(sp) # 4-byte Folded Reload
; QCI-D-NEXT: lw s2, 296(sp) # 4-byte Folded Reload
; QCI-D-NEXT: lw s3, 292(sp) # 4-byte Folded Reload
@@ -2318,61 +2310,61 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-F-NEXT: .cfi_offset ft10, -216
; QCI-F-NEXT: .cfi_offset ft11, -220
; QCI-F-NEXT: lui s0, %hi(var)
-; QCI-F-NEXT: lw a0, %lo(var)(s0)
+; QCI-F-NEXT: addi s0, s0, %lo(var)
+; QCI-F-NEXT: lw a0, 0(s0)
; QCI-F-NEXT: sw a0, 96(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+4)(s0)
+; QCI-F-NEXT: lw a0, 4(s0)
; QCI-F-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+8)(s0)
+; QCI-F-NEXT: lw a0, 8(s0)
; QCI-F-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, %lo(var+12)(s0)
+; QCI-F-NEXT: lw a0, 12(s0)
; QCI-F-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: addi s1, s0, %lo(var)
-; QCI-F-NEXT: lw a0, 16(s1)
+; QCI-F-NEXT: lw a0, 16(s0)
; QCI-F-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 20(s1)
+; QCI-F-NEXT: lw a0, 20(s0)
; QCI-F-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 24(s1)
+; QCI-F-NEXT: lw a0, 24(s0)
; QCI-F-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 28(s1)
+; QCI-F-NEXT: lw a0, 28(s0)
; QCI-F-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 32(s1)
+; QCI-F-NEXT: lw a0, 32(s0)
; QCI-F-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 36(s1)
+; QCI-F-NEXT: lw a0, 36(s0)
; QCI-F-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 40(s1)
+; QCI-F-NEXT: lw a0, 40(s0)
; QCI-F-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 44(s1)
+; QCI-F-NEXT: lw a0, 44(s0)
; QCI-F-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 48(s1)
+; QCI-F-NEXT: lw a0, 48(s0)
; QCI-F-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 52(s1)
+; QCI-F-NEXT: lw a0, 52(s0)
; QCI-F-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 56(s1)
+; QCI-F-NEXT: lw a0, 56(s0)
; QCI-F-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 60(s1)
+; QCI-F-NEXT: lw a0, 60(s0)
; QCI-F-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 64(s1)
+; QCI-F-NEXT: lw a0, 64(s0)
; QCI-F-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 68(s1)
+; QCI-F-NEXT: lw a0, 68(s0)
; QCI-F-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 72(s1)
+; QCI-F-NEXT: lw a0, 72(s0)
; QCI-F-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 76(s1)
+; QCI-F-NEXT: lw a0, 76(s0)
; QCI-F-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 80(s1)
+; QCI-F-NEXT: lw a0, 80(s0)
; QCI-F-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 84(s1)
+; QCI-F-NEXT: lw a0, 84(s0)
; QCI-F-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw s4, 88(s1)
-; QCI-F-NEXT: lw s5, 92(s1)
-; QCI-F-NEXT: lw s6, 96(s1)
-; QCI-F-NEXT: lw s7, 100(s1)
-; QCI-F-NEXT: lw s8, 104(s1)
-; QCI-F-NEXT: lw s9, 108(s1)
-; QCI-F-NEXT: lw s10, 112(s1)
-; QCI-F-NEXT: lw s11, 116(s1)
-; QCI-F-NEXT: lw s2, 120(s1)
-; QCI-F-NEXT: lw s3, 124(s1)
+; QCI-F-NEXT: lw s2, 88(s0)
+; QCI-F-NEXT: lw s3, 92(s0)
+; QCI-F-NEXT: lw s4, 96(s0)
+; QCI-F-NEXT: lw s5, 100(s0)
+; QCI-F-NEXT: lw s6, 104(s0)
+; QCI-F-NEXT: lw s7, 108(s0)
+; QCI-F-NEXT: lw s8, 112(s0)
+; QCI-F-NEXT: lw s9, 116(s0)
+; QCI-F-NEXT: lw s10, 120(s0)
+; QCI-F-NEXT: lw s11, 124(s0)
; QCI-F-NEXT: lui a7, 266496
; QCI-F-NEXT: li t0, 5
; QCI-F-NEXT: lui a0, 260096
@@ -2382,7 +2374,7 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-F-NEXT: lui a1, 264704
; QCI-F-NEXT: lui a6, 265216
; QCI-F-NEXT: fmv.w.x fa0, a0
-; QCI-F-NEXT: lui t1, 265728
+; QCI-F-NEXT: lui s1, 265728
; QCI-F-NEXT: fmv.w.x fa1, a2
; QCI-F-NEXT: lui a3, 266240
; QCI-F-NEXT: fmv.w.x fa2, a4
@@ -2393,7 +2385,7 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-F-NEXT: li a4, 3
; QCI-F-NEXT: fmv.w.x fa5, a6
; QCI-F-NEXT: li a6, 4
-; QCI-F-NEXT: fmv.w.x fa6, t1
+; QCI-F-NEXT: fmv.w.x fa6, s1
; QCI-F-NEXT: fmv.w.x fa7, a3
; QCI-F-NEXT: sw t0, 0(sp)
; QCI-F-NEXT: sw a7, 4(sp)
@@ -2403,60 +2395,60 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-F-NEXT: li a7, 0
; QCI-F-NEXT: call function_with_one_stack_arg
; QCI-F-NEXT: call use_float
-; QCI-F-NEXT: sw s3, 124(s1)
-; QCI-F-NEXT: sw s2, 120(s1)
-; QCI-F-NEXT: sw s11, 116(s1)
-; QCI-F-NEXT: sw s10, 112(s1)
-; QCI-F-NEXT: sw s9, 108(s1)
-; QCI-F-NEXT: sw s8, 104(s1)
-; QCI-F-NEXT: sw s7, 100(s1)
-; QCI-F-NEXT: sw s6, 96(s1)
-; QCI-F-NEXT: sw s5, 92(s1)
-; QCI-F-NEXT: sw s4, 88(s1)
+; QCI-F-NEXT: sw s11, 124(s0)
+; QCI-F-NEXT: sw s10, 120(s0)
+; QCI-F-NEXT: sw s9, 116(s0)
+; QCI-F-NEXT: sw s8, 112(s0)
+; QCI-F-NEXT: sw s7, 108(s0)
+; QCI-F-NEXT: sw s6, 104(s0)
+; QCI-F-NEXT: sw s5, 100(s0)
+; QCI-F-NEXT: sw s4, 96(s0)
+; QCI-F-NEXT: sw s3, 92(s0)
+; QCI-F-NEXT: sw s2, 88(s0)
; QCI-F-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 84(s1)
+; QCI-F-NEXT: sw a0, 84(s0)
; QCI-F-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 80(s1)
+; QCI-F-NEXT: sw a0, 80(s0)
; QCI-F-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 76(s1)
+; QCI-F-NEXT: sw a0, 76(s0)
; QCI-F-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 72(s1)
+; QCI-F-NEXT: sw a0, 72(s0)
; QCI-F-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 68(s1)
+; QCI-F-NEXT: sw a0, 68(s0)
; QCI-F-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 64(s1)
+; QCI-F-NEXT: sw a0, 64(s0)
; QCI-F-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 60(s1)
+; QCI-F-NEXT: sw a0, 60(s0)
; QCI-F-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 56(s1)
+; QCI-F-NEXT: sw a0, 56(s0)
; QCI-F-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 52(s1)
+; QCI-F-NEXT: sw a0, 52(s0)
; QCI-F-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 48(s1)
+; QCI-F-NEXT: sw a0, 48(s0)
; QCI-F-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 44(s1)
+; QCI-F-NEXT: sw a0, 44(s0)
; QCI-F-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 40(s1)
+; QCI-F-NEXT: sw a0, 40(s0)
; QCI-F-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 36(s1)
+; QCI-F-NEXT: sw a0, 36(s0)
; QCI-F-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 32(s1)
+; QCI-F-NEXT: sw a0, 32(s0)
; QCI-F-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 28(s1)
+; QCI-F-NEXT: sw a0, 28(s0)
; QCI-F-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 24(s1)
+; QCI-F-NEXT: sw a0, 24(s0)
; QCI-F-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 20(s1)
+; QCI-F-NEXT: sw a0, 20(s0)
; QCI-F-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 16(s1)
+; QCI-F-NEXT: sw a0, 16(s0)
; QCI-F-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+12)(s0)
+; QCI-F-NEXT: sw a0, 12(s0)
; QCI-F-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+8)(s0)
+; QCI-F-NEXT: sw a0, 8(s0)
; QCI-F-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var+4)(s0)
+; QCI-F-NEXT: sw a0, 4(s0)
; QCI-F-NEXT: lw a0, 96(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, %lo(var)(s0)
+; QCI-F-NEXT: sw a0, 0(s0)
; QCI-F-NEXT: lw s1, 220(sp) # 4-byte Folded Reload
; QCI-F-NEXT: lw s2, 216(sp) # 4-byte Folded Reload
; QCI-F-NEXT: lw s3, 212(sp) # 4-byte Folded Reload
@@ -2609,61 +2601,61 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-D-NEXT: .cfi_offset ft10, -296
; QCI-D-NEXT: .cfi_offset ft11, -304
; QCI-D-NEXT: lui s0, %hi(var)
-; QCI-D-NEXT: lw a0, %lo(var)(s0)
+; QCI-D-NEXT: addi s0, s0, %lo(var)
+; QCI-D-NEXT: lw a0, 0(s0)
; QCI-D-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+4)(s0)
+; QCI-D-NEXT: lw a0, 4(s0)
; QCI-D-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+8)(s0)
+; QCI-D-NEXT: lw a0, 8(s0)
; QCI-D-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, %lo(var+12)(s0)
+; QCI-D-NEXT: lw a0, 12(s0)
; QCI-D-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: addi s1, s0, %lo(var)
-; QCI-D-NEXT: lw a0, 16(s1)
+; QCI-D-NEXT: lw a0, 16(s0)
; QCI-D-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 20(s1)
+; QCI-D-NEXT: lw a0, 20(s0)
; QCI-D-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 24(s1)
+; QCI-D-NEXT: lw a0, 24(s0)
; QCI-D-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 28(s1)
+; QCI-D-NEXT: lw a0, 28(s0)
; QCI-D-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 32(s1)
+; QCI-D-NEXT: lw a0, 32(s0)
; QCI-D-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 36(s1)
+; QCI-D-NEXT: lw a0, 36(s0)
; QCI-D-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 40(s1)
+; QCI-D-NEXT: lw a0, 40(s0)
; QCI-D-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 44(s1)
+; QCI-D-NEXT: lw a0, 44(s0)
; QCI-D-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 48(s1)
+; QCI-D-NEXT: lw a0, 48(s0)
; QCI-D-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 52(s1)
+; QCI-D-NEXT: lw a0, 52(s0)
; QCI-D-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 56(s1)
+; QCI-D-NEXT: lw a0, 56(s0)
; QCI-D-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 60(s1)
+; QCI-D-NEXT: lw a0, 60(s0)
; QCI-D-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 64(s1)
+; QCI-D-NEXT: lw a0, 64(s0)
; QCI-D-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 68(s1)
+; QCI-D-NEXT: lw a0, 68(s0)
; QCI-D-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 72(s1)
+; QCI-D-NEXT: lw a0, 72(s0)
; QCI-D-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 76(s1)
+; QCI-D-NEXT: lw a0, 76(s0)
; QCI-D-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 80(s1)
+; QCI-D-NEXT: lw a0, 80(s0)
; QCI-D-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 84(s1)
+; QCI-D-NEXT: lw a0, 84(s0)
; QCI-D-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw s4, 88(s1)
-; QCI-D-NEXT: lw s5, 92(s1)
-; QCI-D-NEXT: lw s6, 96(s1)
-; QCI-D-NEXT: lw s7, 100(s1)
-; QCI-D-NEXT: lw s8, 104(s1)
-; QCI-D-NEXT: lw s9, 108(s1)
-; QCI-D-NEXT: lw s10, 112(s1)
-; QCI-D-NEXT: lw s11, 116(s1)
-; QCI-D-NEXT: lw s2, 120(s1)
-; QCI-D-NEXT: lw s3, 124(s1)
+; QCI-D-NEXT: lw s2, 88(s0)
+; QCI-D-NEXT: lw s3, 92(s0)
+; QCI-D-NEXT: lw s4, 96(s0)
+; QCI-D-NEXT: lw s5, 100(s0)
+; QCI-D-NEXT: lw s6, 104(s0)
+; QCI-D-NEXT: lw s7, 108(s0)
+; QCI-D-NEXT: lw s8, 112(s0)
+; QCI-D-NEXT: lw s9, 116(s0)
+; QCI-D-NEXT: lw s10, 120(s0)
+; QCI-D-NEXT: lw s11, 124(s0)
; QCI-D-NEXT: lui a7, 266496
; QCI-D-NEXT: li t0, 5
; QCI-D-NEXT: lui a0, 260096
@@ -2673,7 +2665,7 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-D-NEXT: lui a1, 264704
; QCI-D-NEXT: lui a6, 265216
; QCI-D-NEXT: fmv.w.x fa0, a0
-; QCI-D-NEXT: lui t1, 265728
+; QCI-D-NEXT: lui s1, 265728
; QCI-D-NEXT: fmv.w.x fa1, a2
; QCI-D-NEXT: lui a3, 266240
; QCI-D-NEXT: fmv.w.x fa2, a4
@@ -2684,7 +2676,7 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-D-NEXT: li a4, 3
; QCI-D-NEXT: fmv.w.x fa5, a6
; QCI-D-NEXT: li a6, 4
-; QCI-D-NEXT: fmv.w.x fa6, t1
+; QCI-D-NEXT: fmv.w.x fa6, s1
; QCI-D-NEXT: fmv.w.x fa7, a3
; QCI-D-NEXT: sw t0, 0(sp)
; QCI-D-NEXT: sw a7, 4(sp)
@@ -2694,60 +2686,60 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-D-NEXT: li a7, 0
; QCI-D-NEXT: call function_with_one_stack_arg
; QCI-D-NEXT: call use_float
-; QCI-D-NEXT: sw s3, 124(s1)
-; QCI-D-NEXT: sw s2, 120(s1)
-; QCI-D-NEXT: sw s11, 116(s1)
-; QCI-D-NEXT: sw s10, 112(s1)
-; QCI-D-NEXT: sw s9, 108(s1)
-; QCI-D-NEXT: sw s8, 104(s1)
-; QCI-D-NEXT: sw s7, 100(s1)
-; QCI-D-NEXT: sw s6, 96(s1)
-; QCI-D-NEXT: sw s5, 92(s1)
-; QCI-D-NEXT: sw s4, 88(s1)
+; QCI-D-NEXT: sw s11, 124(s0)
+; QCI-D-NEXT: sw s10, 120(s0)
+; QCI-D-NEXT: sw s9, 116(s0)
+; QCI-D-NEXT: sw s8, 112(s0)
+; QCI-D-NEXT: sw s7, 108(s0)
+; QCI-D-NEXT: sw s6, 104(s0)
+; QCI-D-NEXT: sw s5, 100(s0)
+; QCI-D-NEXT: sw s4, 96(s0)
+; QCI-D-NEXT: sw s3, 92(s0)
+; QCI-D-NEXT: sw s2, 88(s0)
; QCI-D-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 84(s1)
+; QCI-D-NEXT: sw a0, 84(s0)
; QCI-D-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 80(s1)
+; QCI-D-NEXT: sw a0, 80(s0)
; QCI-D-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 76(s1)
+; QCI-D-NEXT: sw a0, 76(s0)
; QCI-D-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 72(s1)
+; QCI-D-NEXT: sw a0, 72(s0)
; QCI-D-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 68(s1)
+; QCI-D-NEXT: sw a0, 68(s0)
; QCI-D-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 64(s1)
+; QCI-D-NEXT: sw a0, 64(s0)
; QCI-D-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 60(s1)
+; QCI-D-NEXT: sw a0, 60(s0)
; QCI-D-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 56(s1)
+; QCI-D-NEXT: sw a0, 56(s0)
; QCI-D-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 52(s1)
+; QCI-D-NEXT: sw a0, 52(s0)
; QCI-D-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 48(s1)
+; QCI-D-NEXT: sw a0, 48(s0)
; QCI-D-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 44(s1)
+; QCI-D-NEXT: sw a0, 44(s0)
; QCI-D-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 40(s1)
+; QCI-D-NEXT: sw a0, 40(s0)
; QCI-D-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 36(s1)
+; QCI-D-NEXT: sw a0, 36(s0)
; QCI-D-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 32(s1)
+; QCI-D-NEXT: sw a0, 32(s0)
; QCI-D-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 28(s1)
+; QCI-D-NEXT: sw a0, 28(s0)
; QCI-D-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 24(s1)
+; QCI-D-NEXT: sw a0, 24(s0)
; QCI-D-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 20(s1)
+; QCI-D-NEXT: sw a0, 20(s0)
; QCI-D-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 16(s1)
+; QCI-D-NEXT: sw a0, 16(s0)
; QCI-D-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+12)(s0)
+; QCI-D-NEXT: sw a0, 12(s0)
; QCI-D-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+8)(s0)
+; QCI-D-NEXT: sw a0, 8(s0)
; QCI-D-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var+4)(s0)
+; QCI-D-NEXT: sw a0, 4(s0)
; QCI-D-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, %lo(var)(s0)
+; QCI-D-NEXT: sw a0, 0(s0)
; QCI-D-NEXT: lw s1, 300(sp) # 4-byte Folded Reload
; QCI-D-NEXT: lw s2, 296(sp) # 4-byte Folded Reload
; QCI-D-NEXT: lw s3, 292(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll b/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
index 03e10bba6af58..bcd2c3820328d 100644
--- a/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+++ b/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
@@ -1009,19 +1009,19 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-NEXT: .cfi_offset t4, -72
; QCI-NEXT: .cfi_offset t5, -76
; QCI-NEXT: .cfi_offset t6, -80
-; QCI-NEXT: addi sp, sp, -80
-; QCI-NEXT: .cfi_def_cfa_offset 176
-; QCI-NEXT: sw s1, 76(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s2, 72(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s3, 68(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s4, 64(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s5, 60(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s6, 56(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s7, 52(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s8, 48(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s9, 44(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s10, 40(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s11, 36(sp) # 4-byte Folded Spill
+; QCI-NEXT: addi sp, sp, -64
+; QCI-NEXT: .cfi_def_cfa_offset 160
+; QCI-NEXT: sw s1, 60(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s2, 56(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s3, 52(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s4, 48(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s5, 44(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s6, 40(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s7, 36(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s8, 32(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s9, 28(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s10, 24(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s11, 20(sp) # 4-byte Folded Spill
; QCI-NEXT: .cfi_offset s1, -100
; QCI-NEXT: .cfi_offset s2, -104
; QCI-NEXT: .cfi_offset s3, -108
@@ -1033,95 +1033,93 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-NEXT: .cfi_offset s9, -132
; QCI-NEXT: .cfi_offset s10, -136
; QCI-NEXT: .cfi_offset s11, -140
-; QCI-NEXT: lui t0, %hi(var)
-; QCI-NEXT: lw a0, %lo(var)(t0)
-; QCI-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+4)(t0)
-; QCI-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+8)(t0)
-; QCI-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+12)(t0)
-; QCI-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-NEXT: addi a5, t0, %lo(var)
-; QCI-NEXT: lw a0, 16(a5)
-; QCI-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 20(a5)
-; QCI-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw t4, 24(a5)
-; QCI-NEXT: lw t5, 28(a5)
-; QCI-NEXT: lw t6, 32(a5)
-; QCI-NEXT: lw s2, 36(a5)
-; QCI-NEXT: lw s3, 40(a5)
-; QCI-NEXT: lw s4, 44(a5)
-; QCI-NEXT: lw s5, 48(a5)
-; QCI-NEXT: lw s6, 52(a5)
-; QCI-NEXT: lw s7, 56(a5)
-; QCI-NEXT: lw s8, 60(a5)
-; QCI-NEXT: lw s9, 64(a5)
-; QCI-NEXT: lw s10, 68(a5)
-; QCI-NEXT: lw s11, 72(a5)
-; QCI-NEXT: lw ra, 76(a5)
-; QCI-NEXT: lw s1, 80(a5)
-; QCI-NEXT: lw t3, 84(a5)
-; QCI-NEXT: lw t2, 88(a5)
-; QCI-NEXT: lw t1, 92(a5)
-; QCI-NEXT: lw a7, 112(a5)
-; QCI-NEXT: lw s0, 116(a5)
-; QCI-NEXT: lw a3, 120(a5)
-; QCI-NEXT: lw a0, 124(a5)
-; QCI-NEXT: lw a6, 96(a5)
-; QCI-NEXT: lw a4, 100(a5)
-; QCI-NEXT: lw a2, 104(a5)
-; QCI-NEXT: lw a1, 108(a5)
-; QCI-NEXT: sw a0, 124(a5)
-; QCI-NEXT: sw a3, 120(a5)
-; QCI-NEXT: sw s0, 116(a5)
-; QCI-NEXT: sw a7, 112(a5)
-; QCI-NEXT: sw a1, 108(a5)
-; QCI-NEXT: sw a2, 104(a5)
-; QCI-NEXT: sw a4, 100(a5)
-; QCI-NEXT: sw a6, 96(a5)
-; QCI-NEXT: sw t1, 92(a5)
-; QCI-NEXT: sw t2, 88(a5)
-; QCI-NEXT: sw t3, 84(a5)
-; QCI-NEXT: sw s1, 80(a5)
-; QCI-NEXT: sw ra, 76(a5)
-; QCI-NEXT: sw s11, 72(a5)
-; QCI-NEXT: sw s10, 68(a5)
-; QCI-NEXT: sw s9, 64(a5)
-; QCI-NEXT: sw s8, 60(a5)
-; QCI-NEXT: sw s7, 56(a5)
-; QCI-NEXT: sw s6, 52(a5)
-; QCI-NEXT: sw s5, 48(a5)
-; QCI-NEXT: sw s4, 44(a5)
-; QCI-NEXT: sw s3, 40(a5)
-; QCI-NEXT: sw s2, 36(a5)
-; QCI-NEXT: sw t6, 32(a5)
-; QCI-NEXT: sw t5, 28(a5)
-; QCI-NEXT: sw t4, 24(a5)
-; QCI-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 20(a5)
-; QCI-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 16(a5)
-; QCI-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+12)(t0)
-; QCI-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+8)(t0)
-; QCI-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+4)(t0)
-; QCI-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var)(t0)
-; QCI-NEXT: lw s1, 76(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s2, 72(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s3, 68(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s4, 64(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s5, 60(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s6, 56(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s7, 52(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s8, 48(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s9, 44(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s10, 40(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s11, 36(sp) # 4-byte Folded Reload
+; QCI-NEXT: lui a0, %hi(var)
+; QCI-NEXT: addi a0, a0, %lo(var)
+; QCI-NEXT: lw a1, 0(a0)
+; QCI-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; QCI-NEXT: lw a1, 4(a0)
+; QCI-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; QCI-NEXT: lw a1, 8(a0)
+; QCI-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; QCI-NEXT: lw a1, 12(a0)
+; QCI-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; QCI-NEXT: lw a1, 16(a0)
+; QCI-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; QCI-NEXT: lw t3, 20(a0)
+; QCI-NEXT: lw t4, 24(a0)
+; QCI-NEXT: lw t5, 28(a0)
+; QCI-NEXT: lw t6, 32(a0)
+; QCI-NEXT: lw s2, 36(a0)
+; QCI-NEXT: lw s3, 40(a0)
+; QCI-NEXT: lw s4, 44(a0)
+; QCI-NEXT: lw s5, 48(a0)
+; QCI-NEXT: lw s6, 52(a0)
+; QCI-NEXT: lw s7, 56(a0)
+; QCI-NEXT: lw s8, 60(a0)
+; QCI-NEXT: lw s9, 64(a0)
+; QCI-NEXT: lw s10, 68(a0)
+; QCI-NEXT: lw s11, 72(a0)
+; QCI-NEXT: lw ra, 76(a0)
+; QCI-NEXT: lw t2, 80(a0)
+; QCI-NEXT: lw s0, 84(a0)
+; QCI-NEXT: lw s1, 88(a0)
+; QCI-NEXT: lw t1, 92(a0)
+; QCI-NEXT: lw t0, 112(a0)
+; QCI-NEXT: lw a5, 116(a0)
+; QCI-NEXT: lw a3, 120(a0)
+; QCI-NEXT: lw a1, 124(a0)
+; QCI-NEXT: lw a7, 96(a0)
+; QCI-NEXT: lw a6, 100(a0)
+; QCI-NEXT: lw a4, 104(a0)
+; QCI-NEXT: lw a2, 108(a0)
+; QCI-NEXT: sw a1, 124(a0)
+; QCI-NEXT: sw a3, 120(a0)
+; QCI-NEXT: sw a5, 116(a0)
+; QCI-NEXT: sw t0, 112(a0)
+; QCI-NEXT: sw a2, 108(a0)
+; QCI-NEXT: sw a4, 104(a0)
+; QCI-NEXT: sw a6, 100(a0)
+; QCI-NEXT: sw a7, 96(a0)
+; QCI-NEXT: sw t1, 92(a0)
+; QCI-NEXT: sw s1, 88(a0)
+; QCI-NEXT: sw s0, 84(a0)
+; QCI-NEXT: sw t2, 80(a0)
+; QCI-NEXT: sw ra, 76(a0)
+; QCI-NEXT: sw s11, 72(a0)
+; QCI-NEXT: sw s10, 68(a0)
+; QCI-NEXT: sw s9, 64(a0)
+; QCI-NEXT: sw s8, 60(a0)
+; QCI-NEXT: sw s7, 56(a0)
+; QCI-NEXT: sw s6, 52(a0)
+; QCI-NEXT: sw s5, 48(a0)
+; QCI-NEXT: sw s4, 44(a0)
+; QCI-NEXT: sw s3, 40(a0)
+; QCI-NEXT: sw s2, 36(a0)
+; QCI-NEXT: sw t6, 32(a0)
+; QCI-NEXT: sw t5, 28(a0)
+; QCI-NEXT: sw t4, 24(a0)
+; QCI-NEXT: sw t3, 20(a0)
+; QCI-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; QCI-NEXT: sw a1, 16(a0)
+; QCI-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; QCI-NEXT: sw a1, 12(a0)
+; QCI-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; QCI-NEXT: sw a1, 8(a0)
+; QCI-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; QCI-NEXT: sw a1, 4(a0)
+; QCI-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; QCI-NEXT: sw a1, 0(a0)
+; QCI-NEXT: lw s1, 60(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s2, 56(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s3, 52(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s4, 48(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s5, 44(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s6, 40(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s7, 36(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s8, 32(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s9, 28(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s10, 24(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s11, 20(sp) # 4-byte Folded Reload
; QCI-NEXT: .cfi_restore s1
; QCI-NEXT: .cfi_restore s2
; QCI-NEXT: .cfi_restore s3
@@ -1133,7 +1131,7 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-NEXT: .cfi_restore s9
; QCI-NEXT: .cfi_restore s10
; QCI-NEXT: .cfi_restore s11
-; QCI-NEXT: addi sp, sp, 80
+; QCI-NEXT: addi sp, sp, 64
; QCI-NEXT: .cfi_def_cfa_offset 96
; QCI-NEXT: qc.c.mileaveret
;
@@ -1183,86 +1181,84 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-FP-NEXT: .cfi_offset s10, -136
; QCI-FP-NEXT: .cfi_offset s11, -140
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
-; QCI-FP-NEXT: lui t1, %hi(var)
-; QCI-FP-NEXT: lw a0, %lo(var)(t1)
-; QCI-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+4)(t1)
-; QCI-FP-NEXT: sw a0, -148(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+8)(t1)
-; QCI-FP-NEXT: sw a0, -152(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+12)(t1)
-; QCI-FP-NEXT: sw a0, -156(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: addi a5, t1, %lo(var)
-; QCI-FP-NEXT: lw a0, 16(a5)
-; QCI-FP-NEXT: sw a0, -160(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, 20(a5)
-; QCI-FP-NEXT: sw a0, -164(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, 24(a5)
-; QCI-FP-NEXT: sw a0, -168(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw t5, 28(a5)
-; QCI-FP-NEXT: lw t6, 32(a5)
-; QCI-FP-NEXT: lw s2, 36(a5)
-; QCI-FP-NEXT: lw s3, 40(a5)
-; QCI-FP-NEXT: lw s4, 44(a5)
-; QCI-FP-NEXT: lw s5, 48(a5)
-; QCI-FP-NEXT: lw s6, 52(a5)
-; QCI-FP-NEXT: lw s7, 56(a5)
-; QCI-FP-NEXT: lw s8, 60(a5)
-; QCI-FP-NEXT: lw s9, 64(a5)
-; QCI-FP-NEXT: lw s10, 68(a5)
-; QCI-FP-NEXT: lw s11, 72(a5)
-; QCI-FP-NEXT: lw ra, 76(a5)
-; QCI-FP-NEXT: lw t4, 80(a5)
-; QCI-FP-NEXT: lw t3, 84(a5)
-; QCI-FP-NEXT: lw t2, 88(a5)
-; QCI-FP-NEXT: lw s1, 92(a5)
-; QCI-FP-NEXT: lw t0, 112(a5)
-; QCI-FP-NEXT: lw a4, 116(a5)
-; QCI-FP-NEXT: lw a3, 120(a5)
-; QCI-FP-NEXT: lw a0, 124(a5)
-; QCI-FP-NEXT: lw a7, 96(a5)
-; QCI-FP-NEXT: lw a6, 100(a5)
-; QCI-FP-NEXT: lw a2, 104(a5)
-; QCI-FP-NEXT: lw a1, 108(a5)
-; QCI-FP-NEXT: sw a0, 124(a5)
-; QCI-FP-NEXT: sw a3, 120(a5)
-; QCI-FP-NEXT: sw a4, 116(a5)
-; QCI-FP-NEXT: sw t0, 112(a5)
-; QCI-FP-NEXT: sw a1, 108(a5)
-; QCI-FP-NEXT: sw a2, 104(a5)
-; QCI-FP-NEXT: sw a6, 100(a5)
-; QCI-FP-NEXT: sw a7, 96(a5)
-; QCI-FP-NEXT: sw s1, 92(a5)
-; QCI-FP-NEXT: sw t2, 88(a5)
-; QCI-FP-NEXT: sw t3, 84(a5)
-; QCI-FP-NEXT: sw t4, 80(a5)
-; QCI-FP-NEXT: sw ra, 76(a5)
-; QCI-FP-NEXT: sw s11, 72(a5)
-; QCI-FP-NEXT: sw s10, 68(a5)
-; QCI-FP-NEXT: sw s9, 64(a5)
-; QCI-FP-NEXT: sw s8, 60(a5)
-; QCI-FP-NEXT: sw s7, 56(a5)
-; QCI-FP-NEXT: sw s6, 52(a5)
-; QCI-FP-NEXT: sw s5, 48(a5)
-; QCI-FP-NEXT: sw s4, 44(a5)
-; QCI-FP-NEXT: sw s3, 40(a5)
-; QCI-FP-NEXT: sw s2, 36(a5)
-; QCI-FP-NEXT: sw t6, 32(a5)
-; QCI-FP-NEXT: sw t5, 28(a5)
-; QCI-FP-NEXT: lw a0, -168(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, 24(a5)
-; QCI-FP-NEXT: lw a0, -164(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, 20(a5)
-; QCI-FP-NEXT: lw a0, -160(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, 16(a5)
-; QCI-FP-NEXT: lw a0, -156(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+12)(t1)
-; QCI-FP-NEXT: lw a0, -152(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+8)(t1)
-; QCI-FP-NEXT: lw a0, -148(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+4)(t1)
-; QCI-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var)(t1)
+; QCI-FP-NEXT: lui a0, %hi(var)
+; QCI-FP-NEXT: addi a0, a0, %lo(var)
+; QCI-FP-NEXT: lw a1, 0(a0)
+; QCI-FP-NEXT: sw a1, -144(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw a1, 4(a0)
+; QCI-FP-NEXT: sw a1, -148(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw a1, 8(a0)
+; QCI-FP-NEXT: sw a1, -152(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw a1, 12(a0)
+; QCI-FP-NEXT: sw a1, -156(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw a1, 16(a0)
+; QCI-FP-NEXT: sw a1, -160(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw a1, 20(a0)
+; QCI-FP-NEXT: sw a1, -164(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw t4, 24(a0)
+; QCI-FP-NEXT: lw t5, 28(a0)
+; QCI-FP-NEXT: lw t6, 32(a0)
+; QCI-FP-NEXT: lw s2, 36(a0)
+; QCI-FP-NEXT: lw s3, 40(a0)
+; QCI-FP-NEXT: lw s4, 44(a0)
+; QCI-FP-NEXT: lw s5, 48(a0)
+; QCI-FP-NEXT: lw s6, 52(a0)
+; QCI-FP-NEXT: lw s7, 56(a0)
+; QCI-FP-NEXT: lw s8, 60(a0)
+; QCI-FP-NEXT: lw s9, 64(a0)
+; QCI-FP-NEXT: lw s10, 68(a0)
+; QCI-FP-NEXT: lw s11, 72(a0)
+; QCI-FP-NEXT: lw ra, 76(a0)
+; QCI-FP-NEXT: lw s1, 80(a0)
+; QCI-FP-NEXT: lw t3, 84(a0)
+; QCI-FP-NEXT: lw t2, 88(a0)
+; QCI-FP-NEXT: lw t1, 92(a0)
+; QCI-FP-NEXT: lw t0, 112(a0)
+; QCI-FP-NEXT: lw a6, 116(a0)
+; QCI-FP-NEXT: lw a4, 120(a0)
+; QCI-FP-NEXT: lw a1, 124(a0)
+; QCI-FP-NEXT: lw a7, 96(a0)
+; QCI-FP-NEXT: lw a5, 100(a0)
+; QCI-FP-NEXT: lw a3, 104(a0)
+; QCI-FP-NEXT: lw a2, 108(a0)
+; QCI-FP-NEXT: sw a1, 124(a0)
+; QCI-FP-NEXT: sw a4, 120(a0)
+; QCI-FP-NEXT: sw a6, 116(a0)
+; QCI-FP-NEXT: sw t0, 112(a0)
+; QCI-FP-NEXT: sw a2, 108(a0)
+; QCI-FP-NEXT: sw a3, 104(a0)
+; QCI-FP-NEXT: sw a5, 100(a0)
+; QCI-FP-NEXT: sw a7, 96(a0)
+; QCI-FP-NEXT: sw t1, 92(a0)
+; QCI-FP-NEXT: sw t2, 88(a0)
+; QCI-FP-NEXT: sw t3, 84(a0)
+; QCI-FP-NEXT: sw s1, 80(a0)
+; QCI-FP-NEXT: sw ra, 76(a0)
+; QCI-FP-NEXT: sw s11, 72(a0)
+; QCI-FP-NEXT: sw s10, 68(a0)
+; QCI-FP-NEXT: sw s9, 64(a0)
+; QCI-FP-NEXT: sw s8, 60(a0)
+; QCI-FP-NEXT: sw s7, 56(a0)
+; QCI-FP-NEXT: sw s6, 52(a0)
+; QCI-FP-NEXT: sw s5, 48(a0)
+; QCI-FP-NEXT: sw s4, 44(a0)
+; QCI-FP-NEXT: sw s3, 40(a0)
+; QCI-FP-NEXT: sw s2, 36(a0)
+; QCI-FP-NEXT: sw t6, 32(a0)
+; QCI-FP-NEXT: sw t5, 28(a0)
+; QCI-FP-NEXT: sw t4, 24(a0)
+; QCI-FP-NEXT: lw a1, -164(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 20(a0)
+; QCI-FP-NEXT: lw a1, -160(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 16(a0)
+; QCI-FP-NEXT: lw a1, -156(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 12(a0)
+; QCI-FP-NEXT: lw a1, -152(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 8(a0)
+; QCI-FP-NEXT: lw a1, -148(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 4(a0)
+; QCI-FP-NEXT: lw a1, -144(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 0(a0)
; QCI-FP-NEXT: .cfi_def_cfa sp, 176
; QCI-FP-NEXT: lw s1, 76(sp) # 4-byte Folded Reload
; QCI-FP-NEXT: lw s2, 72(sp) # 4-byte Folded Reload
@@ -1324,84 +1320,82 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-PUSH-POP-NEXT: .cfi_offset s9, -108
; QCI-PUSH-POP-NEXT: .cfi_offset s10, -104
; QCI-PUSH-POP-NEXT: .cfi_offset s11, -100
-; QCI-PUSH-POP-NEXT: lui t0, %hi(var)
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var)(t0)
-; QCI-PUSH-POP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+4)(t0)
-; QCI-PUSH-POP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+8)(t0)
-; QCI-PUSH-POP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+12)(t0)
-; QCI-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: addi a5, t0, %lo(var)
-; QCI-PUSH-POP-NEXT: lw a0, 16(a5)
-; QCI-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 20(a5)
-; QCI-PUSH-POP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw t4, 24(a5)
-; QCI-PUSH-POP-NEXT: lw t5, 28(a5)
-; QCI-PUSH-POP-NEXT: lw t6, 32(a5)
-; QCI-PUSH-POP-NEXT: lw s2, 36(a5)
-; QCI-PUSH-POP-NEXT: lw s3, 40(a5)
-; QCI-PUSH-POP-NEXT: lw s4, 44(a5)
-; QCI-PUSH-POP-NEXT: lw s5, 48(a5)
-; QCI-PUSH-POP-NEXT: lw s6, 52(a5)
-; QCI-PUSH-POP-NEXT: lw s7, 56(a5)
-; QCI-PUSH-POP-NEXT: lw s8, 60(a5)
-; QCI-PUSH-POP-NEXT: lw s9, 64(a5)
-; QCI-PUSH-POP-NEXT: lw s10, 68(a5)
-; QCI-PUSH-POP-NEXT: lw s11, 72(a5)
-; QCI-PUSH-POP-NEXT: lw ra, 76(a5)
-; QCI-PUSH-POP-NEXT: lw s1, 80(a5)
-; QCI-PUSH-POP-NEXT: lw t3, 84(a5)
-; QCI-PUSH-POP-NEXT: lw t2, 88(a5)
-; QCI-PUSH-POP-NEXT: lw t1, 92(a5)
-; QCI-PUSH-POP-NEXT: lw a7, 112(a5)
-; QCI-PUSH-POP-NEXT: lw s0, 116(a5)
-; QCI-PUSH-POP-NEXT: lw a3, 120(a5)
-; QCI-PUSH-POP-NEXT: lw a0, 124(a5)
-; QCI-PUSH-POP-NEXT: lw a6, 96(a5)
-; QCI-PUSH-POP-NEXT: lw a4, 100(a5)
-; QCI-PUSH-POP-NEXT: lw a2, 104(a5)
-; QCI-PUSH-POP-NEXT: lw a1, 108(a5)
-; QCI-PUSH-POP-NEXT: sw a0, 124(a5)
-; QCI-PUSH-POP-NEXT: sw a3, 120(a5)
-; QCI-PUSH-POP-NEXT: sw s0, 116(a5)
-; QCI-PUSH-POP-NEXT: sw a7, 112(a5)
-; QCI-PUSH-POP-NEXT: sw a1, 108(a5)
-; QCI-PUSH-POP-NEXT: sw a2, 104(a5)
-; QCI-PUSH-POP-NEXT: sw a4, 100(a5)
-; QCI-PUSH-POP-NEXT: sw a6, 96(a5)
-; QCI-PUSH-POP-NEXT: sw t1, 92(a5)
-; QCI-PUSH-POP-NEXT: sw t2, 88(a5)
-; QCI-PUSH-POP-NEXT: sw t3, 84(a5)
-; QCI-PUSH-POP-NEXT: sw s1, 80(a5)
-; QCI-PUSH-POP-NEXT: sw ra, 76(a5)
-; QCI-PUSH-POP-NEXT: sw s11, 72(a5)
-; QCI-PUSH-POP-NEXT: sw s10, 68(a5)
-; QCI-PUSH-POP-NEXT: sw s9, 64(a5)
-; QCI-PUSH-POP-NEXT: sw s8, 60(a5)
-; QCI-PUSH-POP-NEXT: sw s7, 56(a5)
-; QCI-PUSH-POP-NEXT: sw s6, 52(a5)
-; QCI-PUSH-POP-NEXT: sw s5, 48(a5)
-; QCI-PUSH-POP-NEXT: sw s4, 44(a5)
-; QCI-PUSH-POP-NEXT: sw s3, 40(a5)
-; QCI-PUSH-POP-NEXT: sw s2, 36(a5)
-; QCI-PUSH-POP-NEXT: sw t6, 32(a5)
-; QCI-PUSH-POP-NEXT: sw t5, 28(a5)
-; QCI-PUSH-POP-NEXT: sw t4, 24(a5)
-; QCI-PUSH-POP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 20(a5)
-; QCI-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 16(a5)
-; QCI-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+12)(t0)
-; QCI-PUSH-POP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+8)(t0)
-; QCI-PUSH-POP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+4)(t0)
-; QCI-PUSH-POP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var)(t0)
+; QCI-PUSH-POP-NEXT: lui a0, %hi(var)
+; QCI-PUSH-POP-NEXT: addi a0, a0, %lo(var)
+; QCI-PUSH-POP-NEXT: lw a1, 0(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; QCI-PUSH-POP-NEXT: lw a1, 4(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; QCI-PUSH-POP-NEXT: lw a1, 8(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; QCI-PUSH-POP-NEXT: lw a1, 12(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; QCI-PUSH-POP-NEXT: lw a1, 16(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; QCI-PUSH-POP-NEXT: lw t3, 20(a0)
+; QCI-PUSH-POP-NEXT: lw t4, 24(a0)
+; QCI-PUSH-POP-NEXT: lw t5, 28(a0)
+; QCI-PUSH-POP-NEXT: lw t6, 32(a0)
+; QCI-PUSH-POP-NEXT: lw s2, 36(a0)
+; QCI-PUSH-POP-NEXT: lw s3, 40(a0)
+; QCI-PUSH-POP-NEXT: lw s4, 44(a0)
+; QCI-PUSH-POP-NEXT: lw s5, 48(a0)
+; QCI-PUSH-POP-NEXT: lw s6, 52(a0)
+; QCI-PUSH-POP-NEXT: lw s7, 56(a0)
+; QCI-PUSH-POP-NEXT: lw s8, 60(a0)
+; QCI-PUSH-POP-NEXT: lw s9, 64(a0)
+; QCI-PUSH-POP-NEXT: lw s10, 68(a0)
+; QCI-PUSH-POP-NEXT: lw s11, 72(a0)
+; QCI-PUSH-POP-NEXT: lw ra, 76(a0)
+; QCI-PUSH-POP-NEXT: lw t2, 80(a0)
+; QCI-PUSH-POP-NEXT: lw s0, 84(a0)
+; QCI-PUSH-POP-NEXT: lw s1, 88(a0)
+; QCI-PUSH-POP-NEXT: lw t1, 92(a0)
+; QCI-PUSH-POP-NEXT: lw t0, 112(a0)
+; QCI-PUSH-POP-NEXT: lw a5, 116(a0)
+; QCI-PUSH-POP-NEXT: lw a3, 120(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 124(a0)
+; QCI-PUSH-POP-NEXT: lw a7, 96(a0)
+; QCI-PUSH-POP-NEXT: lw a6, 100(a0)
+; QCI-PUSH-POP-NEXT: lw a4, 104(a0)
+; QCI-PUSH-POP-NEXT: lw a2, 108(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 124(a0)
+; QCI-PUSH-POP-NEXT: sw a3, 120(a0)
+; QCI-PUSH-POP-NEXT: sw a5, 116(a0)
+; QCI-PUSH-POP-NEXT: sw t0, 112(a0)
+; QCI-PUSH-POP-NEXT: sw a2, 108(a0)
+; QCI-PUSH-POP-NEXT: sw a4, 104(a0)
+; QCI-PUSH-POP-NEXT: sw a6, 100(a0)
+; QCI-PUSH-POP-NEXT: sw a7, 96(a0)
+; QCI-PUSH-POP-NEXT: sw t1, 92(a0)
+; QCI-PUSH-POP-NEXT: sw s1, 88(a0)
+; QCI-PUSH-POP-NEXT: sw s0, 84(a0)
+; QCI-PUSH-POP-NEXT: sw t2, 80(a0)
+; QCI-PUSH-POP-NEXT: sw ra, 76(a0)
+; QCI-PUSH-POP-NEXT: sw s11, 72(a0)
+; QCI-PUSH-POP-NEXT: sw s10, 68(a0)
+; QCI-PUSH-POP-NEXT: sw s9, 64(a0)
+; QCI-PUSH-POP-NEXT: sw s8, 60(a0)
+; QCI-PUSH-POP-NEXT: sw s7, 56(a0)
+; QCI-PUSH-POP-NEXT: sw s6, 52(a0)
+; QCI-PUSH-POP-NEXT: sw s5, 48(a0)
+; QCI-PUSH-POP-NEXT: sw s4, 44(a0)
+; QCI-PUSH-POP-NEXT: sw s3, 40(a0)
+; QCI-PUSH-POP-NEXT: sw s2, 36(a0)
+; QCI-PUSH-POP-NEXT: sw t6, 32(a0)
+; QCI-PUSH-POP-NEXT: sw t5, 28(a0)
+; QCI-PUSH-POP-NEXT: sw t4, 24(a0)
+; QCI-PUSH-POP-NEXT: sw t3, 20(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; QCI-PUSH-POP-NEXT: sw a1, 16(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; QCI-PUSH-POP-NEXT: sw a1, 12(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; QCI-PUSH-POP-NEXT: sw a1, 8(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; QCI-PUSH-POP-NEXT: sw a1, 4(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; QCI-PUSH-POP-NEXT: sw a1, 0(a0)
; QCI-PUSH-POP-NEXT: cm.pop {ra, s0-s11}, 96
; QCI-PUSH-POP-NEXT: .cfi_restore s1
; QCI-PUSH-POP-NEXT: .cfi_restore s2
@@ -1451,84 +1445,82 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_offset s9, -140
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_offset s10, -144
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_offset s11, -148
-; QCI-QCCMP-PUSH-POP-NEXT: lui t0, %hi(var)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+4)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+8)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+12)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: addi a5, t0, %lo(var)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 20(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw t4, 24(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t5, 28(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t6, 32(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 36(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 40(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 44(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 48(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 52(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 56(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 60(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 64(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 68(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 72(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw ra, 76(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 80(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t3, 84(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t2, 88(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t1, 92(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a7, 112(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s0, 116(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a3, 120(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 124(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a6, 96(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a4, 100(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a2, 104(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 108(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 124(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a3, 120(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s0, 116(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a7, 112(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 108(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a2, 104(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a4, 100(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a6, 96(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t1, 92(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t2, 88(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t3, 84(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 80(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw ra, 76(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 72(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 68(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 64(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 60(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 56(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 52(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 48(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 44(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 40(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 36(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t6, 32(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t5, 28(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t4, 24(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 20(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+12)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+8)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+4)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var)(t0)
+; QCI-QCCMP-PUSH-POP-NEXT: lui a0, %hi(var)
+; QCI-QCCMP-PUSH-POP-NEXT: addi a0, a0, %lo(var)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 0(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 4(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 8(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 12(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 16(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-NEXT: lw t3, 20(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t4, 24(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t5, 28(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t6, 32(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 36(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 40(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 44(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 48(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 52(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 56(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 60(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 64(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 68(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 72(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw ra, 76(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t2, 80(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s0, 84(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 88(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t1, 92(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a5, 116(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a3, 120(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 124(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a7, 96(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a6, 100(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a4, 104(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a2, 108(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 124(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a3, 120(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a5, 116(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a2, 108(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a4, 104(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a6, 100(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a7, 96(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t1, 92(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 88(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s0, 84(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t2, 80(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw ra, 76(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 72(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 68(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 64(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 60(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 56(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 52(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 48(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 44(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 40(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 36(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t6, 32(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t5, 28(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t4, 24(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t3, 20(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 16(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 12(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 8(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 4(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 0(a0)
; QCI-QCCMP-PUSH-POP-NEXT: qc.cm.pop {ra, s0-s11}, 96
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_restore s1
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_restore s2
@@ -1579,86 +1571,84 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_offset s10, -144
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_offset s11, -148
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa s0, 0
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lui t1, %hi(var)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -164(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+4)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -168(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+8)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -172(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+12)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -176(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: addi a5, t1, %lo(var)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 16(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -180(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 20(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -184(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 24(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -188(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t5, 28(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t6, 32(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 36(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 40(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 44(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 48(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s6, 52(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 56(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 60(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 64(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 68(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 72(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw ra, 76(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t4, 80(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t3, 84(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t2, 88(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s1, 92(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t0, 112(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a4, 116(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a3, 120(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 124(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a7, 96(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a6, 100(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a2, 104(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 108(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 124(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a3, 120(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a4, 116(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t0, 112(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 108(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a2, 104(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a6, 100(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a7, 96(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s1, 92(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t2, 88(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t3, 84(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t4, 80(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw ra, 76(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 72(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 68(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 64(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 60(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 56(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s6, 52(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 48(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 44(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 40(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 36(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t6, 32(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t5, 28(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -188(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 24(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -184(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 20(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -180(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 16(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -176(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+12)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -172(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+8)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -168(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+4)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -164(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var)(t1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lui a0, %hi(var)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: addi a0, a0, %lo(var)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 0(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -164(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 4(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -168(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 8(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -172(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 12(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -176(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 16(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -180(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 20(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -184(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t4, 24(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t5, 28(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t6, 32(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 36(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 40(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 44(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 48(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s6, 52(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 56(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 60(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 64(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 68(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 72(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw ra, 76(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s1, 80(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t3, 84(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t2, 88(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t1, 92(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a6, 116(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a4, 120(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 124(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a7, 96(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a5, 100(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a3, 104(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a2, 108(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 124(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a4, 120(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a6, 116(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a2, 108(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a3, 104(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a5, 100(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a7, 96(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t1, 92(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t2, 88(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t3, 84(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s1, 80(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw ra, 76(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 72(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 68(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 64(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 60(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 56(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s6, 52(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 48(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 44(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 40(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 36(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t6, 32(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t5, 28(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t4, 24(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -184(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 20(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -180(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 16(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -176(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 12(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -172(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 8(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -168(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 4(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -164(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 0(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa sp, 192
; QCI-QCCMP-PUSH-POP-FP-NEXT: qc.cm.pop {ra, s0-s11}, 96
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_restore s1
@@ -1701,19 +1691,19 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-NEXT: .cfi_offset t4, -72
; QCI-NEXT: .cfi_offset t5, -76
; QCI-NEXT: .cfi_offset t6, -80
-; QCI-NEXT: addi sp, sp, -80
-; QCI-NEXT: .cfi_def_cfa_offset 176
-; QCI-NEXT: sw s1, 76(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s2, 72(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s3, 68(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s4, 64(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s5, 60(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s6, 56(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s7, 52(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s8, 48(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s9, 44(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s10, 40(sp) # 4-byte Folded Spill
-; QCI-NEXT: sw s11, 36(sp) # 4-byte Folded Spill
+; QCI-NEXT: addi sp, sp, -64
+; QCI-NEXT: .cfi_def_cfa_offset 160
+; QCI-NEXT: sw s1, 60(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s2, 56(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s3, 52(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s4, 48(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s5, 44(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s6, 40(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s7, 36(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s8, 32(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s9, 28(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s10, 24(sp) # 4-byte Folded Spill
+; QCI-NEXT: sw s11, 20(sp) # 4-byte Folded Spill
; QCI-NEXT: .cfi_offset s1, -100
; QCI-NEXT: .cfi_offset s2, -104
; QCI-NEXT: .cfi_offset s3, -108
@@ -1725,95 +1715,93 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-NEXT: .cfi_offset s9, -132
; QCI-NEXT: .cfi_offset s10, -136
; QCI-NEXT: .cfi_offset s11, -140
-; QCI-NEXT: lui t0, %hi(var)
-; QCI-NEXT: lw a0, %lo(var)(t0)
-; QCI-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+4)(t0)
-; QCI-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+8)(t0)
-; QCI-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+12)(t0)
-; QCI-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-NEXT: addi a5, t0, %lo(var)
-; QCI-NEXT: lw a0, 16(a5)
-; QCI-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 20(a5)
-; QCI-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw t4, 24(a5)
-; QCI-NEXT: lw t5, 28(a5)
-; QCI-NEXT: lw t6, 32(a5)
-; QCI-NEXT: lw s2, 36(a5)
-; QCI-NEXT: lw s3, 40(a5)
-; QCI-NEXT: lw s4, 44(a5)
-; QCI-NEXT: lw s5, 48(a5)
-; QCI-NEXT: lw s6, 52(a5)
-; QCI-NEXT: lw s7, 56(a5)
-; QCI-NEXT: lw s8, 60(a5)
-; QCI-NEXT: lw s9, 64(a5)
-; QCI-NEXT: lw s10, 68(a5)
-; QCI-NEXT: lw s11, 72(a5)
-; QCI-NEXT: lw ra, 76(a5)
-; QCI-NEXT: lw s1, 80(a5)
-; QCI-NEXT: lw t3, 84(a5)
-; QCI-NEXT: lw t2, 88(a5)
-; QCI-NEXT: lw t1, 92(a5)
-; QCI-NEXT: lw a7, 112(a5)
-; QCI-NEXT: lw s0, 116(a5)
-; QCI-NEXT: lw a3, 120(a5)
-; QCI-NEXT: lw a0, 124(a5)
-; QCI-NEXT: lw a6, 96(a5)
-; QCI-NEXT: lw a4, 100(a5)
-; QCI-NEXT: lw a2, 104(a5)
-; QCI-NEXT: lw a1, 108(a5)
-; QCI-NEXT: sw a0, 124(a5)
-; QCI-NEXT: sw a3, 120(a5)
-; QCI-NEXT: sw s0, 116(a5)
-; QCI-NEXT: sw a7, 112(a5)
-; QCI-NEXT: sw a1, 108(a5)
-; QCI-NEXT: sw a2, 104(a5)
-; QCI-NEXT: sw a4, 100(a5)
-; QCI-NEXT: sw a6, 96(a5)
-; QCI-NEXT: sw t1, 92(a5)
-; QCI-NEXT: sw t2, 88(a5)
-; QCI-NEXT: sw t3, 84(a5)
-; QCI-NEXT: sw s1, 80(a5)
-; QCI-NEXT: sw ra, 76(a5)
-; QCI-NEXT: sw s11, 72(a5)
-; QCI-NEXT: sw s10, 68(a5)
-; QCI-NEXT: sw s9, 64(a5)
-; QCI-NEXT: sw s8, 60(a5)
-; QCI-NEXT: sw s7, 56(a5)
-; QCI-NEXT: sw s6, 52(a5)
-; QCI-NEXT: sw s5, 48(a5)
-; QCI-NEXT: sw s4, 44(a5)
-; QCI-NEXT: sw s3, 40(a5)
-; QCI-NEXT: sw s2, 36(a5)
-; QCI-NEXT: sw t6, 32(a5)
-; QCI-NEXT: sw t5, 28(a5)
-; QCI-NEXT: sw t4, 24(a5)
-; QCI-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 20(a5)
-; QCI-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 16(a5)
-; QCI-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+12)(t0)
-; QCI-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+8)(t0)
-; QCI-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+4)(t0)
-; QCI-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var)(t0)
-; QCI-NEXT: lw s1, 76(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s2, 72(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s3, 68(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s4, 64(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s5, 60(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s6, 56(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s7, 52(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s8, 48(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s9, 44(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s10, 40(sp) # 4-byte Folded Reload
-; QCI-NEXT: lw s11, 36(sp) # 4-byte Folded Reload
+; QCI-NEXT: lui a0, %hi(var)
+; QCI-NEXT: addi a0, a0, %lo(var)
+; QCI-NEXT: lw a1, 0(a0)
+; QCI-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; QCI-NEXT: lw a1, 4(a0)
+; QCI-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; QCI-NEXT: lw a1, 8(a0)
+; QCI-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; QCI-NEXT: lw a1, 12(a0)
+; QCI-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; QCI-NEXT: lw a1, 16(a0)
+; QCI-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; QCI-NEXT: lw t3, 20(a0)
+; QCI-NEXT: lw t4, 24(a0)
+; QCI-NEXT: lw t5, 28(a0)
+; QCI-NEXT: lw t6, 32(a0)
+; QCI-NEXT: lw s2, 36(a0)
+; QCI-NEXT: lw s3, 40(a0)
+; QCI-NEXT: lw s4, 44(a0)
+; QCI-NEXT: lw s5, 48(a0)
+; QCI-NEXT: lw s6, 52(a0)
+; QCI-NEXT: lw s7, 56(a0)
+; QCI-NEXT: lw s8, 60(a0)
+; QCI-NEXT: lw s9, 64(a0)
+; QCI-NEXT: lw s10, 68(a0)
+; QCI-NEXT: lw s11, 72(a0)
+; QCI-NEXT: lw ra, 76(a0)
+; QCI-NEXT: lw t2, 80(a0)
+; QCI-NEXT: lw s0, 84(a0)
+; QCI-NEXT: lw s1, 88(a0)
+; QCI-NEXT: lw t1, 92(a0)
+; QCI-NEXT: lw t0, 112(a0)
+; QCI-NEXT: lw a5, 116(a0)
+; QCI-NEXT: lw a3, 120(a0)
+; QCI-NEXT: lw a1, 124(a0)
+; QCI-NEXT: lw a7, 96(a0)
+; QCI-NEXT: lw a6, 100(a0)
+; QCI-NEXT: lw a4, 104(a0)
+; QCI-NEXT: lw a2, 108(a0)
+; QCI-NEXT: sw a1, 124(a0)
+; QCI-NEXT: sw a3, 120(a0)
+; QCI-NEXT: sw a5, 116(a0)
+; QCI-NEXT: sw t0, 112(a0)
+; QCI-NEXT: sw a2, 108(a0)
+; QCI-NEXT: sw a4, 104(a0)
+; QCI-NEXT: sw a6, 100(a0)
+; QCI-NEXT: sw a7, 96(a0)
+; QCI-NEXT: sw t1, 92(a0)
+; QCI-NEXT: sw s1, 88(a0)
+; QCI-NEXT: sw s0, 84(a0)
+; QCI-NEXT: sw t2, 80(a0)
+; QCI-NEXT: sw ra, 76(a0)
+; QCI-NEXT: sw s11, 72(a0)
+; QCI-NEXT: sw s10, 68(a0)
+; QCI-NEXT: sw s9, 64(a0)
+; QCI-NEXT: sw s8, 60(a0)
+; QCI-NEXT: sw s7, 56(a0)
+; QCI-NEXT: sw s6, 52(a0)
+; QCI-NEXT: sw s5, 48(a0)
+; QCI-NEXT: sw s4, 44(a0)
+; QCI-NEXT: sw s3, 40(a0)
+; QCI-NEXT: sw s2, 36(a0)
+; QCI-NEXT: sw t6, 32(a0)
+; QCI-NEXT: sw t5, 28(a0)
+; QCI-NEXT: sw t4, 24(a0)
+; QCI-NEXT: sw t3, 20(a0)
+; QCI-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; QCI-NEXT: sw a1, 16(a0)
+; QCI-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; QCI-NEXT: sw a1, 12(a0)
+; QCI-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; QCI-NEXT: sw a1, 8(a0)
+; QCI-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; QCI-NEXT: sw a1, 4(a0)
+; QCI-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; QCI-NEXT: sw a1, 0(a0)
+; QCI-NEXT: lw s1, 60(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s2, 56(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s3, 52(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s4, 48(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s5, 44(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s6, 40(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s7, 36(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s8, 32(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s9, 28(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s10, 24(sp) # 4-byte Folded Reload
+; QCI-NEXT: lw s11, 20(sp) # 4-byte Folded Reload
; QCI-NEXT: .cfi_restore s1
; QCI-NEXT: .cfi_restore s2
; QCI-NEXT: .cfi_restore s3
@@ -1825,7 +1813,7 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-NEXT: .cfi_restore s9
; QCI-NEXT: .cfi_restore s10
; QCI-NEXT: .cfi_restore s11
-; QCI-NEXT: addi sp, sp, 80
+; QCI-NEXT: addi sp, sp, 64
; QCI-NEXT: .cfi_def_cfa_offset 96
; QCI-NEXT: qc.c.mileaveret
;
@@ -1875,86 +1863,84 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: .cfi_offset s10, -136
; QCI-FP-NEXT: .cfi_offset s11, -140
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
-; QCI-FP-NEXT: lui t1, %hi(var)
-; QCI-FP-NEXT: lw a0, %lo(var)(t1)
-; QCI-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+4)(t1)
-; QCI-FP-NEXT: sw a0, -148(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+8)(t1)
-; QCI-FP-NEXT: sw a0, -152(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+12)(t1)
-; QCI-FP-NEXT: sw a0, -156(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: addi a5, t1, %lo(var)
-; QCI-FP-NEXT: lw a0, 16(a5)
-; QCI-FP-NEXT: sw a0, -160(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, 20(a5)
-; QCI-FP-NEXT: sw a0, -164(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, 24(a5)
-; QCI-FP-NEXT: sw a0, -168(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw t5, 28(a5)
-; QCI-FP-NEXT: lw t6, 32(a5)
-; QCI-FP-NEXT: lw s2, 36(a5)
-; QCI-FP-NEXT: lw s3, 40(a5)
-; QCI-FP-NEXT: lw s4, 44(a5)
-; QCI-FP-NEXT: lw s5, 48(a5)
-; QCI-FP-NEXT: lw s6, 52(a5)
-; QCI-FP-NEXT: lw s7, 56(a5)
-; QCI-FP-NEXT: lw s8, 60(a5)
-; QCI-FP-NEXT: lw s9, 64(a5)
-; QCI-FP-NEXT: lw s10, 68(a5)
-; QCI-FP-NEXT: lw s11, 72(a5)
-; QCI-FP-NEXT: lw ra, 76(a5)
-; QCI-FP-NEXT: lw t4, 80(a5)
-; QCI-FP-NEXT: lw t3, 84(a5)
-; QCI-FP-NEXT: lw t2, 88(a5)
-; QCI-FP-NEXT: lw s1, 92(a5)
-; QCI-FP-NEXT: lw t0, 112(a5)
-; QCI-FP-NEXT: lw a4, 116(a5)
-; QCI-FP-NEXT: lw a3, 120(a5)
-; QCI-FP-NEXT: lw a0, 124(a5)
-; QCI-FP-NEXT: lw a7, 96(a5)
-; QCI-FP-NEXT: lw a6, 100(a5)
-; QCI-FP-NEXT: lw a2, 104(a5)
-; QCI-FP-NEXT: lw a1, 108(a5)
-; QCI-FP-NEXT: sw a0, 124(a5)
-; QCI-FP-NEXT: sw a3, 120(a5)
-; QCI-FP-NEXT: sw a4, 116(a5)
-; QCI-FP-NEXT: sw t0, 112(a5)
-; QCI-FP-NEXT: sw a1, 108(a5)
-; QCI-FP-NEXT: sw a2, 104(a5)
-; QCI-FP-NEXT: sw a6, 100(a5)
-; QCI-FP-NEXT: sw a7, 96(a5)
-; QCI-FP-NEXT: sw s1, 92(a5)
-; QCI-FP-NEXT: sw t2, 88(a5)
-; QCI-FP-NEXT: sw t3, 84(a5)
-; QCI-FP-NEXT: sw t4, 80(a5)
-; QCI-FP-NEXT: sw ra, 76(a5)
-; QCI-FP-NEXT: sw s11, 72(a5)
-; QCI-FP-NEXT: sw s10, 68(a5)
-; QCI-FP-NEXT: sw s9, 64(a5)
-; QCI-FP-NEXT: sw s8, 60(a5)
-; QCI-FP-NEXT: sw s7, 56(a5)
-; QCI-FP-NEXT: sw s6, 52(a5)
-; QCI-FP-NEXT: sw s5, 48(a5)
-; QCI-FP-NEXT: sw s4, 44(a5)
-; QCI-FP-NEXT: sw s3, 40(a5)
-; QCI-FP-NEXT: sw s2, 36(a5)
-; QCI-FP-NEXT: sw t6, 32(a5)
-; QCI-FP-NEXT: sw t5, 28(a5)
-; QCI-FP-NEXT: lw a0, -168(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, 24(a5)
-; QCI-FP-NEXT: lw a0, -164(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, 20(a5)
-; QCI-FP-NEXT: lw a0, -160(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, 16(a5)
-; QCI-FP-NEXT: lw a0, -156(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+12)(t1)
-; QCI-FP-NEXT: lw a0, -152(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+8)(t1)
-; QCI-FP-NEXT: lw a0, -148(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+4)(t1)
-; QCI-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var)(t1)
+; QCI-FP-NEXT: lui a0, %hi(var)
+; QCI-FP-NEXT: addi a0, a0, %lo(var)
+; QCI-FP-NEXT: lw a1, 0(a0)
+; QCI-FP-NEXT: sw a1, -144(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw a1, 4(a0)
+; QCI-FP-NEXT: sw a1, -148(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw a1, 8(a0)
+; QCI-FP-NEXT: sw a1, -152(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw a1, 12(a0)
+; QCI-FP-NEXT: sw a1, -156(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw a1, 16(a0)
+; QCI-FP-NEXT: sw a1, -160(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw a1, 20(a0)
+; QCI-FP-NEXT: sw a1, -164(s0) # 4-byte Folded Spill
+; QCI-FP-NEXT: lw t4, 24(a0)
+; QCI-FP-NEXT: lw t5, 28(a0)
+; QCI-FP-NEXT: lw t6, 32(a0)
+; QCI-FP-NEXT: lw s2, 36(a0)
+; QCI-FP-NEXT: lw s3, 40(a0)
+; QCI-FP-NEXT: lw s4, 44(a0)
+; QCI-FP-NEXT: lw s5, 48(a0)
+; QCI-FP-NEXT: lw s6, 52(a0)
+; QCI-FP-NEXT: lw s7, 56(a0)
+; QCI-FP-NEXT: lw s8, 60(a0)
+; QCI-FP-NEXT: lw s9, 64(a0)
+; QCI-FP-NEXT: lw s10, 68(a0)
+; QCI-FP-NEXT: lw s11, 72(a0)
+; QCI-FP-NEXT: lw ra, 76(a0)
+; QCI-FP-NEXT: lw s1, 80(a0)
+; QCI-FP-NEXT: lw t3, 84(a0)
+; QCI-FP-NEXT: lw t2, 88(a0)
+; QCI-FP-NEXT: lw t1, 92(a0)
+; QCI-FP-NEXT: lw t0, 112(a0)
+; QCI-FP-NEXT: lw a6, 116(a0)
+; QCI-FP-NEXT: lw a4, 120(a0)
+; QCI-FP-NEXT: lw a1, 124(a0)
+; QCI-FP-NEXT: lw a7, 96(a0)
+; QCI-FP-NEXT: lw a5, 100(a0)
+; QCI-FP-NEXT: lw a3, 104(a0)
+; QCI-FP-NEXT: lw a2, 108(a0)
+; QCI-FP-NEXT: sw a1, 124(a0)
+; QCI-FP-NEXT: sw a4, 120(a0)
+; QCI-FP-NEXT: sw a6, 116(a0)
+; QCI-FP-NEXT: sw t0, 112(a0)
+; QCI-FP-NEXT: sw a2, 108(a0)
+; QCI-FP-NEXT: sw a3, 104(a0)
+; QCI-FP-NEXT: sw a5, 100(a0)
+; QCI-FP-NEXT: sw a7, 96(a0)
+; QCI-FP-NEXT: sw t1, 92(a0)
+; QCI-FP-NEXT: sw t2, 88(a0)
+; QCI-FP-NEXT: sw t3, 84(a0)
+; QCI-FP-NEXT: sw s1, 80(a0)
+; QCI-FP-NEXT: sw ra, 76(a0)
+; QCI-FP-NEXT: sw s11, 72(a0)
+; QCI-FP-NEXT: sw s10, 68(a0)
+; QCI-FP-NEXT: sw s9, 64(a0)
+; QCI-FP-NEXT: sw s8, 60(a0)
+; QCI-FP-NEXT: sw s7, 56(a0)
+; QCI-FP-NEXT: sw s6, 52(a0)
+; QCI-FP-NEXT: sw s5, 48(a0)
+; QCI-FP-NEXT: sw s4, 44(a0)
+; QCI-FP-NEXT: sw s3, 40(a0)
+; QCI-FP-NEXT: sw s2, 36(a0)
+; QCI-FP-NEXT: sw t6, 32(a0)
+; QCI-FP-NEXT: sw t5, 28(a0)
+; QCI-FP-NEXT: sw t4, 24(a0)
+; QCI-FP-NEXT: lw a1, -164(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 20(a0)
+; QCI-FP-NEXT: lw a1, -160(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 16(a0)
+; QCI-FP-NEXT: lw a1, -156(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 12(a0)
+; QCI-FP-NEXT: lw a1, -152(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 8(a0)
+; QCI-FP-NEXT: lw a1, -148(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 4(a0)
+; QCI-FP-NEXT: lw a1, -144(s0) # 4-byte Folded Reload
+; QCI-FP-NEXT: sw a1, 0(a0)
; QCI-FP-NEXT: .cfi_def_cfa sp, 176
; QCI-FP-NEXT: lw s1, 76(sp) # 4-byte Folded Reload
; QCI-FP-NEXT: lw s2, 72(sp) # 4-byte Folded Reload
@@ -2016,84 +2002,82 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-PUSH-POP-NEXT: .cfi_offset s9, -108
; QCI-PUSH-POP-NEXT: .cfi_offset s10, -104
; QCI-PUSH-POP-NEXT: .cfi_offset s11, -100
-; QCI-PUSH-POP-NEXT: lui t0, %hi(var)
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var)(t0)
-; QCI-PUSH-POP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+4)(t0)
-; QCI-PUSH-POP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+8)(t0)
-; QCI-PUSH-POP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+12)(t0)
-; QCI-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: addi a5, t0, %lo(var)
-; QCI-PUSH-POP-NEXT: lw a0, 16(a5)
-; QCI-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 20(a5)
-; QCI-PUSH-POP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw t4, 24(a5)
-; QCI-PUSH-POP-NEXT: lw t5, 28(a5)
-; QCI-PUSH-POP-NEXT: lw t6, 32(a5)
-; QCI-PUSH-POP-NEXT: lw s2, 36(a5)
-; QCI-PUSH-POP-NEXT: lw s3, 40(a5)
-; QCI-PUSH-POP-NEXT: lw s4, 44(a5)
-; QCI-PUSH-POP-NEXT: lw s5, 48(a5)
-; QCI-PUSH-POP-NEXT: lw s6, 52(a5)
-; QCI-PUSH-POP-NEXT: lw s7, 56(a5)
-; QCI-PUSH-POP-NEXT: lw s8, 60(a5)
-; QCI-PUSH-POP-NEXT: lw s9, 64(a5)
-; QCI-PUSH-POP-NEXT: lw s10, 68(a5)
-; QCI-PUSH-POP-NEXT: lw s11, 72(a5)
-; QCI-PUSH-POP-NEXT: lw ra, 76(a5)
-; QCI-PUSH-POP-NEXT: lw s1, 80(a5)
-; QCI-PUSH-POP-NEXT: lw t3, 84(a5)
-; QCI-PUSH-POP-NEXT: lw t2, 88(a5)
-; QCI-PUSH-POP-NEXT: lw t1, 92(a5)
-; QCI-PUSH-POP-NEXT: lw a7, 112(a5)
-; QCI-PUSH-POP-NEXT: lw s0, 116(a5)
-; QCI-PUSH-POP-NEXT: lw a3, 120(a5)
-; QCI-PUSH-POP-NEXT: lw a0, 124(a5)
-; QCI-PUSH-POP-NEXT: lw a6, 96(a5)
-; QCI-PUSH-POP-NEXT: lw a4, 100(a5)
-; QCI-PUSH-POP-NEXT: lw a2, 104(a5)
-; QCI-PUSH-POP-NEXT: lw a1, 108(a5)
-; QCI-PUSH-POP-NEXT: sw a0, 124(a5)
-; QCI-PUSH-POP-NEXT: sw a3, 120(a5)
-; QCI-PUSH-POP-NEXT: sw s0, 116(a5)
-; QCI-PUSH-POP-NEXT: sw a7, 112(a5)
-; QCI-PUSH-POP-NEXT: sw a1, 108(a5)
-; QCI-PUSH-POP-NEXT: sw a2, 104(a5)
-; QCI-PUSH-POP-NEXT: sw a4, 100(a5)
-; QCI-PUSH-POP-NEXT: sw a6, 96(a5)
-; QCI-PUSH-POP-NEXT: sw t1, 92(a5)
-; QCI-PUSH-POP-NEXT: sw t2, 88(a5)
-; QCI-PUSH-POP-NEXT: sw t3, 84(a5)
-; QCI-PUSH-POP-NEXT: sw s1, 80(a5)
-; QCI-PUSH-POP-NEXT: sw ra, 76(a5)
-; QCI-PUSH-POP-NEXT: sw s11, 72(a5)
-; QCI-PUSH-POP-NEXT: sw s10, 68(a5)
-; QCI-PUSH-POP-NEXT: sw s9, 64(a5)
-; QCI-PUSH-POP-NEXT: sw s8, 60(a5)
-; QCI-PUSH-POP-NEXT: sw s7, 56(a5)
-; QCI-PUSH-POP-NEXT: sw s6, 52(a5)
-; QCI-PUSH-POP-NEXT: sw s5, 48(a5)
-; QCI-PUSH-POP-NEXT: sw s4, 44(a5)
-; QCI-PUSH-POP-NEXT: sw s3, 40(a5)
-; QCI-PUSH-POP-NEXT: sw s2, 36(a5)
-; QCI-PUSH-POP-NEXT: sw t6, 32(a5)
-; QCI-PUSH-POP-NEXT: sw t5, 28(a5)
-; QCI-PUSH-POP-NEXT: sw t4, 24(a5)
-; QCI-PUSH-POP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 20(a5)
-; QCI-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 16(a5)
-; QCI-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+12)(t0)
-; QCI-PUSH-POP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+8)(t0)
-; QCI-PUSH-POP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+4)(t0)
-; QCI-PUSH-POP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var)(t0)
+; QCI-PUSH-POP-NEXT: lui a0, %hi(var)
+; QCI-PUSH-POP-NEXT: addi a0, a0, %lo(var)
+; QCI-PUSH-POP-NEXT: lw a1, 0(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; QCI-PUSH-POP-NEXT: lw a1, 4(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; QCI-PUSH-POP-NEXT: lw a1, 8(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; QCI-PUSH-POP-NEXT: lw a1, 12(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; QCI-PUSH-POP-NEXT: lw a1, 16(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; QCI-PUSH-POP-NEXT: lw t3, 20(a0)
+; QCI-PUSH-POP-NEXT: lw t4, 24(a0)
+; QCI-PUSH-POP-NEXT: lw t5, 28(a0)
+; QCI-PUSH-POP-NEXT: lw t6, 32(a0)
+; QCI-PUSH-POP-NEXT: lw s2, 36(a0)
+; QCI-PUSH-POP-NEXT: lw s3, 40(a0)
+; QCI-PUSH-POP-NEXT: lw s4, 44(a0)
+; QCI-PUSH-POP-NEXT: lw s5, 48(a0)
+; QCI-PUSH-POP-NEXT: lw s6, 52(a0)
+; QCI-PUSH-POP-NEXT: lw s7, 56(a0)
+; QCI-PUSH-POP-NEXT: lw s8, 60(a0)
+; QCI-PUSH-POP-NEXT: lw s9, 64(a0)
+; QCI-PUSH-POP-NEXT: lw s10, 68(a0)
+; QCI-PUSH-POP-NEXT: lw s11, 72(a0)
+; QCI-PUSH-POP-NEXT: lw ra, 76(a0)
+; QCI-PUSH-POP-NEXT: lw t2, 80(a0)
+; QCI-PUSH-POP-NEXT: lw s0, 84(a0)
+; QCI-PUSH-POP-NEXT: lw s1, 88(a0)
+; QCI-PUSH-POP-NEXT: lw t1, 92(a0)
+; QCI-PUSH-POP-NEXT: lw t0, 112(a0)
+; QCI-PUSH-POP-NEXT: lw a5, 116(a0)
+; QCI-PUSH-POP-NEXT: lw a3, 120(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 124(a0)
+; QCI-PUSH-POP-NEXT: lw a7, 96(a0)
+; QCI-PUSH-POP-NEXT: lw a6, 100(a0)
+; QCI-PUSH-POP-NEXT: lw a4, 104(a0)
+; QCI-PUSH-POP-NEXT: lw a2, 108(a0)
+; QCI-PUSH-POP-NEXT: sw a1, 124(a0)
+; QCI-PUSH-POP-NEXT: sw a3, 120(a0)
+; QCI-PUSH-POP-NEXT: sw a5, 116(a0)
+; QCI-PUSH-POP-NEXT: sw t0, 112(a0)
+; QCI-PUSH-POP-NEXT: sw a2, 108(a0)
+; QCI-PUSH-POP-NEXT: sw a4, 104(a0)
+; QCI-PUSH-POP-NEXT: sw a6, 100(a0)
+; QCI-PUSH-POP-NEXT: sw a7, 96(a0)
+; QCI-PUSH-POP-NEXT: sw t1, 92(a0)
+; QCI-PUSH-POP-NEXT: sw s1, 88(a0)
+; QCI-PUSH-POP-NEXT: sw s0, 84(a0)
+; QCI-PUSH-POP-NEXT: sw t2, 80(a0)
+; QCI-PUSH-POP-NEXT: sw ra, 76(a0)
+; QCI-PUSH-POP-NEXT: sw s11, 72(a0)
+; QCI-PUSH-POP-NEXT: sw s10, 68(a0)
+; QCI-PUSH-POP-NEXT: sw s9, 64(a0)
+; QCI-PUSH-POP-NEXT: sw s8, 60(a0)
+; QCI-PUSH-POP-NEXT: sw s7, 56(a0)
+; QCI-PUSH-POP-NEXT: sw s6, 52(a0)
+; QCI-PUSH-POP-NEXT: sw s5, 48(a0)
+; QCI-PUSH-POP-NEXT: sw s4, 44(a0)
+; QCI-PUSH-POP-NEXT: sw s3, 40(a0)
+; QCI-PUSH-POP-NEXT: sw s2, 36(a0)
+; QCI-PUSH-POP-NEXT: sw t6, 32(a0)
+; QCI-PUSH-POP-NEXT: sw t5, 28(a0)
+; QCI-PUSH-POP-NEXT: sw t4, 24(a0)
+; QCI-PUSH-POP-NEXT: sw t3, 20(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; QCI-PUSH-POP-NEXT: sw a1, 16(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; QCI-PUSH-POP-NEXT: sw a1, 12(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; QCI-PUSH-POP-NEXT: sw a1, 8(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; QCI-PUSH-POP-NEXT: sw a1, 4(a0)
+; QCI-PUSH-POP-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; QCI-PUSH-POP-NEXT: sw a1, 0(a0)
; QCI-PUSH-POP-NEXT: cm.pop {ra, s0-s11}, 96
; QCI-PUSH-POP-NEXT: .cfi_restore s1
; QCI-PUSH-POP-NEXT: .cfi_restore s2
@@ -2143,84 +2127,82 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_offset s9, -140
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_offset s10, -144
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_offset s11, -148
-; QCI-QCCMP-PUSH-POP-NEXT: lui t0, %hi(var)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+4)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+8)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+12)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: addi a5, t0, %lo(var)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 20(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw t4, 24(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t5, 28(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t6, 32(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 36(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 40(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 44(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 48(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 52(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 56(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 60(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 64(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 68(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 72(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw ra, 76(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 80(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t3, 84(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t2, 88(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t1, 92(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a7, 112(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s0, 116(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a3, 120(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 124(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a6, 96(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a4, 100(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a2, 104(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 108(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 124(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a3, 120(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s0, 116(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a7, 112(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 108(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a2, 104(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a4, 100(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a6, 96(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t1, 92(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t2, 88(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t3, 84(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 80(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw ra, 76(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 72(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 68(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 64(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 60(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 56(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 52(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 48(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 44(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 40(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 36(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t6, 32(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t5, 28(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t4, 24(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 20(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(a5)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+12)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+8)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+4)(t0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var)(t0)
+; QCI-QCCMP-PUSH-POP-NEXT: lui a0, %hi(var)
+; QCI-QCCMP-PUSH-POP-NEXT: addi a0, a0, %lo(var)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 0(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 4(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 8(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 12(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 16(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-NEXT: lw t3, 20(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t4, 24(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t5, 28(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t6, 32(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 36(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 40(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 44(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 48(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 52(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 56(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 60(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 64(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 68(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 72(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw ra, 76(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t2, 80(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s0, 84(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 88(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t1, 92(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a5, 116(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a3, 120(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 124(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a7, 96(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a6, 100(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a4, 104(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a2, 108(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 124(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a3, 120(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a5, 116(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a2, 108(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a4, 104(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a6, 100(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a7, 96(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t1, 92(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 88(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s0, 84(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t2, 80(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw ra, 76(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 72(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 68(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 64(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 60(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 56(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 52(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 48(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 44(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 40(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 36(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t6, 32(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t5, 28(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t4, 24(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t3, 20(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 16(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 12(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 8(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 4(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 0(a0)
; QCI-QCCMP-PUSH-POP-NEXT: qc.cm.pop {ra, s0-s11}, 96
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_restore s1
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_restore s2
@@ -2271,86 +2253,84 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_offset s10, -144
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_offset s11, -148
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa s0, 0
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lui t1, %hi(var)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -164(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+4)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -168(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+8)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -172(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+12)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -176(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: addi a5, t1, %lo(var)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 16(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -180(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 20(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -184(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 24(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -188(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t5, 28(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t6, 32(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 36(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 40(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 44(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 48(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s6, 52(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 56(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 60(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 64(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 68(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 72(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw ra, 76(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t4, 80(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t3, 84(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t2, 88(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s1, 92(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t0, 112(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a4, 116(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a3, 120(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 124(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a7, 96(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a6, 100(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a2, 104(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 108(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 124(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a3, 120(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a4, 116(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t0, 112(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 108(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a2, 104(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a6, 100(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a7, 96(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s1, 92(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t2, 88(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t3, 84(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t4, 80(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw ra, 76(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 72(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 68(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 64(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 60(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 56(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s6, 52(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 48(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 44(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 40(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 36(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t6, 32(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t5, 28(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -188(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 24(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -184(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 20(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -180(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 16(a5)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -176(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+12)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -172(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+8)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -168(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+4)(t1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -164(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var)(t1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lui a0, %hi(var)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: addi a0, a0, %lo(var)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 0(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -164(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 4(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -168(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 8(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -172(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 12(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -176(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 16(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -180(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 20(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -184(s0) # 4-byte Folded Spill
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t4, 24(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t5, 28(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t6, 32(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 36(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 40(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 44(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 48(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s6, 52(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 56(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 60(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 64(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 68(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 72(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw ra, 76(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s1, 80(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t3, 84(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t2, 88(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t1, 92(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a6, 116(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a4, 120(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 124(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a7, 96(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a5, 100(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a3, 104(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a2, 108(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 124(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a4, 120(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a6, 116(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a2, 108(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a3, 104(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a5, 100(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a7, 96(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t1, 92(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t2, 88(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t3, 84(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s1, 80(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw ra, 76(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 72(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 68(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 64(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 60(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 56(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s6, 52(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 48(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 44(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 40(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 36(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t6, 32(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t5, 28(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t4, 24(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -184(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 20(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -180(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 16(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -176(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 12(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -172(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 8(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -168(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 4(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -164(s0) # 4-byte Folded Reload
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 0(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa sp, 192
; QCI-QCCMP-PUSH-POP-FP-NEXT: qc.cm.pop {ra, s0-s11}, 96
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_restore s1
@@ -2418,61 +2398,60 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-NEXT: .cfi_offset s10, -136
; QCI-NEXT: .cfi_offset s11, -140
; QCI-NEXT: lui s0, %hi(var)
-; QCI-NEXT: lw a0, %lo(var)(s0)
+; QCI-NEXT: addi s0, s0, %lo(var)
+; QCI-NEXT: lw a0, 0(s0)
; QCI-NEXT: sw a0, 96(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+4)(s0)
+; QCI-NEXT: lw a0, 4(s0)
; QCI-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+8)(s0)
+; QCI-NEXT: lw a0, 8(s0)
; QCI-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+12)(s0)
+; QCI-NEXT: lw a0, 12(s0)
; QCI-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; QCI-NEXT: addi s1, s0, %lo(var)
-; QCI-NEXT: lw a0, 16(s1)
+; QCI-NEXT: lw a0, 16(s0)
; QCI-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 20(s1)
+; QCI-NEXT: lw a0, 20(s0)
; QCI-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 24(s1)
+; QCI-NEXT: lw a0, 24(s0)
; QCI-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 28(s1)
+; QCI-NEXT: lw a0, 28(s0)
; QCI-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 32(s1)
+; QCI-NEXT: lw a0, 32(s0)
; QCI-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 36(s1)
+; QCI-NEXT: lw a0, 36(s0)
; QCI-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 40(s1)
+; QCI-NEXT: lw a0, 40(s0)
; QCI-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 44(s1)
+; QCI-NEXT: lw a0, 44(s0)
; QCI-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 48(s1)
+; QCI-NEXT: lw a0, 48(s0)
; QCI-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 52(s1)
+; QCI-NEXT: lw a0, 52(s0)
; QCI-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 56(s1)
+; QCI-NEXT: lw a0, 56(s0)
; QCI-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 60(s1)
+; QCI-NEXT: lw a0, 60(s0)
; QCI-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 64(s1)
+; QCI-NEXT: lw a0, 64(s0)
; QCI-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 68(s1)
+; QCI-NEXT: lw a0, 68(s0)
; QCI-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 72(s1)
+; QCI-NEXT: lw a0, 72(s0)
; QCI-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 76(s1)
+; QCI-NEXT: lw a0, 76(s0)
; QCI-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 80(s1)
+; QCI-NEXT: lw a0, 80(s0)
; QCI-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 84(s1)
-; QCI-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw s4, 88(s1)
-; QCI-NEXT: lw s5, 92(s1)
-; QCI-NEXT: lw s6, 96(s1)
-; QCI-NEXT: lw s7, 100(s1)
-; QCI-NEXT: lw s8, 104(s1)
-; QCI-NEXT: lw s9, 108(s1)
-; QCI-NEXT: lw s10, 112(s1)
-; QCI-NEXT: lw s11, 116(s1)
-; QCI-NEXT: lw s2, 120(s1)
-; QCI-NEXT: lw s3, 124(s1)
+; QCI-NEXT: lw s1, 84(s0)
+; QCI-NEXT: lw s2, 88(s0)
+; QCI-NEXT: lw s3, 92(s0)
+; QCI-NEXT: lw s4, 96(s0)
+; QCI-NEXT: lw s5, 100(s0)
+; QCI-NEXT: lw s6, 104(s0)
+; QCI-NEXT: lw s7, 108(s0)
+; QCI-NEXT: lw s8, 112(s0)
+; QCI-NEXT: lw s9, 116(s0)
+; QCI-NEXT: lw s10, 120(s0)
+; QCI-NEXT: lw s11, 124(s0)
; QCI-NEXT: li a0, 4
; QCI-NEXT: li a2, 1
; QCI-NEXT: li a4, 2
@@ -2485,60 +2464,59 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-NEXT: li a7, 0
; QCI-NEXT: call function_with_one_stack_arg
; QCI-NEXT: call use_i64
-; QCI-NEXT: sw s3, 124(s1)
-; QCI-NEXT: sw s2, 120(s1)
-; QCI-NEXT: sw s11, 116(s1)
-; QCI-NEXT: sw s10, 112(s1)
-; QCI-NEXT: sw s9, 108(s1)
-; QCI-NEXT: sw s8, 104(s1)
-; QCI-NEXT: sw s7, 100(s1)
-; QCI-NEXT: sw s6, 96(s1)
-; QCI-NEXT: sw s5, 92(s1)
-; QCI-NEXT: sw s4, 88(s1)
-; QCI-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 84(s1)
+; QCI-NEXT: sw s11, 124(s0)
+; QCI-NEXT: sw s10, 120(s0)
+; QCI-NEXT: sw s9, 116(s0)
+; QCI-NEXT: sw s8, 112(s0)
+; QCI-NEXT: sw s7, 108(s0)
+; QCI-NEXT: sw s6, 104(s0)
+; QCI-NEXT: sw s5, 100(s0)
+; QCI-NEXT: sw s4, 96(s0)
+; QCI-NEXT: sw s3, 92(s0)
+; QCI-NEXT: sw s2, 88(s0)
+; QCI-NEXT: sw s1, 84(s0)
; QCI-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 80(s1)
+; QCI-NEXT: sw a0, 80(s0)
; QCI-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 76(s1)
+; QCI-NEXT: sw a0, 76(s0)
; QCI-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 72(s1)
+; QCI-NEXT: sw a0, 72(s0)
; QCI-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 68(s1)
+; QCI-NEXT: sw a0, 68(s0)
; QCI-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 64(s1)
+; QCI-NEXT: sw a0, 64(s0)
; QCI-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 60(s1)
+; QCI-NEXT: sw a0, 60(s0)
; QCI-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 56(s1)
+; QCI-NEXT: sw a0, 56(s0)
; QCI-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 52(s1)
+; QCI-NEXT: sw a0, 52(s0)
; QCI-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 48(s1)
+; QCI-NEXT: sw a0, 48(s0)
; QCI-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 44(s1)
+; QCI-NEXT: sw a0, 44(s0)
; QCI-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 40(s1)
+; QCI-NEXT: sw a0, 40(s0)
; QCI-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 36(s1)
+; QCI-NEXT: sw a0, 36(s0)
; QCI-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 32(s1)
+; QCI-NEXT: sw a0, 32(s0)
; QCI-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 28(s1)
+; QCI-NEXT: sw a0, 28(s0)
; QCI-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 24(s1)
+; QCI-NEXT: sw a0, 24(s0)
; QCI-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 20(s1)
+; QCI-NEXT: sw a0, 20(s0)
; QCI-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 16(s1)
+; QCI-NEXT: sw a0, 16(s0)
; QCI-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+12)(s0)
+; QCI-NEXT: sw a0, 12(s0)
; QCI-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+8)(s0)
+; QCI-NEXT: sw a0, 8(s0)
; QCI-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+4)(s0)
+; QCI-NEXT: sw a0, 4(s0)
; QCI-NEXT: lw a0, 96(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var)(s0)
+; QCI-NEXT: sw a0, 0(s0)
; QCI-NEXT: lw s1, 140(sp) # 4-byte Folded Reload
; QCI-NEXT: lw s2, 136(sp) # 4-byte Folded Reload
; QCI-NEXT: lw s3, 132(sp) # 4-byte Folded Reload
@@ -2611,16 +2589,16 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-FP-NEXT: .cfi_offset s10, -136
; QCI-FP-NEXT: .cfi_offset s11, -140
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
-; QCI-FP-NEXT: lui s6, %hi(var)
-; QCI-FP-NEXT: lw a0, %lo(var)(s6)
+; QCI-FP-NEXT: lui s1, %hi(var)
+; QCI-FP-NEXT: addi s1, s1, %lo(var)
+; QCI-FP-NEXT: lw a0, 0(s1)
; QCI-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+4)(s6)
+; QCI-FP-NEXT: lw a0, 4(s1)
; QCI-FP-NEXT: sw a0, -148(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+8)(s6)
+; QCI-FP-NEXT: lw a0, 8(s1)
; QCI-FP-NEXT: sw a0, -152(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+12)(s6)
+; QCI-FP-NEXT: lw a0, 12(s1)
; QCI-FP-NEXT: sw a0, -156(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: addi s1, s6, %lo(var)
; QCI-FP-NEXT: lw a0, 16(s1)
; QCI-FP-NEXT: sw a0, -160(s0) # 4-byte Folded Spill
; QCI-FP-NEXT: lw a0, 20(s1)
@@ -2657,17 +2635,16 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-FP-NEXT: sw a0, -224(s0) # 4-byte Folded Spill
; QCI-FP-NEXT: lw a0, 84(s1)
; QCI-FP-NEXT: sw a0, -228(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, 88(s1)
-; QCI-FP-NEXT: sw a0, -232(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw s8, 92(s1)
-; QCI-FP-NEXT: lw s9, 96(s1)
-; QCI-FP-NEXT: lw s10, 100(s1)
-; QCI-FP-NEXT: lw s11, 104(s1)
-; QCI-FP-NEXT: lw s2, 108(s1)
-; QCI-FP-NEXT: lw s3, 112(s1)
-; QCI-FP-NEXT: lw s4, 116(s1)
-; QCI-FP-NEXT: lw s5, 120(s1)
-; QCI-FP-NEXT: lw s7, 124(s1)
+; QCI-FP-NEXT: lw s4, 88(s1)
+; QCI-FP-NEXT: lw s5, 92(s1)
+; QCI-FP-NEXT: lw s6, 96(s1)
+; QCI-FP-NEXT: lw s7, 100(s1)
+; QCI-FP-NEXT: lw s8, 104(s1)
+; QCI-FP-NEXT: lw s9, 108(s1)
+; QCI-FP-NEXT: lw s10, 112(s1)
+; QCI-FP-NEXT: lw s11, 116(s1)
+; QCI-FP-NEXT: lw s2, 120(s1)
+; QCI-FP-NEXT: lw s3, 124(s1)
; QCI-FP-NEXT: li a0, 4
; QCI-FP-NEXT: li a2, 1
; QCI-FP-NEXT: li a4, 2
@@ -2680,17 +2657,16 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-FP-NEXT: li a7, 0
; QCI-FP-NEXT: call function_with_one_stack_arg
; QCI-FP-NEXT: call use_i64
-; QCI-FP-NEXT: sw s7, 124(s1)
-; QCI-FP-NEXT: sw s5, 120(s1)
-; QCI-FP-NEXT: sw s4, 116(s1)
-; QCI-FP-NEXT: sw s3, 112(s1)
-; QCI-FP-NEXT: sw s2, 108(s1)
-; QCI-FP-NEXT: sw s11, 104(s1)
-; QCI-FP-NEXT: sw s10, 100(s1)
-; QCI-FP-NEXT: sw s9, 96(s1)
-; QCI-FP-NEXT: sw s8, 92(s1)
-; QCI-FP-NEXT: lw a0, -232(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, 88(s1)
+; QCI-FP-NEXT: sw s3, 124(s1)
+; QCI-FP-NEXT: sw s2, 120(s1)
+; QCI-FP-NEXT: sw s11, 116(s1)
+; QCI-FP-NEXT: sw s10, 112(s1)
+; QCI-FP-NEXT: sw s9, 108(s1)
+; QCI-FP-NEXT: sw s8, 104(s1)
+; QCI-FP-NEXT: sw s7, 100(s1)
+; QCI-FP-NEXT: sw s6, 96(s1)
+; QCI-FP-NEXT: sw s5, 92(s1)
+; QCI-FP-NEXT: sw s4, 88(s1)
; QCI-FP-NEXT: lw a0, -228(s0) # 4-byte Folded Reload
; QCI-FP-NEXT: sw a0, 84(s1)
; QCI-FP-NEXT: lw a0, -224(s0) # 4-byte Folded Reload
@@ -2728,13 +2704,13 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-FP-NEXT: lw a0, -160(s0) # 4-byte Folded Reload
; QCI-FP-NEXT: sw a0, 16(s1)
; QCI-FP-NEXT: lw a0, -156(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+12)(s6)
+; QCI-FP-NEXT: sw a0, 12(s1)
; QCI-FP-NEXT: lw a0, -152(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+8)(s6)
+; QCI-FP-NEXT: sw a0, 8(s1)
; QCI-FP-NEXT: lw a0, -148(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+4)(s6)
+; QCI-FP-NEXT: sw a0, 4(s1)
; QCI-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var)(s6)
+; QCI-FP-NEXT: sw a0, 0(s1)
; QCI-FP-NEXT: .cfi_def_cfa sp, 240
; QCI-FP-NEXT: lw s1, 140(sp) # 4-byte Folded Reload
; QCI-FP-NEXT: lw s2, 136(sp) # 4-byte Folded Reload
@@ -2799,61 +2775,60 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-PUSH-POP-NEXT: addi sp, sp, -48
; QCI-PUSH-POP-NEXT: .cfi_def_cfa_offset 256
; QCI-PUSH-POP-NEXT: lui s0, %hi(var)
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var)(s0)
+; QCI-PUSH-POP-NEXT: addi s0, s0, %lo(var)
+; QCI-PUSH-POP-NEXT: lw a0, 0(s0)
; QCI-PUSH-POP-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+4)(s0)
+; QCI-PUSH-POP-NEXT: lw a0, 4(s0)
; QCI-PUSH-POP-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+8)(s0)
+; QCI-PUSH-POP-NEXT: lw a0, 8(s0)
; QCI-PUSH-POP-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+12)(s0)
+; QCI-PUSH-POP-NEXT: lw a0, 12(s0)
; QCI-PUSH-POP-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: addi s1, s0, %lo(var)
-; QCI-PUSH-POP-NEXT: lw a0, 16(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 16(s0)
; QCI-PUSH-POP-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 20(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 20(s0)
; QCI-PUSH-POP-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 24(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 24(s0)
; QCI-PUSH-POP-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 28(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 28(s0)
; QCI-PUSH-POP-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 32(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 32(s0)
; QCI-PUSH-POP-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 36(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 36(s0)
; QCI-PUSH-POP-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 40(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 40(s0)
; QCI-PUSH-POP-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 44(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 44(s0)
; QCI-PUSH-POP-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 48(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 48(s0)
; QCI-PUSH-POP-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 52(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 52(s0)
; QCI-PUSH-POP-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 56(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 56(s0)
; QCI-PUSH-POP-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 60(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 60(s0)
; QCI-PUSH-POP-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 64(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 64(s0)
; QCI-PUSH-POP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 68(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 68(s0)
; QCI-PUSH-POP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 72(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 72(s0)
; QCI-PUSH-POP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 76(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 76(s0)
; QCI-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 80(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 80(s0)
; QCI-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 84(s1)
-; QCI-PUSH-POP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw s4, 88(s1)
-; QCI-PUSH-POP-NEXT: lw s5, 92(s1)
-; QCI-PUSH-POP-NEXT: lw s6, 96(s1)
-; QCI-PUSH-POP-NEXT: lw s7, 100(s1)
-; QCI-PUSH-POP-NEXT: lw s8, 104(s1)
-; QCI-PUSH-POP-NEXT: lw s9, 108(s1)
-; QCI-PUSH-POP-NEXT: lw s10, 112(s1)
-; QCI-PUSH-POP-NEXT: lw s11, 116(s1)
-; QCI-PUSH-POP-NEXT: lw s2, 120(s1)
-; QCI-PUSH-POP-NEXT: lw s3, 124(s1)
+; QCI-PUSH-POP-NEXT: lw s1, 84(s0)
+; QCI-PUSH-POP-NEXT: lw s2, 88(s0)
+; QCI-PUSH-POP-NEXT: lw s3, 92(s0)
+; QCI-PUSH-POP-NEXT: lw s4, 96(s0)
+; QCI-PUSH-POP-NEXT: lw s5, 100(s0)
+; QCI-PUSH-POP-NEXT: lw s6, 104(s0)
+; QCI-PUSH-POP-NEXT: lw s7, 108(s0)
+; QCI-PUSH-POP-NEXT: lw s8, 112(s0)
+; QCI-PUSH-POP-NEXT: lw s9, 116(s0)
+; QCI-PUSH-POP-NEXT: lw s10, 120(s0)
+; QCI-PUSH-POP-NEXT: lw s11, 124(s0)
; QCI-PUSH-POP-NEXT: li a0, 4
; QCI-PUSH-POP-NEXT: li a2, 1
; QCI-PUSH-POP-NEXT: li a4, 2
@@ -2866,60 +2841,59 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-PUSH-POP-NEXT: li a7, 0
; QCI-PUSH-POP-NEXT: call function_with_one_stack_arg
; QCI-PUSH-POP-NEXT: call use_i64
-; QCI-PUSH-POP-NEXT: sw s3, 124(s1)
-; QCI-PUSH-POP-NEXT: sw s2, 120(s1)
-; QCI-PUSH-POP-NEXT: sw s11, 116(s1)
-; QCI-PUSH-POP-NEXT: sw s10, 112(s1)
-; QCI-PUSH-POP-NEXT: sw s9, 108(s1)
-; QCI-PUSH-POP-NEXT: sw s8, 104(s1)
-; QCI-PUSH-POP-NEXT: sw s7, 100(s1)
-; QCI-PUSH-POP-NEXT: sw s6, 96(s1)
-; QCI-PUSH-POP-NEXT: sw s5, 92(s1)
-; QCI-PUSH-POP-NEXT: sw s4, 88(s1)
-; QCI-PUSH-POP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 84(s1)
+; QCI-PUSH-POP-NEXT: sw s11, 124(s0)
+; QCI-PUSH-POP-NEXT: sw s10, 120(s0)
+; QCI-PUSH-POP-NEXT: sw s9, 116(s0)
+; QCI-PUSH-POP-NEXT: sw s8, 112(s0)
+; QCI-PUSH-POP-NEXT: sw s7, 108(s0)
+; QCI-PUSH-POP-NEXT: sw s6, 104(s0)
+; QCI-PUSH-POP-NEXT: sw s5, 100(s0)
+; QCI-PUSH-POP-NEXT: sw s4, 96(s0)
+; QCI-PUSH-POP-NEXT: sw s3, 92(s0)
+; QCI-PUSH-POP-NEXT: sw s2, 88(s0)
+; QCI-PUSH-POP-NEXT: sw s1, 84(s0)
; QCI-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 80(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 80(s0)
; QCI-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 76(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 76(s0)
; QCI-PUSH-POP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 72(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 72(s0)
; QCI-PUSH-POP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 68(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 68(s0)
; QCI-PUSH-POP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 64(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 64(s0)
; QCI-PUSH-POP-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 60(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 60(s0)
; QCI-PUSH-POP-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 56(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 56(s0)
; QCI-PUSH-POP-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 52(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 52(s0)
; QCI-PUSH-POP-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 48(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 48(s0)
; QCI-PUSH-POP-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 44(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 44(s0)
; QCI-PUSH-POP-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 40(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 40(s0)
; QCI-PUSH-POP-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 36(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 36(s0)
; QCI-PUSH-POP-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 32(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 32(s0)
; QCI-PUSH-POP-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 28(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 28(s0)
; QCI-PUSH-POP-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 24(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 24(s0)
; QCI-PUSH-POP-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 20(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 20(s0)
; QCI-PUSH-POP-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 16(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 16(s0)
; QCI-PUSH-POP-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+12)(s0)
+; QCI-PUSH-POP-NEXT: sw a0, 12(s0)
; QCI-PUSH-POP-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+8)(s0)
+; QCI-PUSH-POP-NEXT: sw a0, 8(s0)
; QCI-PUSH-POP-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+4)(s0)
+; QCI-PUSH-POP-NEXT: sw a0, 4(s0)
; QCI-PUSH-POP-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var)(s0)
+; QCI-PUSH-POP-NEXT: sw a0, 0(s0)
; QCI-PUSH-POP-NEXT: addi sp, sp, 48
; QCI-PUSH-POP-NEXT: .cfi_def_cfa_offset 208
; QCI-PUSH-POP-NEXT: cm.pop {ra, s0-s11}, 112
@@ -2974,61 +2948,60 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-NEXT: addi sp, sp, -48
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_def_cfa_offset 256
; QCI-QCCMP-PUSH-POP-NEXT: lui s0, %hi(var)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: addi s0, s0, %lo(var)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 0(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+4)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 4(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+8)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 8(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+12)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 12(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: addi s1, s0, %lo(var)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 20(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 20(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 24(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 24(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 28(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 28(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 32(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 32(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 36(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 36(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 40(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 40(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 44(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 44(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 48(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 48(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 52(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 52(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 56(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 56(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 60(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 60(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 64(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 64(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 68(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 68(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 72(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 72(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 76(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 76(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 80(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 80(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 84(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 88(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 92(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 96(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 100(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 104(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 108(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 112(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 116(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 120(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 124(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 84(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 88(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 92(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 96(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 100(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 104(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 108(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 112(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 116(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 120(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 124(s0)
; QCI-QCCMP-PUSH-POP-NEXT: li a0, 4
; QCI-QCCMP-PUSH-POP-NEXT: li a2, 1
; QCI-QCCMP-PUSH-POP-NEXT: li a4, 2
@@ -3041,60 +3014,59 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-NEXT: li a7, 0
; QCI-QCCMP-PUSH-POP-NEXT: call function_with_one_stack_arg
; QCI-QCCMP-PUSH-POP-NEXT: call use_i64
-; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 124(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 120(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 116(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 112(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 108(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 104(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 100(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 96(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 92(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 88(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 84(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 124(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 120(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 116(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 112(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 108(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 104(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 100(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 96(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 92(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 88(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 84(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 80(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 80(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 76(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 76(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 72(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 72(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 68(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 68(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 64(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 64(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 60(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 60(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 56(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 56(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 52(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 52(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 48(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 48(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 44(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 44(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 40(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 40(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 36(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 36(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 32(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 32(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 28(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 28(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 24(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 24(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 20(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 20(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+12)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 12(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+8)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 8(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+4)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 4(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 0(s0)
; QCI-QCCMP-PUSH-POP-NEXT: addi sp, sp, 48
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_def_cfa_offset 208
; QCI-QCCMP-PUSH-POP-NEXT: qc.cm.pop {ra, s0-s11}, 112
@@ -3149,16 +3121,16 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: addi sp, sp, -48
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa_offset 256
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa s0, 0
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lui s6, %hi(var)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lui s1, %hi(var)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: addi s1, s1, %lo(var)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 0(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -164(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+4)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 4(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -168(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+8)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 8(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -172(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+12)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 12(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -176(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: addi s1, s6, %lo(var)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 16(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -180(s0) # 4-byte Folded Spill
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 20(s1)
@@ -3195,17 +3167,16 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -244(s0) # 4-byte Folded Spill
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 84(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -248(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 88(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -252(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 92(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 96(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 100(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 104(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 108(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 112(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 116(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 120(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 124(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 88(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 92(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s6, 96(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 100(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 104(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 108(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 112(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 116(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 120(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 124(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: li a0, 4
; QCI-QCCMP-PUSH-POP-FP-NEXT: li a2, 1
; QCI-QCCMP-PUSH-POP-FP-NEXT: li a4, 2
@@ -3218,17 +3189,16 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: li a7, 0
; QCI-QCCMP-PUSH-POP-FP-NEXT: call function_with_one_stack_arg
; QCI-QCCMP-PUSH-POP-FP-NEXT: call use_i64
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 124(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 120(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 116(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 112(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 108(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 104(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 100(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 96(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 92(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -252(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 88(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 124(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 120(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 116(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 112(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 108(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 104(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 100(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s6, 96(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 92(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 88(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -248(s0) # 4-byte Folded Reload
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 84(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -244(s0) # 4-byte Folded Reload
@@ -3266,13 +3236,13 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -180(s0) # 4-byte Folded Reload
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 16(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -176(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+12)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 12(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -172(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+8)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 8(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -168(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+4)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 4(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -164(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 0(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa sp, 256
; QCI-QCCMP-PUSH-POP-FP-NEXT: addi sp, sp, 48
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa_offset 208
@@ -3344,61 +3314,60 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-NEXT: .cfi_offset s10, -136
; QCI-NEXT: .cfi_offset s11, -140
; QCI-NEXT: lui s0, %hi(var)
-; QCI-NEXT: lw a0, %lo(var)(s0)
+; QCI-NEXT: addi s0, s0, %lo(var)
+; QCI-NEXT: lw a0, 0(s0)
; QCI-NEXT: sw a0, 96(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+4)(s0)
+; QCI-NEXT: lw a0, 4(s0)
; QCI-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+8)(s0)
+; QCI-NEXT: lw a0, 8(s0)
; QCI-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, %lo(var+12)(s0)
+; QCI-NEXT: lw a0, 12(s0)
; QCI-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; QCI-NEXT: addi s1, s0, %lo(var)
-; QCI-NEXT: lw a0, 16(s1)
+; QCI-NEXT: lw a0, 16(s0)
; QCI-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 20(s1)
+; QCI-NEXT: lw a0, 20(s0)
; QCI-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 24(s1)
+; QCI-NEXT: lw a0, 24(s0)
; QCI-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 28(s1)
+; QCI-NEXT: lw a0, 28(s0)
; QCI-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 32(s1)
+; QCI-NEXT: lw a0, 32(s0)
; QCI-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 36(s1)
+; QCI-NEXT: lw a0, 36(s0)
; QCI-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 40(s1)
+; QCI-NEXT: lw a0, 40(s0)
; QCI-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 44(s1)
+; QCI-NEXT: lw a0, 44(s0)
; QCI-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 48(s1)
+; QCI-NEXT: lw a0, 48(s0)
; QCI-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 52(s1)
+; QCI-NEXT: lw a0, 52(s0)
; QCI-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 56(s1)
+; QCI-NEXT: lw a0, 56(s0)
; QCI-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 60(s1)
+; QCI-NEXT: lw a0, 60(s0)
; QCI-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 64(s1)
+; QCI-NEXT: lw a0, 64(s0)
; QCI-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 68(s1)
+; QCI-NEXT: lw a0, 68(s0)
; QCI-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 72(s1)
+; QCI-NEXT: lw a0, 72(s0)
; QCI-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 76(s1)
+; QCI-NEXT: lw a0, 76(s0)
; QCI-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 80(s1)
+; QCI-NEXT: lw a0, 80(s0)
; QCI-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw a0, 84(s1)
-; QCI-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw s4, 88(s1)
-; QCI-NEXT: lw s5, 92(s1)
-; QCI-NEXT: lw s6, 96(s1)
-; QCI-NEXT: lw s7, 100(s1)
-; QCI-NEXT: lw s8, 104(s1)
-; QCI-NEXT: lw s9, 108(s1)
-; QCI-NEXT: lw s10, 112(s1)
-; QCI-NEXT: lw s11, 116(s1)
-; QCI-NEXT: lw s2, 120(s1)
-; QCI-NEXT: lw s3, 124(s1)
+; QCI-NEXT: lw s1, 84(s0)
+; QCI-NEXT: lw s2, 88(s0)
+; QCI-NEXT: lw s3, 92(s0)
+; QCI-NEXT: lw s4, 96(s0)
+; QCI-NEXT: lw s5, 100(s0)
+; QCI-NEXT: lw s6, 104(s0)
+; QCI-NEXT: lw s7, 108(s0)
+; QCI-NEXT: lw s8, 112(s0)
+; QCI-NEXT: lw s9, 116(s0)
+; QCI-NEXT: lw s10, 120(s0)
+; QCI-NEXT: lw s11, 124(s0)
; QCI-NEXT: li a0, 4
; QCI-NEXT: li a2, 1
; QCI-NEXT: li a4, 2
@@ -3411,60 +3380,59 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-NEXT: li a7, 0
; QCI-NEXT: call function_with_one_stack_arg
; QCI-NEXT: call use_i64
-; QCI-NEXT: sw s3, 124(s1)
-; QCI-NEXT: sw s2, 120(s1)
-; QCI-NEXT: sw s11, 116(s1)
-; QCI-NEXT: sw s10, 112(s1)
-; QCI-NEXT: sw s9, 108(s1)
-; QCI-NEXT: sw s8, 104(s1)
-; QCI-NEXT: sw s7, 100(s1)
-; QCI-NEXT: sw s6, 96(s1)
-; QCI-NEXT: sw s5, 92(s1)
-; QCI-NEXT: sw s4, 88(s1)
-; QCI-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 84(s1)
+; QCI-NEXT: sw s11, 124(s0)
+; QCI-NEXT: sw s10, 120(s0)
+; QCI-NEXT: sw s9, 116(s0)
+; QCI-NEXT: sw s8, 112(s0)
+; QCI-NEXT: sw s7, 108(s0)
+; QCI-NEXT: sw s6, 104(s0)
+; QCI-NEXT: sw s5, 100(s0)
+; QCI-NEXT: sw s4, 96(s0)
+; QCI-NEXT: sw s3, 92(s0)
+; QCI-NEXT: sw s2, 88(s0)
+; QCI-NEXT: sw s1, 84(s0)
; QCI-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 80(s1)
+; QCI-NEXT: sw a0, 80(s0)
; QCI-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 76(s1)
+; QCI-NEXT: sw a0, 76(s0)
; QCI-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 72(s1)
+; QCI-NEXT: sw a0, 72(s0)
; QCI-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 68(s1)
+; QCI-NEXT: sw a0, 68(s0)
; QCI-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 64(s1)
+; QCI-NEXT: sw a0, 64(s0)
; QCI-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 60(s1)
+; QCI-NEXT: sw a0, 60(s0)
; QCI-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 56(s1)
+; QCI-NEXT: sw a0, 56(s0)
; QCI-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 52(s1)
+; QCI-NEXT: sw a0, 52(s0)
; QCI-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 48(s1)
+; QCI-NEXT: sw a0, 48(s0)
; QCI-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 44(s1)
+; QCI-NEXT: sw a0, 44(s0)
; QCI-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 40(s1)
+; QCI-NEXT: sw a0, 40(s0)
; QCI-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 36(s1)
+; QCI-NEXT: sw a0, 36(s0)
; QCI-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 32(s1)
+; QCI-NEXT: sw a0, 32(s0)
; QCI-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 28(s1)
+; QCI-NEXT: sw a0, 28(s0)
; QCI-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 24(s1)
+; QCI-NEXT: sw a0, 24(s0)
; QCI-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 20(s1)
+; QCI-NEXT: sw a0, 20(s0)
; QCI-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, 16(s1)
+; QCI-NEXT: sw a0, 16(s0)
; QCI-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+12)(s0)
+; QCI-NEXT: sw a0, 12(s0)
; QCI-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+8)(s0)
+; QCI-NEXT: sw a0, 8(s0)
; QCI-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var+4)(s0)
+; QCI-NEXT: sw a0, 4(s0)
; QCI-NEXT: lw a0, 96(sp) # 4-byte Folded Reload
-; QCI-NEXT: sw a0, %lo(var)(s0)
+; QCI-NEXT: sw a0, 0(s0)
; QCI-NEXT: lw s1, 140(sp) # 4-byte Folded Reload
; QCI-NEXT: lw s2, 136(sp) # 4-byte Folded Reload
; QCI-NEXT: lw s3, 132(sp) # 4-byte Folded Reload
@@ -3537,16 +3505,16 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: .cfi_offset s10, -136
; QCI-FP-NEXT: .cfi_offset s11, -140
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
-; QCI-FP-NEXT: lui s6, %hi(var)
-; QCI-FP-NEXT: lw a0, %lo(var)(s6)
+; QCI-FP-NEXT: lui s1, %hi(var)
+; QCI-FP-NEXT: addi s1, s1, %lo(var)
+; QCI-FP-NEXT: lw a0, 0(s1)
; QCI-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+4)(s6)
+; QCI-FP-NEXT: lw a0, 4(s1)
; QCI-FP-NEXT: sw a0, -148(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+8)(s6)
+; QCI-FP-NEXT: lw a0, 8(s1)
; QCI-FP-NEXT: sw a0, -152(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, %lo(var+12)(s6)
+; QCI-FP-NEXT: lw a0, 12(s1)
; QCI-FP-NEXT: sw a0, -156(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: addi s1, s6, %lo(var)
; QCI-FP-NEXT: lw a0, 16(s1)
; QCI-FP-NEXT: sw a0, -160(s0) # 4-byte Folded Spill
; QCI-FP-NEXT: lw a0, 20(s1)
@@ -3583,17 +3551,16 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: sw a0, -224(s0) # 4-byte Folded Spill
; QCI-FP-NEXT: lw a0, 84(s1)
; QCI-FP-NEXT: sw a0, -228(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw a0, 88(s1)
-; QCI-FP-NEXT: sw a0, -232(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw s8, 92(s1)
-; QCI-FP-NEXT: lw s9, 96(s1)
-; QCI-FP-NEXT: lw s10, 100(s1)
-; QCI-FP-NEXT: lw s11, 104(s1)
-; QCI-FP-NEXT: lw s2, 108(s1)
-; QCI-FP-NEXT: lw s3, 112(s1)
-; QCI-FP-NEXT: lw s4, 116(s1)
-; QCI-FP-NEXT: lw s5, 120(s1)
-; QCI-FP-NEXT: lw s7, 124(s1)
+; QCI-FP-NEXT: lw s4, 88(s1)
+; QCI-FP-NEXT: lw s5, 92(s1)
+; QCI-FP-NEXT: lw s6, 96(s1)
+; QCI-FP-NEXT: lw s7, 100(s1)
+; QCI-FP-NEXT: lw s8, 104(s1)
+; QCI-FP-NEXT: lw s9, 108(s1)
+; QCI-FP-NEXT: lw s10, 112(s1)
+; QCI-FP-NEXT: lw s11, 116(s1)
+; QCI-FP-NEXT: lw s2, 120(s1)
+; QCI-FP-NEXT: lw s3, 124(s1)
; QCI-FP-NEXT: li a0, 4
; QCI-FP-NEXT: li a2, 1
; QCI-FP-NEXT: li a4, 2
@@ -3606,17 +3573,16 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: li a7, 0
; QCI-FP-NEXT: call function_with_one_stack_arg
; QCI-FP-NEXT: call use_i64
-; QCI-FP-NEXT: sw s7, 124(s1)
-; QCI-FP-NEXT: sw s5, 120(s1)
-; QCI-FP-NEXT: sw s4, 116(s1)
-; QCI-FP-NEXT: sw s3, 112(s1)
-; QCI-FP-NEXT: sw s2, 108(s1)
-; QCI-FP-NEXT: sw s11, 104(s1)
-; QCI-FP-NEXT: sw s10, 100(s1)
-; QCI-FP-NEXT: sw s9, 96(s1)
-; QCI-FP-NEXT: sw s8, 92(s1)
-; QCI-FP-NEXT: lw a0, -232(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, 88(s1)
+; QCI-FP-NEXT: sw s3, 124(s1)
+; QCI-FP-NEXT: sw s2, 120(s1)
+; QCI-FP-NEXT: sw s11, 116(s1)
+; QCI-FP-NEXT: sw s10, 112(s1)
+; QCI-FP-NEXT: sw s9, 108(s1)
+; QCI-FP-NEXT: sw s8, 104(s1)
+; QCI-FP-NEXT: sw s7, 100(s1)
+; QCI-FP-NEXT: sw s6, 96(s1)
+; QCI-FP-NEXT: sw s5, 92(s1)
+; QCI-FP-NEXT: sw s4, 88(s1)
; QCI-FP-NEXT: lw a0, -228(s0) # 4-byte Folded Reload
; QCI-FP-NEXT: sw a0, 84(s1)
; QCI-FP-NEXT: lw a0, -224(s0) # 4-byte Folded Reload
@@ -3654,13 +3620,13 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: lw a0, -160(s0) # 4-byte Folded Reload
; QCI-FP-NEXT: sw a0, 16(s1)
; QCI-FP-NEXT: lw a0, -156(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+12)(s6)
+; QCI-FP-NEXT: sw a0, 12(s1)
; QCI-FP-NEXT: lw a0, -152(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+8)(s6)
+; QCI-FP-NEXT: sw a0, 8(s1)
; QCI-FP-NEXT: lw a0, -148(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var+4)(s6)
+; QCI-FP-NEXT: sw a0, 4(s1)
; QCI-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload
-; QCI-FP-NEXT: sw a0, %lo(var)(s6)
+; QCI-FP-NEXT: sw a0, 0(s1)
; QCI-FP-NEXT: .cfi_def_cfa sp, 240
; QCI-FP-NEXT: lw s1, 140(sp) # 4-byte Folded Reload
; QCI-FP-NEXT: lw s2, 136(sp) # 4-byte Folded Reload
@@ -3725,61 +3691,60 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-PUSH-POP-NEXT: addi sp, sp, -48
; QCI-PUSH-POP-NEXT: .cfi_def_cfa_offset 256
; QCI-PUSH-POP-NEXT: lui s0, %hi(var)
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var)(s0)
+; QCI-PUSH-POP-NEXT: addi s0, s0, %lo(var)
+; QCI-PUSH-POP-NEXT: lw a0, 0(s0)
; QCI-PUSH-POP-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+4)(s0)
+; QCI-PUSH-POP-NEXT: lw a0, 4(s0)
; QCI-PUSH-POP-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+8)(s0)
+; QCI-PUSH-POP-NEXT: lw a0, 8(s0)
; QCI-PUSH-POP-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, %lo(var+12)(s0)
+; QCI-PUSH-POP-NEXT: lw a0, 12(s0)
; QCI-PUSH-POP-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: addi s1, s0, %lo(var)
-; QCI-PUSH-POP-NEXT: lw a0, 16(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 16(s0)
; QCI-PUSH-POP-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 20(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 20(s0)
; QCI-PUSH-POP-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 24(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 24(s0)
; QCI-PUSH-POP-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 28(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 28(s0)
; QCI-PUSH-POP-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 32(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 32(s0)
; QCI-PUSH-POP-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 36(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 36(s0)
; QCI-PUSH-POP-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 40(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 40(s0)
; QCI-PUSH-POP-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 44(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 44(s0)
; QCI-PUSH-POP-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 48(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 48(s0)
; QCI-PUSH-POP-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 52(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 52(s0)
; QCI-PUSH-POP-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 56(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 56(s0)
; QCI-PUSH-POP-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 60(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 60(s0)
; QCI-PUSH-POP-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 64(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 64(s0)
; QCI-PUSH-POP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 68(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 68(s0)
; QCI-PUSH-POP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 72(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 72(s0)
; QCI-PUSH-POP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 76(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 76(s0)
; QCI-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 80(s1)
+; QCI-PUSH-POP-NEXT: lw a0, 80(s0)
; QCI-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw a0, 84(s1)
-; QCI-PUSH-POP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw s4, 88(s1)
-; QCI-PUSH-POP-NEXT: lw s5, 92(s1)
-; QCI-PUSH-POP-NEXT: lw s6, 96(s1)
-; QCI-PUSH-POP-NEXT: lw s7, 100(s1)
-; QCI-PUSH-POP-NEXT: lw s8, 104(s1)
-; QCI-PUSH-POP-NEXT: lw s9, 108(s1)
-; QCI-PUSH-POP-NEXT: lw s10, 112(s1)
-; QCI-PUSH-POP-NEXT: lw s11, 116(s1)
-; QCI-PUSH-POP-NEXT: lw s2, 120(s1)
-; QCI-PUSH-POP-NEXT: lw s3, 124(s1)
+; QCI-PUSH-POP-NEXT: lw s1, 84(s0)
+; QCI-PUSH-POP-NEXT: lw s2, 88(s0)
+; QCI-PUSH-POP-NEXT: lw s3, 92(s0)
+; QCI-PUSH-POP-NEXT: lw s4, 96(s0)
+; QCI-PUSH-POP-NEXT: lw s5, 100(s0)
+; QCI-PUSH-POP-NEXT: lw s6, 104(s0)
+; QCI-PUSH-POP-NEXT: lw s7, 108(s0)
+; QCI-PUSH-POP-NEXT: lw s8, 112(s0)
+; QCI-PUSH-POP-NEXT: lw s9, 116(s0)
+; QCI-PUSH-POP-NEXT: lw s10, 120(s0)
+; QCI-PUSH-POP-NEXT: lw s11, 124(s0)
; QCI-PUSH-POP-NEXT: li a0, 4
; QCI-PUSH-POP-NEXT: li a2, 1
; QCI-PUSH-POP-NEXT: li a4, 2
@@ -3792,60 +3757,59 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-PUSH-POP-NEXT: li a7, 0
; QCI-PUSH-POP-NEXT: call function_with_one_stack_arg
; QCI-PUSH-POP-NEXT: call use_i64
-; QCI-PUSH-POP-NEXT: sw s3, 124(s1)
-; QCI-PUSH-POP-NEXT: sw s2, 120(s1)
-; QCI-PUSH-POP-NEXT: sw s11, 116(s1)
-; QCI-PUSH-POP-NEXT: sw s10, 112(s1)
-; QCI-PUSH-POP-NEXT: sw s9, 108(s1)
-; QCI-PUSH-POP-NEXT: sw s8, 104(s1)
-; QCI-PUSH-POP-NEXT: sw s7, 100(s1)
-; QCI-PUSH-POP-NEXT: sw s6, 96(s1)
-; QCI-PUSH-POP-NEXT: sw s5, 92(s1)
-; QCI-PUSH-POP-NEXT: sw s4, 88(s1)
-; QCI-PUSH-POP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 84(s1)
+; QCI-PUSH-POP-NEXT: sw s11, 124(s0)
+; QCI-PUSH-POP-NEXT: sw s10, 120(s0)
+; QCI-PUSH-POP-NEXT: sw s9, 116(s0)
+; QCI-PUSH-POP-NEXT: sw s8, 112(s0)
+; QCI-PUSH-POP-NEXT: sw s7, 108(s0)
+; QCI-PUSH-POP-NEXT: sw s6, 104(s0)
+; QCI-PUSH-POP-NEXT: sw s5, 100(s0)
+; QCI-PUSH-POP-NEXT: sw s4, 96(s0)
+; QCI-PUSH-POP-NEXT: sw s3, 92(s0)
+; QCI-PUSH-POP-NEXT: sw s2, 88(s0)
+; QCI-PUSH-POP-NEXT: sw s1, 84(s0)
; QCI-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 80(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 80(s0)
; QCI-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 76(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 76(s0)
; QCI-PUSH-POP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 72(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 72(s0)
; QCI-PUSH-POP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 68(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 68(s0)
; QCI-PUSH-POP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 64(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 64(s0)
; QCI-PUSH-POP-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 60(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 60(s0)
; QCI-PUSH-POP-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 56(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 56(s0)
; QCI-PUSH-POP-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 52(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 52(s0)
; QCI-PUSH-POP-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 48(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 48(s0)
; QCI-PUSH-POP-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 44(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 44(s0)
; QCI-PUSH-POP-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 40(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 40(s0)
; QCI-PUSH-POP-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 36(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 36(s0)
; QCI-PUSH-POP-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 32(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 32(s0)
; QCI-PUSH-POP-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 28(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 28(s0)
; QCI-PUSH-POP-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 24(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 24(s0)
; QCI-PUSH-POP-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 20(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 20(s0)
; QCI-PUSH-POP-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, 16(s1)
+; QCI-PUSH-POP-NEXT: sw a0, 16(s0)
; QCI-PUSH-POP-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+12)(s0)
+; QCI-PUSH-POP-NEXT: sw a0, 12(s0)
; QCI-PUSH-POP-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+8)(s0)
+; QCI-PUSH-POP-NEXT: sw a0, 8(s0)
; QCI-PUSH-POP-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var+4)(s0)
+; QCI-PUSH-POP-NEXT: sw a0, 4(s0)
; QCI-PUSH-POP-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; QCI-PUSH-POP-NEXT: sw a0, %lo(var)(s0)
+; QCI-PUSH-POP-NEXT: sw a0, 0(s0)
; QCI-PUSH-POP-NEXT: addi sp, sp, 48
; QCI-PUSH-POP-NEXT: .cfi_def_cfa_offset 208
; QCI-PUSH-POP-NEXT: cm.pop {ra, s0-s11}, 112
@@ -3900,61 +3864,60 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-NEXT: addi sp, sp, -48
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_def_cfa_offset 256
; QCI-QCCMP-PUSH-POP-NEXT: lui s0, %hi(var)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: addi s0, s0, %lo(var)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 0(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+4)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 4(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+8)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 8(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, %lo(var+12)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 12(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: addi s1, s0, %lo(var)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 20(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 20(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 24(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 24(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 28(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 28(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 32(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 32(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 36(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 36(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 40(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 40(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 44(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 44(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 48(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 48(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 52(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 52(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 56(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 56(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 60(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 60(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 64(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 64(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 68(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 68(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 72(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 72(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 76(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 76(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 80(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 80(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 84(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 88(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 92(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 96(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 100(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 104(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 108(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 112(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 116(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 120(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 124(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 84(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 88(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 92(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 96(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 100(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 104(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 108(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 112(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 116(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 120(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 124(s0)
; QCI-QCCMP-PUSH-POP-NEXT: li a0, 4
; QCI-QCCMP-PUSH-POP-NEXT: li a2, 1
; QCI-QCCMP-PUSH-POP-NEXT: li a4, 2
@@ -3967,60 +3930,59 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-NEXT: li a7, 0
; QCI-QCCMP-PUSH-POP-NEXT: call function_with_one_stack_arg
; QCI-QCCMP-PUSH-POP-NEXT: call use_i64
-; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 124(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 120(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 116(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 112(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 108(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 104(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 100(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 96(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 92(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 88(s1)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 84(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 124(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 120(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 116(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 112(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 108(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 104(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 100(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 96(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 92(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 88(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 84(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 80(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 80(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 76(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 76(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 72(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 72(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 68(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 68(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 64(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 64(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 60(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 60(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 56(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 56(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 52(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 52(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 48(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 48(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 44(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 44(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 40(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 40(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 36(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 36(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 32(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 32(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 28(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 28(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 24(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 24(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 20(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 20(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(s1)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+12)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 12(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+8)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 8(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var+4)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 4(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-NEXT: sw a0, %lo(var)(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 0(s0)
; QCI-QCCMP-PUSH-POP-NEXT: addi sp, sp, 48
; QCI-QCCMP-PUSH-POP-NEXT: .cfi_def_cfa_offset 208
; QCI-QCCMP-PUSH-POP-NEXT: qc.cm.pop {ra, s0-s11}, 112
@@ -4075,16 +4037,16 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: addi sp, sp, -48
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa_offset 256
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa s0, 0
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lui s6, %hi(var)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lui s1, %hi(var)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: addi s1, s1, %lo(var)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 0(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -164(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+4)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 4(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -168(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+8)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 8(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -172(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, %lo(var+12)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 12(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -176(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: addi s1, s6, %lo(var)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 16(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -180(s0) # 4-byte Folded Spill
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 20(s1)
@@ -4121,17 +4083,16 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -244(s0) # 4-byte Folded Spill
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 84(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -248(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, 88(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, -252(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 92(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 96(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 100(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 104(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 108(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 112(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 116(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 120(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 124(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 88(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 92(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s6, 96(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 100(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 104(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 108(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 112(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 116(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 120(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 124(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: li a0, 4
; QCI-QCCMP-PUSH-POP-FP-NEXT: li a2, 1
; QCI-QCCMP-PUSH-POP-FP-NEXT: li a4, 2
@@ -4144,17 +4105,16 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: li a7, 0
; QCI-QCCMP-PUSH-POP-FP-NEXT: call function_with_one_stack_arg
; QCI-QCCMP-PUSH-POP-FP-NEXT: call use_i64
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 124(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 120(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 116(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 112(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 108(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 104(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 100(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 96(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 92(s1)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -252(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 88(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 124(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 120(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 116(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 112(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 108(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 104(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 100(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s6, 96(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 92(s1)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 88(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -248(s0) # 4-byte Folded Reload
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 84(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -244(s0) # 4-byte Folded Reload
@@ -4192,13 +4152,13 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -180(s0) # 4-byte Folded Reload
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 16(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -176(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+12)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 12(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -172(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+8)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 8(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -168(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var+4)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 4(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a0, -164(s0) # 4-byte Folded Reload
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, %lo(var)(s6)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a0, 0(s1)
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa sp, 256
; QCI-QCCMP-PUSH-POP-FP-NEXT: addi sp, sp, 48
; QCI-QCCMP-PUSH-POP-FP-NEXT: .cfi_def_cfa_offset 208
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll
index 391117c72ece7..d04dbe9bf27ed 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll
@@ -13,13 +13,13 @@ define void @baz() nounwind {
; CHECK-LABEL: baz:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(foo)
-; CHECK-NEXT: addi a1, a0, %lo(foo)
-; CHECK-NEXT: lw a1, 4(a1)
-; CHECK-NEXT: lw a0, %lo(foo)(a0)
+; CHECK-NEXT: addi a0, a0, %lo(foo)
+; CHECK-NEXT: lw a1, 4(a0)
+; CHECK-NEXT: lw a0, 0(a0)
; CHECK-NEXT: lui a2, %hi(bar)
-; CHECK-NEXT: sw a1, %lo(bar)(a2)
-; CHECK-NEXT: addi a1, a2, %lo(bar)
-; CHECK-NEXT: sw a0, 4(a1)
+; CHECK-NEXT: addi a2, a2, %lo(bar)
+; CHECK-NEXT: sw a1, 0(a2)
+; CHECK-NEXT: sw a0, 4(a2)
; CHECK-NEXT: ret
entry:
%0 = load i32, ptr getelementptr inbounds ([2 x i32], ptr @foo, i64 0, i64 1), align 4
diff --git a/llvm/test/CodeGen/RISCV/saverestore.ll b/llvm/test/CodeGen/RISCV/saverestore.ll
index f3dc2d0ef5078..f753f817b0ab6 100644
--- a/llvm/test/CodeGen/RISCV/saverestore.ll
+++ b/llvm/test/CodeGen/RISCV/saverestore.ll
@@ -21,20 +21,20 @@ define void @callee_saved0() nounwind {
; RV64I-NOT: tail __riscv_restore
;
; RV32I-SR-LABEL: callee_saved0:
-; RV32I-SR: call t0, __riscv_save_5
-; RV32I-SR: tail __riscv_restore_5
+; RV32I-SR: call t0, __riscv_save_4
+; RV32I-SR: tail __riscv_restore_4
;
; RV64I-SR-LABEL: callee_saved0:
-; RV64I-SR: call t0, __riscv_save_5
-; RV64I-SR: tail __riscv_restore_5
+; RV64I-SR: call t0, __riscv_save_4
+; RV64I-SR: tail __riscv_restore_4
;
; RV32I-FP-SR-LABEL: callee_saved0:
-; RV32I-FP-SR: call t0, __riscv_save_5
-; RV32I-FP-SR: tail __riscv_restore_5
+; RV32I-FP-SR: call t0, __riscv_save_4
+; RV32I-FP-SR: tail __riscv_restore_4
;
; RV64I-FP-SR-LABEL: callee_saved0:
-; RV64I-FP-SR: call t0, __riscv_save_5
-; RV64I-FP-SR: tail __riscv_restore_5
+; RV64I-FP-SR: call t0, __riscv_save_4
+; RV64I-FP-SR: tail __riscv_restore_4
%val = load [18 x i32], ptr @var0
store volatile [18 x i32] %val, ptr @var0
ret void
@@ -50,20 +50,20 @@ define void @callee_saved1() nounwind {
; RV64I-NOT: tail __riscv_restore
;
; RV32I-SR-LABEL: callee_saved1:
-; RV32I-SR: call t0, __riscv_save_11
-; RV32I-SR: tail __riscv_restore_11
+; RV32I-SR: call t0, __riscv_save_10
+; RV32I-SR: tail __riscv_restore_10
;
; RV64I-SR-LABEL: callee_saved1:
-; RV64I-SR: call t0, __riscv_save_11
-; RV64I-SR: tail __riscv_restore_11
+; RV64I-SR: call t0, __riscv_save_10
+; RV64I-SR: tail __riscv_restore_10
;
; RV32I-FP-SR-LABEL: callee_saved1:
-; RV32I-FP-SR: call t0, __riscv_save_11
-; RV32I-FP-SR: tail __riscv_restore_11
+; RV32I-FP-SR: call t0, __riscv_save_10
+; RV32I-FP-SR: tail __riscv_restore_10
;
; RV64I-FP-SR-LABEL: callee_saved1:
-; RV64I-FP-SR: call t0, __riscv_save_11
-; RV64I-FP-SR: tail __riscv_restore_11
+; RV64I-FP-SR: call t0, __riscv_save_10
+; RV64I-FP-SR: tail __riscv_restore_10
%val = load [24 x i32], ptr @var1
store volatile [24 x i32] %val, ptr @var1
ret void
@@ -227,20 +227,20 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind {
; RV64I-NOT: tail __riscv_restore
;
; RV32I-SR-LABEL: many_args:
-; RV32I-SR: call t0, __riscv_save_5
-; RV32I-SR: tail __riscv_restore_5
+; RV32I-SR: call t0, __riscv_save_4
+; RV32I-SR: tail __riscv_restore_4
;
; RV64I-SR-LABEL: many_args:
-; RV64I-SR: call t0, __riscv_save_5
-; RV64I-SR: tail __riscv_restore_5
+; RV64I-SR: call t0, __riscv_save_4
+; RV64I-SR: tail __riscv_restore_4
;
; RV32I-FP-SR-LABEL: many_args:
-; RV32I-FP-SR: call t0, __riscv_save_5
-; RV32I-FP-SR: tail __riscv_restore_5
+; RV32I-FP-SR: call t0, __riscv_save_4
+; RV32I-FP-SR: tail __riscv_restore_4
;
; RV64I-FP-SR-LABEL: many_args:
-; RV64I-FP-SR: call t0, __riscv_save_5
-; RV64I-FP-SR: tail __riscv_restore_5
+; RV64I-FP-SR: call t0, __riscv_save_4
+; RV64I-FP-SR: tail __riscv_restore_4
entry:
%val = load [18 x i32], ptr @var0
store volatile [18 x i32] %val, ptr @var0
diff --git a/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
index 529d1d3984bec..7904bbcf6f0fa 100644
--- a/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
+++ b/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
@@ -31,84 +31,82 @@ define void @callee() {
; RV32IXQCCMP-NEXT: .cfi_offset s9, -44
; RV32IXQCCMP-NEXT: .cfi_offset s10, -48
; RV32IXQCCMP-NEXT: .cfi_offset s11, -52
-; RV32IXQCCMP-NEXT: lui t0, %hi(var)
-; RV32IXQCCMP-NEXT: lw a0, %lo(var)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var+4)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var+8)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var+12)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: addi a5, t0, %lo(var)
-; RV32IXQCCMP-NEXT: lw a0, 16(a5)
-; RV32IXQCCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 20(a5)
-; RV32IXQCCMP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw t4, 24(a5)
-; RV32IXQCCMP-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-NEXT: lw t6, 32(a5)
-; RV32IXQCCMP-NEXT: lw s2, 36(a5)
-; RV32IXQCCMP-NEXT: lw s3, 40(a5)
-; RV32IXQCCMP-NEXT: lw s4, 44(a5)
-; RV32IXQCCMP-NEXT: lw s5, 48(a5)
-; RV32IXQCCMP-NEXT: lw s6, 52(a5)
-; RV32IXQCCMP-NEXT: lw s7, 56(a5)
-; RV32IXQCCMP-NEXT: lw s8, 60(a5)
-; RV32IXQCCMP-NEXT: lw s9, 64(a5)
-; RV32IXQCCMP-NEXT: lw s10, 68(a5)
-; RV32IXQCCMP-NEXT: lw s11, 72(a5)
-; RV32IXQCCMP-NEXT: lw ra, 76(a5)
-; RV32IXQCCMP-NEXT: lw s1, 80(a5)
-; RV32IXQCCMP-NEXT: lw t3, 84(a5)
-; RV32IXQCCMP-NEXT: lw t2, 88(a5)
-; RV32IXQCCMP-NEXT: lw t1, 92(a5)
-; RV32IXQCCMP-NEXT: lw a7, 112(a5)
-; RV32IXQCCMP-NEXT: lw s0, 116(a5)
-; RV32IXQCCMP-NEXT: lw a3, 120(a5)
-; RV32IXQCCMP-NEXT: lw a0, 124(a5)
-; RV32IXQCCMP-NEXT: lw a6, 96(a5)
-; RV32IXQCCMP-NEXT: lw a4, 100(a5)
-; RV32IXQCCMP-NEXT: lw a2, 104(a5)
-; RV32IXQCCMP-NEXT: lw a1, 108(a5)
-; RV32IXQCCMP-NEXT: sw a0, 124(a5)
-; RV32IXQCCMP-NEXT: sw a3, 120(a5)
-; RV32IXQCCMP-NEXT: sw s0, 116(a5)
-; RV32IXQCCMP-NEXT: sw a7, 112(a5)
-; RV32IXQCCMP-NEXT: sw a1, 108(a5)
-; RV32IXQCCMP-NEXT: sw a2, 104(a5)
-; RV32IXQCCMP-NEXT: sw a4, 100(a5)
-; RV32IXQCCMP-NEXT: sw a6, 96(a5)
-; RV32IXQCCMP-NEXT: sw t1, 92(a5)
-; RV32IXQCCMP-NEXT: sw t2, 88(a5)
-; RV32IXQCCMP-NEXT: sw t3, 84(a5)
-; RV32IXQCCMP-NEXT: sw s1, 80(a5)
-; RV32IXQCCMP-NEXT: sw ra, 76(a5)
-; RV32IXQCCMP-NEXT: sw s11, 72(a5)
-; RV32IXQCCMP-NEXT: sw s10, 68(a5)
-; RV32IXQCCMP-NEXT: sw s9, 64(a5)
-; RV32IXQCCMP-NEXT: sw s8, 60(a5)
-; RV32IXQCCMP-NEXT: sw s7, 56(a5)
-; RV32IXQCCMP-NEXT: sw s6, 52(a5)
-; RV32IXQCCMP-NEXT: sw s5, 48(a5)
-; RV32IXQCCMP-NEXT: sw s4, 44(a5)
-; RV32IXQCCMP-NEXT: sw s3, 40(a5)
-; RV32IXQCCMP-NEXT: sw s2, 36(a5)
-; RV32IXQCCMP-NEXT: sw t6, 32(a5)
-; RV32IXQCCMP-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-NEXT: sw t4, 24(a5)
-; RV32IXQCCMP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 20(a5)
-; RV32IXQCCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 16(a5)
-; RV32IXQCCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var+12)(t0)
-; RV32IXQCCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var+8)(t0)
-; RV32IXQCCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var+4)(t0)
-; RV32IXQCCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var)(t0)
+; RV32IXQCCMP-NEXT: lui a0, %hi(var)
+; RV32IXQCCMP-NEXT: addi a0, a0, %lo(var)
+; RV32IXQCCMP-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 4(a0)
+; RV32IXQCCMP-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 8(a0)
+; RV32IXQCCMP-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 12(a0)
+; RV32IXQCCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 16(a0)
+; RV32IXQCCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw t3, 20(a0)
+; RV32IXQCCMP-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-NEXT: lw t6, 32(a0)
+; RV32IXQCCMP-NEXT: lw s2, 36(a0)
+; RV32IXQCCMP-NEXT: lw s3, 40(a0)
+; RV32IXQCCMP-NEXT: lw s4, 44(a0)
+; RV32IXQCCMP-NEXT: lw s5, 48(a0)
+; RV32IXQCCMP-NEXT: lw s6, 52(a0)
+; RV32IXQCCMP-NEXT: lw s7, 56(a0)
+; RV32IXQCCMP-NEXT: lw s8, 60(a0)
+; RV32IXQCCMP-NEXT: lw s9, 64(a0)
+; RV32IXQCCMP-NEXT: lw s10, 68(a0)
+; RV32IXQCCMP-NEXT: lw s11, 72(a0)
+; RV32IXQCCMP-NEXT: lw ra, 76(a0)
+; RV32IXQCCMP-NEXT: lw t2, 80(a0)
+; RV32IXQCCMP-NEXT: lw s0, 84(a0)
+; RV32IXQCCMP-NEXT: lw s1, 88(a0)
+; RV32IXQCCMP-NEXT: lw t1, 92(a0)
+; RV32IXQCCMP-NEXT: lw t0, 112(a0)
+; RV32IXQCCMP-NEXT: lw a5, 116(a0)
+; RV32IXQCCMP-NEXT: lw a3, 120(a0)
+; RV32IXQCCMP-NEXT: lw a1, 124(a0)
+; RV32IXQCCMP-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-NEXT: lw a6, 100(a0)
+; RV32IXQCCMP-NEXT: lw a4, 104(a0)
+; RV32IXQCCMP-NEXT: lw a2, 108(a0)
+; RV32IXQCCMP-NEXT: sw a1, 124(a0)
+; RV32IXQCCMP-NEXT: sw a3, 120(a0)
+; RV32IXQCCMP-NEXT: sw a5, 116(a0)
+; RV32IXQCCMP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-NEXT: sw a2, 108(a0)
+; RV32IXQCCMP-NEXT: sw a4, 104(a0)
+; RV32IXQCCMP-NEXT: sw a6, 100(a0)
+; RV32IXQCCMP-NEXT: sw a7, 96(a0)
+; RV32IXQCCMP-NEXT: sw t1, 92(a0)
+; RV32IXQCCMP-NEXT: sw s1, 88(a0)
+; RV32IXQCCMP-NEXT: sw s0, 84(a0)
+; RV32IXQCCMP-NEXT: sw t2, 80(a0)
+; RV32IXQCCMP-NEXT: sw ra, 76(a0)
+; RV32IXQCCMP-NEXT: sw s11, 72(a0)
+; RV32IXQCCMP-NEXT: sw s10, 68(a0)
+; RV32IXQCCMP-NEXT: sw s9, 64(a0)
+; RV32IXQCCMP-NEXT: sw s8, 60(a0)
+; RV32IXQCCMP-NEXT: sw s7, 56(a0)
+; RV32IXQCCMP-NEXT: sw s6, 52(a0)
+; RV32IXQCCMP-NEXT: sw s5, 48(a0)
+; RV32IXQCCMP-NEXT: sw s4, 44(a0)
+; RV32IXQCCMP-NEXT: sw s3, 40(a0)
+; RV32IXQCCMP-NEXT: sw s2, 36(a0)
+; RV32IXQCCMP-NEXT: sw t6, 32(a0)
+; RV32IXQCCMP-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 16(a0)
+; RV32IXQCCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 12(a0)
+; RV32IXQCCMP-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 8(a0)
+; RV32IXQCCMP-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 4(a0)
+; RV32IXQCCMP-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 0(a0)
; RV32IXQCCMP-NEXT: qc.cm.popret {ra, s0-s11}, 96
;
; RV32IXQCCMP-WITH-FP-LABEL: callee:
@@ -129,86 +127,84 @@ define void @callee() {
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset s10, -48
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset s11, -52
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
-; RV32IXQCCMP-WITH-FP-NEXT: lui t1, %hi(var)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: addi a5, t1, %lo(var)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 16(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -84(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 20(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -88(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 24(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -92(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t6, 32(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s2, 36(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s3, 40(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s4, 44(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s5, 48(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s6, 52(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s7, 56(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s8, 60(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s9, 64(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s10, 68(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s11, 72(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw ra, 76(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t4, 80(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t3, 84(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t2, 88(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s1, 92(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t0, 112(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a4, 116(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a3, 120(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 124(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a7, 96(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a6, 100(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a2, 104(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a1, 108(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 124(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a3, 120(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a4, 116(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t0, 112(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a1, 108(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a2, 104(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a6, 100(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a7, 96(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s1, 92(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t2, 88(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t3, 84(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t4, 80(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw ra, 76(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s11, 72(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s10, 68(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s9, 64(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s8, 60(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s7, 56(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s6, 52(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s5, 48(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s4, 44(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s3, 40(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s2, 36(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t6, 32(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -92(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 24(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -88(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 20(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -84(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 16(a5)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(t1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var)(t1)
+; RV32IXQCCMP-WITH-FP-NEXT: lui a0, %hi(var)
+; RV32IXQCCMP-WITH-FP-NEXT: addi a0, a0, %lo(var)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, -68(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, 4(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, -72(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, 8(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, -76(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, 12(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, -80(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, 16(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, -84(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, 20(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, -88(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-WITH-FP-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t6, 32(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s2, 36(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s3, 40(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s4, 44(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s5, 48(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s6, 52(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s7, 56(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s8, 60(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s9, 64(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s10, 68(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s11, 72(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw ra, 76(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s1, 80(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t3, 84(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t2, 88(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t1, 92(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t0, 112(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a6, 116(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a4, 120(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, 124(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a5, 100(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a3, 104(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a2, 108(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, 124(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a4, 120(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a6, 116(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a2, 108(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a3, 104(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a5, 100(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a7, 96(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t1, 92(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t2, 88(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t3, 84(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s1, 80(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw ra, 76(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s11, 72(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s10, 68(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s9, 64(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s8, 60(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s7, 56(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s6, 52(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s5, 48(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s4, 44(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s3, 40(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s2, 36(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t6, 32(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, -88(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, 20(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, -84(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, 16(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, -80(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, 12(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, -76(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, 8(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, -72(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, 4(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a1, -68(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-WITH-FP-NEXT: sw a1, 0(a0)
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa sp, 96
; RV32IXQCCMP-WITH-FP-NEXT: qc.cm.popret {ra, s0-s11}, 96
;
@@ -229,84 +225,82 @@ define void @callee() {
; RV64IXQCCMP-NEXT: .cfi_offset s9, -88
; RV64IXQCCMP-NEXT: .cfi_offset s10, -96
; RV64IXQCCMP-NEXT: .cfi_offset s11, -104
-; RV64IXQCCMP-NEXT: lui t0, %hi(var)
-; RV64IXQCCMP-NEXT: lw a0, %lo(var)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var+4)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var+8)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var+12)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: addi a5, t0, %lo(var)
-; RV64IXQCCMP-NEXT: lw a0, 16(a5)
-; RV64IXQCCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 20(a5)
-; RV64IXQCCMP-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw t4, 24(a5)
-; RV64IXQCCMP-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-NEXT: lw t6, 32(a5)
-; RV64IXQCCMP-NEXT: lw s2, 36(a5)
-; RV64IXQCCMP-NEXT: lw s3, 40(a5)
-; RV64IXQCCMP-NEXT: lw s4, 44(a5)
-; RV64IXQCCMP-NEXT: lw s5, 48(a5)
-; RV64IXQCCMP-NEXT: lw s6, 52(a5)
-; RV64IXQCCMP-NEXT: lw s7, 56(a5)
-; RV64IXQCCMP-NEXT: lw s8, 60(a5)
-; RV64IXQCCMP-NEXT: lw s9, 64(a5)
-; RV64IXQCCMP-NEXT: lw s10, 68(a5)
-; RV64IXQCCMP-NEXT: lw s11, 72(a5)
-; RV64IXQCCMP-NEXT: lw ra, 76(a5)
-; RV64IXQCCMP-NEXT: lw s1, 80(a5)
-; RV64IXQCCMP-NEXT: lw t3, 84(a5)
-; RV64IXQCCMP-NEXT: lw t2, 88(a5)
-; RV64IXQCCMP-NEXT: lw t1, 92(a5)
-; RV64IXQCCMP-NEXT: lw a7, 112(a5)
-; RV64IXQCCMP-NEXT: lw s0, 116(a5)
-; RV64IXQCCMP-NEXT: lw a3, 120(a5)
-; RV64IXQCCMP-NEXT: lw a0, 124(a5)
-; RV64IXQCCMP-NEXT: lw a6, 96(a5)
-; RV64IXQCCMP-NEXT: lw a4, 100(a5)
-; RV64IXQCCMP-NEXT: lw a2, 104(a5)
-; RV64IXQCCMP-NEXT: lw a1, 108(a5)
-; RV64IXQCCMP-NEXT: sw a0, 124(a5)
-; RV64IXQCCMP-NEXT: sw a3, 120(a5)
-; RV64IXQCCMP-NEXT: sw s0, 116(a5)
-; RV64IXQCCMP-NEXT: sw a7, 112(a5)
-; RV64IXQCCMP-NEXT: sw a1, 108(a5)
-; RV64IXQCCMP-NEXT: sw a2, 104(a5)
-; RV64IXQCCMP-NEXT: sw a4, 100(a5)
-; RV64IXQCCMP-NEXT: sw a6, 96(a5)
-; RV64IXQCCMP-NEXT: sw t1, 92(a5)
-; RV64IXQCCMP-NEXT: sw t2, 88(a5)
-; RV64IXQCCMP-NEXT: sw t3, 84(a5)
-; RV64IXQCCMP-NEXT: sw s1, 80(a5)
-; RV64IXQCCMP-NEXT: sw ra, 76(a5)
-; RV64IXQCCMP-NEXT: sw s11, 72(a5)
-; RV64IXQCCMP-NEXT: sw s10, 68(a5)
-; RV64IXQCCMP-NEXT: sw s9, 64(a5)
-; RV64IXQCCMP-NEXT: sw s8, 60(a5)
-; RV64IXQCCMP-NEXT: sw s7, 56(a5)
-; RV64IXQCCMP-NEXT: sw s6, 52(a5)
-; RV64IXQCCMP-NEXT: sw s5, 48(a5)
-; RV64IXQCCMP-NEXT: sw s4, 44(a5)
-; RV64IXQCCMP-NEXT: sw s3, 40(a5)
-; RV64IXQCCMP-NEXT: sw s2, 36(a5)
-; RV64IXQCCMP-NEXT: sw t6, 32(a5)
-; RV64IXQCCMP-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-NEXT: sw t4, 24(a5)
-; RV64IXQCCMP-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 20(a5)
-; RV64IXQCCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 16(a5)
-; RV64IXQCCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var+12)(t0)
-; RV64IXQCCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var+8)(t0)
-; RV64IXQCCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var+4)(t0)
-; RV64IXQCCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var)(t0)
+; RV64IXQCCMP-NEXT: lui a0, %hi(var)
+; RV64IXQCCMP-NEXT: addi a0, a0, %lo(var)
+; RV64IXQCCMP-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-NEXT: sd a1, 40(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 4(a0)
+; RV64IXQCCMP-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 8(a0)
+; RV64IXQCCMP-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 12(a0)
+; RV64IXQCCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 16(a0)
+; RV64IXQCCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw t3, 20(a0)
+; RV64IXQCCMP-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-NEXT: lw t6, 32(a0)
+; RV64IXQCCMP-NEXT: lw s2, 36(a0)
+; RV64IXQCCMP-NEXT: lw s3, 40(a0)
+; RV64IXQCCMP-NEXT: lw s4, 44(a0)
+; RV64IXQCCMP-NEXT: lw s5, 48(a0)
+; RV64IXQCCMP-NEXT: lw s6, 52(a0)
+; RV64IXQCCMP-NEXT: lw s7, 56(a0)
+; RV64IXQCCMP-NEXT: lw s8, 60(a0)
+; RV64IXQCCMP-NEXT: lw s9, 64(a0)
+; RV64IXQCCMP-NEXT: lw s10, 68(a0)
+; RV64IXQCCMP-NEXT: lw s11, 72(a0)
+; RV64IXQCCMP-NEXT: lw ra, 76(a0)
+; RV64IXQCCMP-NEXT: lw t2, 80(a0)
+; RV64IXQCCMP-NEXT: lw s0, 84(a0)
+; RV64IXQCCMP-NEXT: lw s1, 88(a0)
+; RV64IXQCCMP-NEXT: lw t1, 92(a0)
+; RV64IXQCCMP-NEXT: lw t0, 112(a0)
+; RV64IXQCCMP-NEXT: lw a5, 116(a0)
+; RV64IXQCCMP-NEXT: lw a3, 120(a0)
+; RV64IXQCCMP-NEXT: lw a1, 124(a0)
+; RV64IXQCCMP-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-NEXT: lw a6, 100(a0)
+; RV64IXQCCMP-NEXT: lw a4, 104(a0)
+; RV64IXQCCMP-NEXT: lw a2, 108(a0)
+; RV64IXQCCMP-NEXT: sw a1, 124(a0)
+; RV64IXQCCMP-NEXT: sw a3, 120(a0)
+; RV64IXQCCMP-NEXT: sw a5, 116(a0)
+; RV64IXQCCMP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-NEXT: sw a2, 108(a0)
+; RV64IXQCCMP-NEXT: sw a4, 104(a0)
+; RV64IXQCCMP-NEXT: sw a6, 100(a0)
+; RV64IXQCCMP-NEXT: sw a7, 96(a0)
+; RV64IXQCCMP-NEXT: sw t1, 92(a0)
+; RV64IXQCCMP-NEXT: sw s1, 88(a0)
+; RV64IXQCCMP-NEXT: sw s0, 84(a0)
+; RV64IXQCCMP-NEXT: sw t2, 80(a0)
+; RV64IXQCCMP-NEXT: sw ra, 76(a0)
+; RV64IXQCCMP-NEXT: sw s11, 72(a0)
+; RV64IXQCCMP-NEXT: sw s10, 68(a0)
+; RV64IXQCCMP-NEXT: sw s9, 64(a0)
+; RV64IXQCCMP-NEXT: sw s8, 60(a0)
+; RV64IXQCCMP-NEXT: sw s7, 56(a0)
+; RV64IXQCCMP-NEXT: sw s6, 52(a0)
+; RV64IXQCCMP-NEXT: sw s5, 48(a0)
+; RV64IXQCCMP-NEXT: sw s4, 44(a0)
+; RV64IXQCCMP-NEXT: sw s3, 40(a0)
+; RV64IXQCCMP-NEXT: sw s2, 36(a0)
+; RV64IXQCCMP-NEXT: sw t6, 32(a0)
+; RV64IXQCCMP-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 16(a0)
+; RV64IXQCCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 12(a0)
+; RV64IXQCCMP-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 8(a0)
+; RV64IXQCCMP-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 4(a0)
+; RV64IXQCCMP-NEXT: ld a1, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 0(a0)
; RV64IXQCCMP-NEXT: qc.cm.popret {ra, s0-s11}, 160
;
; RV64IXQCCMP-WITH-FP-LABEL: callee:
@@ -326,92 +320,86 @@ define void @callee() {
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s9, -88
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s10, -96
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s11, -104
-; RV64IXQCCMP-WITH-FP-NEXT: addi sp, sp, -16
-; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 176
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
-; RV64IXQCCMP-WITH-FP-NEXT: lui t1, %hi(var)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: addi a5, t1, %lo(var)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 16(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 20(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 24(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -168(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t6, 32(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s2, 36(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s3, 40(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s4, 44(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s5, 48(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s6, 52(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s7, 56(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s8, 60(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s9, 64(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s10, 68(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s11, 72(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw ra, 76(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t4, 80(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t3, 84(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t2, 88(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s1, 92(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t0, 112(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a4, 116(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a3, 120(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 124(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a7, 96(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a6, 100(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a2, 104(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a1, 108(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 124(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw a3, 120(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw a4, 116(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t0, 112(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw a1, 108(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw a2, 104(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw a6, 100(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw a7, 96(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s1, 92(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t2, 88(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t3, 84(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t4, 80(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw ra, 76(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s11, 72(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s10, 68(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s9, 64(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s8, 60(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s7, 56(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s6, 52(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s5, 48(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s4, 44(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s3, 40(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s2, 36(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t6, 32(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -168(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 24(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 20(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 16(a5)
-; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var)(t1)
-; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa sp, 176
-; RV64IXQCCMP-WITH-FP-NEXT: addi sp, sp, 16
-; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 160
+; RV64IXQCCMP-WITH-FP-NEXT: lui a0, %hi(var)
+; RV64IXQCCMP-WITH-FP-NEXT: addi a0, a0, %lo(var)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sd a1, -120(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-WITH-FP-NEXT: lw a1, 4(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sd a1, -128(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-WITH-FP-NEXT: lw a1, 8(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sd a1, -136(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-WITH-FP-NEXT: lw a1, 12(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sd a1, -144(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-WITH-FP-NEXT: lw a1, 16(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sd a1, -152(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-WITH-FP-NEXT: lw a1, 20(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sd a1, -160(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-WITH-FP-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t6, 32(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s2, 36(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s3, 40(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s4, 44(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s5, 48(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s6, 52(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s7, 56(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s8, 60(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s9, 64(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s10, 68(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s11, 72(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw ra, 76(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s1, 80(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t3, 84(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t2, 88(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t1, 92(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t0, 112(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a6, 116(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a4, 120(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a1, 124(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a5, 100(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a3, 104(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a2, 108(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a1, 124(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a4, 120(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a6, 116(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a2, 108(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a3, 104(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a5, 100(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a7, 96(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t1, 92(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t2, 88(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t3, 84(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s1, 80(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw ra, 76(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s11, 72(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s10, 68(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s9, 64(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s8, 60(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s7, 56(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s6, 52(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s5, 48(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s4, 44(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s3, 40(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s2, 36(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t6, 32(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: ld a1, -160(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT: sw a1, 20(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: ld a1, -152(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT: sw a1, 16(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: ld a1, -144(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT: sw a1, 12(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: ld a1, -136(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT: sw a1, 8(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: ld a1, -128(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT: sw a1, 4(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: ld a1, -120(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-WITH-FP-NEXT: sw a1, 0(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa sp, 160
; RV64IXQCCMP-WITH-FP-NEXT: qc.cm.popret {ra, s0-s11}, 160
%val = load [32 x i32], ptr @var
store volatile [32 x i32] %val, ptr @var
@@ -442,116 +430,114 @@ define void @caller() {
; RV32IXQCCMP-NEXT: addi sp, sp, -48
; RV32IXQCCMP-NEXT: .cfi_def_cfa_offset 160
; RV32IXQCCMP-NEXT: lui s0, %hi(var)
-; RV32IXQCCMP-NEXT: lw a0, %lo(var)(s0)
+; RV32IXQCCMP-NEXT: addi s0, s0, %lo(var)
+; RV32IXQCCMP-NEXT: lw a0, 0(s0)
; RV32IXQCCMP-NEXT: sw a0, 92(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var+4)(s0)
+; RV32IXQCCMP-NEXT: lw a0, 4(s0)
; RV32IXQCCMP-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var+8)(s0)
+; RV32IXQCCMP-NEXT: lw a0, 8(s0)
; RV32IXQCCMP-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var+12)(s0)
+; RV32IXQCCMP-NEXT: lw a0, 12(s0)
; RV32IXQCCMP-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: addi s1, s0, %lo(var)
-; RV32IXQCCMP-NEXT: lw a0, 16(s1)
+; RV32IXQCCMP-NEXT: lw a0, 16(s0)
; RV32IXQCCMP-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 20(s1)
+; RV32IXQCCMP-NEXT: lw a0, 20(s0)
; RV32IXQCCMP-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 24(s1)
+; RV32IXQCCMP-NEXT: lw a0, 24(s0)
; RV32IXQCCMP-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 28(s1)
+; RV32IXQCCMP-NEXT: lw a0, 28(s0)
; RV32IXQCCMP-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 32(s1)
+; RV32IXQCCMP-NEXT: lw a0, 32(s0)
; RV32IXQCCMP-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 36(s1)
+; RV32IXQCCMP-NEXT: lw a0, 36(s0)
; RV32IXQCCMP-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 40(s1)
+; RV32IXQCCMP-NEXT: lw a0, 40(s0)
; RV32IXQCCMP-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 44(s1)
+; RV32IXQCCMP-NEXT: lw a0, 44(s0)
; RV32IXQCCMP-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 48(s1)
+; RV32IXQCCMP-NEXT: lw a0, 48(s0)
; RV32IXQCCMP-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 52(s1)
+; RV32IXQCCMP-NEXT: lw a0, 52(s0)
; RV32IXQCCMP-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 56(s1)
+; RV32IXQCCMP-NEXT: lw a0, 56(s0)
; RV32IXQCCMP-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 60(s1)
+; RV32IXQCCMP-NEXT: lw a0, 60(s0)
; RV32IXQCCMP-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 64(s1)
+; RV32IXQCCMP-NEXT: lw a0, 64(s0)
; RV32IXQCCMP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 68(s1)
+; RV32IXQCCMP-NEXT: lw a0, 68(s0)
; RV32IXQCCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 72(s1)
+; RV32IXQCCMP-NEXT: lw a0, 72(s0)
; RV32IXQCCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 76(s1)
+; RV32IXQCCMP-NEXT: lw a0, 76(s0)
; RV32IXQCCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 80(s1)
+; RV32IXQCCMP-NEXT: lw a0, 80(s0)
; RV32IXQCCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 84(s1)
-; RV32IXQCCMP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw s4, 88(s1)
-; RV32IXQCCMP-NEXT: lw s5, 92(s1)
-; RV32IXQCCMP-NEXT: lw s6, 96(s1)
-; RV32IXQCCMP-NEXT: lw s7, 100(s1)
-; RV32IXQCCMP-NEXT: lw s8, 104(s1)
-; RV32IXQCCMP-NEXT: lw s9, 108(s1)
-; RV32IXQCCMP-NEXT: lw s10, 112(s1)
-; RV32IXQCCMP-NEXT: lw s11, 116(s1)
-; RV32IXQCCMP-NEXT: lw s2, 120(s1)
-; RV32IXQCCMP-NEXT: lw s3, 124(s1)
+; RV32IXQCCMP-NEXT: lw s1, 84(s0)
+; RV32IXQCCMP-NEXT: lw s2, 88(s0)
+; RV32IXQCCMP-NEXT: lw s3, 92(s0)
+; RV32IXQCCMP-NEXT: lw s4, 96(s0)
+; RV32IXQCCMP-NEXT: lw s5, 100(s0)
+; RV32IXQCCMP-NEXT: lw s6, 104(s0)
+; RV32IXQCCMP-NEXT: lw s7, 108(s0)
+; RV32IXQCCMP-NEXT: lw s8, 112(s0)
+; RV32IXQCCMP-NEXT: lw s9, 116(s0)
+; RV32IXQCCMP-NEXT: lw s10, 120(s0)
+; RV32IXQCCMP-NEXT: lw s11, 124(s0)
; RV32IXQCCMP-NEXT: call callee
-; RV32IXQCCMP-NEXT: sw s3, 124(s1)
-; RV32IXQCCMP-NEXT: sw s2, 120(s1)
-; RV32IXQCCMP-NEXT: sw s11, 116(s1)
-; RV32IXQCCMP-NEXT: sw s10, 112(s1)
-; RV32IXQCCMP-NEXT: sw s9, 108(s1)
-; RV32IXQCCMP-NEXT: sw s8, 104(s1)
-; RV32IXQCCMP-NEXT: sw s7, 100(s1)
-; RV32IXQCCMP-NEXT: sw s6, 96(s1)
-; RV32IXQCCMP-NEXT: sw s5, 92(s1)
-; RV32IXQCCMP-NEXT: sw s4, 88(s1)
-; RV32IXQCCMP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 84(s1)
+; RV32IXQCCMP-NEXT: sw s11, 124(s0)
+; RV32IXQCCMP-NEXT: sw s10, 120(s0)
+; RV32IXQCCMP-NEXT: sw s9, 116(s0)
+; RV32IXQCCMP-NEXT: sw s8, 112(s0)
+; RV32IXQCCMP-NEXT: sw s7, 108(s0)
+; RV32IXQCCMP-NEXT: sw s6, 104(s0)
+; RV32IXQCCMP-NEXT: sw s5, 100(s0)
+; RV32IXQCCMP-NEXT: sw s4, 96(s0)
+; RV32IXQCCMP-NEXT: sw s3, 92(s0)
+; RV32IXQCCMP-NEXT: sw s2, 88(s0)
+; RV32IXQCCMP-NEXT: sw s1, 84(s0)
; RV32IXQCCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 80(s1)
+; RV32IXQCCMP-NEXT: sw a0, 80(s0)
; RV32IXQCCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 76(s1)
+; RV32IXQCCMP-NEXT: sw a0, 76(s0)
; RV32IXQCCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 72(s1)
+; RV32IXQCCMP-NEXT: sw a0, 72(s0)
; RV32IXQCCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 68(s1)
+; RV32IXQCCMP-NEXT: sw a0, 68(s0)
; RV32IXQCCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 64(s1)
+; RV32IXQCCMP-NEXT: sw a0, 64(s0)
; RV32IXQCCMP-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 60(s1)
+; RV32IXQCCMP-NEXT: sw a0, 60(s0)
; RV32IXQCCMP-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 56(s1)
+; RV32IXQCCMP-NEXT: sw a0, 56(s0)
; RV32IXQCCMP-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 52(s1)
+; RV32IXQCCMP-NEXT: sw a0, 52(s0)
; RV32IXQCCMP-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 48(s1)
+; RV32IXQCCMP-NEXT: sw a0, 48(s0)
; RV32IXQCCMP-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 44(s1)
+; RV32IXQCCMP-NEXT: sw a0, 44(s0)
; RV32IXQCCMP-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 40(s1)
+; RV32IXQCCMP-NEXT: sw a0, 40(s0)
; RV32IXQCCMP-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 36(s1)
+; RV32IXQCCMP-NEXT: sw a0, 36(s0)
; RV32IXQCCMP-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 32(s1)
+; RV32IXQCCMP-NEXT: sw a0, 32(s0)
; RV32IXQCCMP-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 28(s1)
+; RV32IXQCCMP-NEXT: sw a0, 28(s0)
; RV32IXQCCMP-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 24(s1)
+; RV32IXQCCMP-NEXT: sw a0, 24(s0)
; RV32IXQCCMP-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 20(s1)
+; RV32IXQCCMP-NEXT: sw a0, 20(s0)
; RV32IXQCCMP-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 16(s1)
+; RV32IXQCCMP-NEXT: sw a0, 16(s0)
; RV32IXQCCMP-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var+12)(s0)
+; RV32IXQCCMP-NEXT: sw a0, 12(s0)
; RV32IXQCCMP-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var+8)(s0)
+; RV32IXQCCMP-NEXT: sw a0, 8(s0)
; RV32IXQCCMP-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var+4)(s0)
+; RV32IXQCCMP-NEXT: sw a0, 4(s0)
; RV32IXQCCMP-NEXT: lw a0, 92(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var)(s0)
+; RV32IXQCCMP-NEXT: sw a0, 0(s0)
; RV32IXQCCMP-NEXT: addi sp, sp, 48
; RV32IXQCCMP-NEXT: .cfi_def_cfa_offset 112
; RV32IXQCCMP-NEXT: qc.cm.popret {ra, s0-s11}, 112
@@ -576,16 +562,16 @@ define void @caller() {
; RV32IXQCCMP-WITH-FP-NEXT: addi sp, sp, -48
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 160
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
-; RV32IXQCCMP-WITH-FP-NEXT: lui s6, %hi(var)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var)(s6)
+; RV32IXQCCMP-WITH-FP-NEXT: lui s1, %hi(var)
+; RV32IXQCCMP-WITH-FP-NEXT: addi s1, s1, %lo(var)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 0(s1)
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(s6)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 4(s1)
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(s6)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 8(s1)
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(s6)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 12(s1)
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: addi s1, s6, %lo(var)
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 16(s1)
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -84(s0) # 4-byte Folded Spill
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 20(s1)
@@ -622,29 +608,27 @@ define void @caller() {
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -148(s0) # 4-byte Folded Spill
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 84(s1)
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -152(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, 88(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -156(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw s8, 92(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s9, 96(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s10, 100(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s11, 104(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s2, 108(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s3, 112(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s4, 116(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s5, 120(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s7, 124(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s4, 88(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s5, 92(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s6, 96(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s7, 100(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s8, 104(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s9, 108(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s10, 112(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s11, 116(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s2, 120(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s3, 124(s1)
; RV32IXQCCMP-WITH-FP-NEXT: call callee
-; RV32IXQCCMP-WITH-FP-NEXT: sw s7, 124(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s5, 120(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s4, 116(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s3, 112(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s2, 108(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s11, 104(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s10, 100(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s9, 96(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s8, 92(s1)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -156(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 88(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s3, 124(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s2, 120(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s11, 116(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s10, 112(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s9, 108(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s8, 104(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s7, 100(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s6, 96(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s5, 92(s1)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s4, 88(s1)
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -152(s0) # 4-byte Folded Reload
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 84(s1)
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -148(s0) # 4-byte Folded Reload
@@ -682,13 +666,13 @@ define void @caller() {
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -84(s0) # 4-byte Folded Reload
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 16(s1)
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(s6)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 12(s1)
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(s6)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 8(s1)
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(s6)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 4(s1)
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var)(s6)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a0, 0(s1)
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa sp, 160
; RV32IXQCCMP-WITH-FP-NEXT: addi sp, sp, 48
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 112
@@ -714,116 +698,114 @@ define void @caller() {
; RV64IXQCCMP-NEXT: addi sp, sp, -128
; RV64IXQCCMP-NEXT: .cfi_def_cfa_offset 288
; RV64IXQCCMP-NEXT: lui s0, %hi(var)
-; RV64IXQCCMP-NEXT: lw a0, %lo(var)(s0)
+; RV64IXQCCMP-NEXT: addi s0, s0, %lo(var)
+; RV64IXQCCMP-NEXT: lw a0, 0(s0)
; RV64IXQCCMP-NEXT: sd a0, 168(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var+4)(s0)
+; RV64IXQCCMP-NEXT: lw a0, 4(s0)
; RV64IXQCCMP-NEXT: sd a0, 160(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var+8)(s0)
+; RV64IXQCCMP-NEXT: lw a0, 8(s0)
; RV64IXQCCMP-NEXT: sd a0, 152(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var+12)(s0)
+; RV64IXQCCMP-NEXT: lw a0, 12(s0)
; RV64IXQCCMP-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: addi s1, s0, %lo(var)
-; RV64IXQCCMP-NEXT: lw a0, 16(s1)
+; RV64IXQCCMP-NEXT: lw a0, 16(s0)
; RV64IXQCCMP-NEXT: sd a0, 136(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 20(s1)
+; RV64IXQCCMP-NEXT: lw a0, 20(s0)
; RV64IXQCCMP-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 24(s1)
+; RV64IXQCCMP-NEXT: lw a0, 24(s0)
; RV64IXQCCMP-NEXT: sd a0, 120(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 28(s1)
+; RV64IXQCCMP-NEXT: lw a0, 28(s0)
; RV64IXQCCMP-NEXT: sd a0, 112(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 32(s1)
+; RV64IXQCCMP-NEXT: lw a0, 32(s0)
; RV64IXQCCMP-NEXT: sd a0, 104(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 36(s1)
+; RV64IXQCCMP-NEXT: lw a0, 36(s0)
; RV64IXQCCMP-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 40(s1)
+; RV64IXQCCMP-NEXT: lw a0, 40(s0)
; RV64IXQCCMP-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 44(s1)
+; RV64IXQCCMP-NEXT: lw a0, 44(s0)
; RV64IXQCCMP-NEXT: sd a0, 80(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 48(s1)
+; RV64IXQCCMP-NEXT: lw a0, 48(s0)
; RV64IXQCCMP-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 52(s1)
+; RV64IXQCCMP-NEXT: lw a0, 52(s0)
; RV64IXQCCMP-NEXT: sd a0, 64(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 56(s1)
+; RV64IXQCCMP-NEXT: lw a0, 56(s0)
; RV64IXQCCMP-NEXT: sd a0, 56(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 60(s1)
+; RV64IXQCCMP-NEXT: lw a0, 60(s0)
; RV64IXQCCMP-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 64(s1)
+; RV64IXQCCMP-NEXT: lw a0, 64(s0)
; RV64IXQCCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 68(s1)
+; RV64IXQCCMP-NEXT: lw a0, 68(s0)
; RV64IXQCCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 72(s1)
+; RV64IXQCCMP-NEXT: lw a0, 72(s0)
; RV64IXQCCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 76(s1)
+; RV64IXQCCMP-NEXT: lw a0, 76(s0)
; RV64IXQCCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 80(s1)
+; RV64IXQCCMP-NEXT: lw a0, 80(s0)
; RV64IXQCCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 84(s1)
-; RV64IXQCCMP-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw s4, 88(s1)
-; RV64IXQCCMP-NEXT: lw s5, 92(s1)
-; RV64IXQCCMP-NEXT: lw s6, 96(s1)
-; RV64IXQCCMP-NEXT: lw s7, 100(s1)
-; RV64IXQCCMP-NEXT: lw s8, 104(s1)
-; RV64IXQCCMP-NEXT: lw s9, 108(s1)
-; RV64IXQCCMP-NEXT: lw s10, 112(s1)
-; RV64IXQCCMP-NEXT: lw s11, 116(s1)
-; RV64IXQCCMP-NEXT: lw s2, 120(s1)
-; RV64IXQCCMP-NEXT: lw s3, 124(s1)
+; RV64IXQCCMP-NEXT: lw s1, 84(s0)
+; RV64IXQCCMP-NEXT: lw s2, 88(s0)
+; RV64IXQCCMP-NEXT: lw s3, 92(s0)
+; RV64IXQCCMP-NEXT: lw s4, 96(s0)
+; RV64IXQCCMP-NEXT: lw s5, 100(s0)
+; RV64IXQCCMP-NEXT: lw s6, 104(s0)
+; RV64IXQCCMP-NEXT: lw s7, 108(s0)
+; RV64IXQCCMP-NEXT: lw s8, 112(s0)
+; RV64IXQCCMP-NEXT: lw s9, 116(s0)
+; RV64IXQCCMP-NEXT: lw s10, 120(s0)
+; RV64IXQCCMP-NEXT: lw s11, 124(s0)
; RV64IXQCCMP-NEXT: call callee
-; RV64IXQCCMP-NEXT: sw s3, 124(s1)
-; RV64IXQCCMP-NEXT: sw s2, 120(s1)
-; RV64IXQCCMP-NEXT: sw s11, 116(s1)
-; RV64IXQCCMP-NEXT: sw s10, 112(s1)
-; RV64IXQCCMP-NEXT: sw s9, 108(s1)
-; RV64IXQCCMP-NEXT: sw s8, 104(s1)
-; RV64IXQCCMP-NEXT: sw s7, 100(s1)
-; RV64IXQCCMP-NEXT: sw s6, 96(s1)
-; RV64IXQCCMP-NEXT: sw s5, 92(s1)
-; RV64IXQCCMP-NEXT: sw s4, 88(s1)
-; RV64IXQCCMP-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 84(s1)
+; RV64IXQCCMP-NEXT: sw s11, 124(s0)
+; RV64IXQCCMP-NEXT: sw s10, 120(s0)
+; RV64IXQCCMP-NEXT: sw s9, 116(s0)
+; RV64IXQCCMP-NEXT: sw s8, 112(s0)
+; RV64IXQCCMP-NEXT: sw s7, 108(s0)
+; RV64IXQCCMP-NEXT: sw s6, 104(s0)
+; RV64IXQCCMP-NEXT: sw s5, 100(s0)
+; RV64IXQCCMP-NEXT: sw s4, 96(s0)
+; RV64IXQCCMP-NEXT: sw s3, 92(s0)
+; RV64IXQCCMP-NEXT: sw s2, 88(s0)
+; RV64IXQCCMP-NEXT: sw s1, 84(s0)
; RV64IXQCCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 80(s1)
+; RV64IXQCCMP-NEXT: sw a0, 80(s0)
; RV64IXQCCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 76(s1)
+; RV64IXQCCMP-NEXT: sw a0, 76(s0)
; RV64IXQCCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 72(s1)
+; RV64IXQCCMP-NEXT: sw a0, 72(s0)
; RV64IXQCCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 68(s1)
+; RV64IXQCCMP-NEXT: sw a0, 68(s0)
; RV64IXQCCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 64(s1)
+; RV64IXQCCMP-NEXT: sw a0, 64(s0)
; RV64IXQCCMP-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 60(s1)
+; RV64IXQCCMP-NEXT: sw a0, 60(s0)
; RV64IXQCCMP-NEXT: ld a0, 56(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 56(s1)
+; RV64IXQCCMP-NEXT: sw a0, 56(s0)
; RV64IXQCCMP-NEXT: ld a0, 64(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 52(s1)
+; RV64IXQCCMP-NEXT: sw a0, 52(s0)
; RV64IXQCCMP-NEXT: ld a0, 72(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 48(s1)
+; RV64IXQCCMP-NEXT: sw a0, 48(s0)
; RV64IXQCCMP-NEXT: ld a0, 80(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 44(s1)
+; RV64IXQCCMP-NEXT: sw a0, 44(s0)
; RV64IXQCCMP-NEXT: ld a0, 88(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 40(s1)
+; RV64IXQCCMP-NEXT: sw a0, 40(s0)
; RV64IXQCCMP-NEXT: ld a0, 96(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 36(s1)
+; RV64IXQCCMP-NEXT: sw a0, 36(s0)
; RV64IXQCCMP-NEXT: ld a0, 104(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 32(s1)
+; RV64IXQCCMP-NEXT: sw a0, 32(s0)
; RV64IXQCCMP-NEXT: ld a0, 112(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 28(s1)
+; RV64IXQCCMP-NEXT: sw a0, 28(s0)
; RV64IXQCCMP-NEXT: ld a0, 120(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 24(s1)
+; RV64IXQCCMP-NEXT: sw a0, 24(s0)
; RV64IXQCCMP-NEXT: ld a0, 128(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 20(s1)
+; RV64IXQCCMP-NEXT: sw a0, 20(s0)
; RV64IXQCCMP-NEXT: ld a0, 136(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 16(s1)
+; RV64IXQCCMP-NEXT: sw a0, 16(s0)
; RV64IXQCCMP-NEXT: ld a0, 144(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var+12)(s0)
+; RV64IXQCCMP-NEXT: sw a0, 12(s0)
; RV64IXQCCMP-NEXT: ld a0, 152(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var+8)(s0)
+; RV64IXQCCMP-NEXT: sw a0, 8(s0)
; RV64IXQCCMP-NEXT: ld a0, 160(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var+4)(s0)
+; RV64IXQCCMP-NEXT: sw a0, 4(s0)
; RV64IXQCCMP-NEXT: ld a0, 168(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var)(s0)
+; RV64IXQCCMP-NEXT: sw a0, 0(s0)
; RV64IXQCCMP-NEXT: addi sp, sp, 128
; RV64IXQCCMP-NEXT: .cfi_def_cfa_offset 160
; RV64IXQCCMP-NEXT: qc.cm.popret {ra, s0-s11}, 160
@@ -845,19 +827,19 @@ define void @caller() {
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s9, -88
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s10, -96
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s11, -104
-; RV64IXQCCMP-WITH-FP-NEXT: addi sp, sp, -144
-; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 304
+; RV64IXQCCMP-WITH-FP-NEXT: addi sp, sp, -128
+; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 288
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
-; RV64IXQCCMP-WITH-FP-NEXT: lui s6, %hi(var)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var)(s6)
+; RV64IXQCCMP-WITH-FP-NEXT: lui s1, %hi(var)
+; RV64IXQCCMP-WITH-FP-NEXT: addi s1, s1, %lo(var)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 0(s1)
; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(s6)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 4(s1)
; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(s6)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 8(s1)
; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(s6)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 12(s1)
; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: addi s1, s6, %lo(var)
; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 16(s1)
; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill
; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 20(s1)
@@ -894,29 +876,27 @@ define void @caller() {
; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -280(s0) # 8-byte Folded Spill
; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 84(s1)
; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -288(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw a0, 88(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -296(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw s8, 92(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s9, 96(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s10, 100(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s11, 104(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s2, 108(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s3, 112(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s4, 116(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s5, 120(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s7, 124(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s4, 88(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s5, 92(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s6, 96(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s7, 100(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s8, 104(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s9, 108(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s10, 112(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s11, 116(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s2, 120(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s3, 124(s1)
; RV64IXQCCMP-WITH-FP-NEXT: call callee
-; RV64IXQCCMP-WITH-FP-NEXT: sw s7, 124(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s5, 120(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s4, 116(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s3, 112(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s2, 108(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s11, 104(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s10, 100(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s9, 96(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s8, 92(s1)
-; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -296(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 88(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s3, 124(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s2, 120(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s11, 116(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s10, 112(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s9, 108(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s8, 104(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s7, 100(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s6, 96(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s5, 92(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s4, 88(s1)
; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -288(s0) # 8-byte Folded Reload
; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 84(s1)
; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -280(s0) # 8-byte Folded Reload
@@ -954,15 +934,15 @@ define void @caller() {
; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload
; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 16(s1)
; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(s6)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 12(s1)
; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(s6)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 8(s1)
; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(s6)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 4(s1)
; RV64IXQCCMP-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-WITH-FP-NEXT: sw a0, %lo(var)(s6)
-; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa sp, 304
-; RV64IXQCCMP-WITH-FP-NEXT: addi sp, sp, 144
+; RV64IXQCCMP-WITH-FP-NEXT: sw a0, 0(s1)
+; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa sp, 288
+; RV64IXQCCMP-WITH-FP-NEXT: addi sp, sp, 128
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 160
; RV64IXQCCMP-WITH-FP-NEXT: qc.cm.popret {ra, s0-s11}, 160
%val = load [32 x i32], ptr @var
diff --git a/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll b/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
index 415511fcfd995..a7e24cecb4f26 100644
--- a/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+++ b/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
@@ -686,7 +686,7 @@ entry:
define i32 @nocompress(i32 signext %size) {
; RV32IXQCCMP-LABEL: nocompress:
; RV32IXQCCMP: # %bb.0: # %entry
-; RV32IXQCCMP-NEXT: qc.cm.pushfp {ra, s0-s8}, -48
+; RV32IXQCCMP-NEXT: qc.cm.pushfp {ra, s0-s7}, -48
; RV32IXQCCMP-NEXT: .cfi_def_cfa_offset 48
; RV32IXQCCMP-NEXT: .cfi_offset ra, -4
; RV32IXQCCMP-NEXT: .cfi_offset s0, -8
@@ -697,30 +697,29 @@ define i32 @nocompress(i32 signext %size) {
; RV32IXQCCMP-NEXT: .cfi_offset s5, -28
; RV32IXQCCMP-NEXT: .cfi_offset s6, -32
; RV32IXQCCMP-NEXT: .cfi_offset s7, -36
-; RV32IXQCCMP-NEXT: .cfi_offset s8, -40
; RV32IXQCCMP-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-NEXT: addi a0, a0, 15
; RV32IXQCCMP-NEXT: andi a0, a0, -16
; RV32IXQCCMP-NEXT: sub s2, sp, a0
; RV32IXQCCMP-NEXT: mv sp, s2
; RV32IXQCCMP-NEXT: lui s1, %hi(var)
-; RV32IXQCCMP-NEXT: lw s3, %lo(var)(s1)
-; RV32IXQCCMP-NEXT: lw s4, %lo(var+4)(s1)
-; RV32IXQCCMP-NEXT: lw s5, %lo(var+8)(s1)
-; RV32IXQCCMP-NEXT: lw s6, %lo(var+12)(s1)
-; RV32IXQCCMP-NEXT: addi s7, s1, %lo(var)
-; RV32IXQCCMP-NEXT: lw s8, 16(s7)
+; RV32IXQCCMP-NEXT: addi s1, s1, %lo(var)
+; RV32IXQCCMP-NEXT: lw s3, 0(s1)
+; RV32IXQCCMP-NEXT: lw s4, 4(s1)
+; RV32IXQCCMP-NEXT: lw s5, 8(s1)
+; RV32IXQCCMP-NEXT: lw s6, 12(s1)
+; RV32IXQCCMP-NEXT: lw s7, 16(s1)
; RV32IXQCCMP-NEXT: mv a0, s2
; RV32IXQCCMP-NEXT: call callee_void
-; RV32IXQCCMP-NEXT: sw s8, 16(s7)
-; RV32IXQCCMP-NEXT: sw s6, %lo(var+12)(s1)
-; RV32IXQCCMP-NEXT: sw s5, %lo(var+8)(s1)
-; RV32IXQCCMP-NEXT: sw s4, %lo(var+4)(s1)
-; RV32IXQCCMP-NEXT: sw s3, %lo(var)(s1)
+; RV32IXQCCMP-NEXT: sw s7, 16(s1)
+; RV32IXQCCMP-NEXT: sw s6, 12(s1)
+; RV32IXQCCMP-NEXT: sw s5, 8(s1)
+; RV32IXQCCMP-NEXT: sw s4, 4(s1)
+; RV32IXQCCMP-NEXT: sw s3, 0(s1)
; RV32IXQCCMP-NEXT: mv a0, s2
; RV32IXQCCMP-NEXT: addi sp, s0, -48
; RV32IXQCCMP-NEXT: .cfi_def_cfa sp, 48
-; RV32IXQCCMP-NEXT: qc.cm.pop {ra, s0-s8}, 48
+; RV32IXQCCMP-NEXT: qc.cm.pop {ra, s0-s7}, 48
; RV32IXQCCMP-NEXT: .cfi_restore ra
; RV32IXQCCMP-NEXT: .cfi_restore s0
; RV32IXQCCMP-NEXT: .cfi_restore s1
@@ -730,13 +729,12 @@ define i32 @nocompress(i32 signext %size) {
; RV32IXQCCMP-NEXT: .cfi_restore s5
; RV32IXQCCMP-NEXT: .cfi_restore s6
; RV32IXQCCMP-NEXT: .cfi_restore s7
-; RV32IXQCCMP-NEXT: .cfi_restore s8
; RV32IXQCCMP-NEXT: .cfi_def_cfa_offset 0
; RV32IXQCCMP-NEXT: tail callee
;
; RV64IXQCCMP-LABEL: nocompress:
; RV64IXQCCMP: # %bb.0: # %entry
-; RV64IXQCCMP-NEXT: qc.cm.pushfp {ra, s0-s8}, -80
+; RV64IXQCCMP-NEXT: qc.cm.pushfp {ra, s0-s7}, -80
; RV64IXQCCMP-NEXT: .cfi_def_cfa_offset 80
; RV64IXQCCMP-NEXT: .cfi_offset ra, -8
; RV64IXQCCMP-NEXT: .cfi_offset s0, -16
@@ -747,7 +745,6 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-NEXT: .cfi_offset s5, -56
; RV64IXQCCMP-NEXT: .cfi_offset s6, -64
; RV64IXQCCMP-NEXT: .cfi_offset s7, -72
-; RV64IXQCCMP-NEXT: .cfi_offset s8, -80
; RV64IXQCCMP-NEXT: .cfi_def_cfa s0, 0
; RV64IXQCCMP-NEXT: slli a0, a0, 32
; RV64IXQCCMP-NEXT: srli a0, a0, 32
@@ -756,23 +753,23 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-NEXT: sub s2, sp, a0
; RV64IXQCCMP-NEXT: mv sp, s2
; RV64IXQCCMP-NEXT: lui s1, %hi(var)
-; RV64IXQCCMP-NEXT: lw s3, %lo(var)(s1)
-; RV64IXQCCMP-NEXT: lw s4, %lo(var+4)(s1)
-; RV64IXQCCMP-NEXT: lw s5, %lo(var+8)(s1)
-; RV64IXQCCMP-NEXT: lw s6, %lo(var+12)(s1)
-; RV64IXQCCMP-NEXT: addi s7, s1, %lo(var)
-; RV64IXQCCMP-NEXT: lw s8, 16(s7)
+; RV64IXQCCMP-NEXT: addi s1, s1, %lo(var)
+; RV64IXQCCMP-NEXT: lw s3, 0(s1)
+; RV64IXQCCMP-NEXT: lw s4, 4(s1)
+; RV64IXQCCMP-NEXT: lw s5, 8(s1)
+; RV64IXQCCMP-NEXT: lw s6, 12(s1)
+; RV64IXQCCMP-NEXT: lw s7, 16(s1)
; RV64IXQCCMP-NEXT: mv a0, s2
; RV64IXQCCMP-NEXT: call callee_void
-; RV64IXQCCMP-NEXT: sw s8, 16(s7)
-; RV64IXQCCMP-NEXT: sw s6, %lo(var+12)(s1)
-; RV64IXQCCMP-NEXT: sw s5, %lo(var+8)(s1)
-; RV64IXQCCMP-NEXT: sw s4, %lo(var+4)(s1)
-; RV64IXQCCMP-NEXT: sw s3, %lo(var)(s1)
+; RV64IXQCCMP-NEXT: sw s7, 16(s1)
+; RV64IXQCCMP-NEXT: sw s6, 12(s1)
+; RV64IXQCCMP-NEXT: sw s5, 8(s1)
+; RV64IXQCCMP-NEXT: sw s4, 4(s1)
+; RV64IXQCCMP-NEXT: sw s3, 0(s1)
; RV64IXQCCMP-NEXT: mv a0, s2
; RV64IXQCCMP-NEXT: addi sp, s0, -80
; RV64IXQCCMP-NEXT: .cfi_def_cfa sp, 80
-; RV64IXQCCMP-NEXT: qc.cm.pop {ra, s0-s8}, 80
+; RV64IXQCCMP-NEXT: qc.cm.pop {ra, s0-s7}, 80
; RV64IXQCCMP-NEXT: .cfi_restore ra
; RV64IXQCCMP-NEXT: .cfi_restore s0
; RV64IXQCCMP-NEXT: .cfi_restore s1
@@ -782,13 +779,12 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-NEXT: .cfi_restore s5
; RV64IXQCCMP-NEXT: .cfi_restore s6
; RV64IXQCCMP-NEXT: .cfi_restore s7
-; RV64IXQCCMP-NEXT: .cfi_restore s8
; RV64IXQCCMP-NEXT: .cfi_def_cfa_offset 0
; RV64IXQCCMP-NEXT: tail callee
;
; RV32IXQCCMP-FP-LABEL: nocompress:
; RV32IXQCCMP-FP: # %bb.0: # %entry
-; RV32IXQCCMP-FP-NEXT: qc.cm.pushfp {ra, s0-s8}, -48
+; RV32IXQCCMP-FP-NEXT: qc.cm.pushfp {ra, s0-s7}, -48
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa_offset 48
; RV32IXQCCMP-FP-NEXT: .cfi_offset ra, -4
; RV32IXQCCMP-FP-NEXT: .cfi_offset s0, -8
@@ -799,30 +795,29 @@ define i32 @nocompress(i32 signext %size) {
; RV32IXQCCMP-FP-NEXT: .cfi_offset s5, -28
; RV32IXQCCMP-FP-NEXT: .cfi_offset s6, -32
; RV32IXQCCMP-FP-NEXT: .cfi_offset s7, -36
-; RV32IXQCCMP-FP-NEXT: .cfi_offset s8, -40
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-FP-NEXT: addi a0, a0, 15
; RV32IXQCCMP-FP-NEXT: andi a0, a0, -16
; RV32IXQCCMP-FP-NEXT: sub s2, sp, a0
; RV32IXQCCMP-FP-NEXT: mv sp, s2
; RV32IXQCCMP-FP-NEXT: lui s1, %hi(var)
-; RV32IXQCCMP-FP-NEXT: lw s3, %lo(var)(s1)
-; RV32IXQCCMP-FP-NEXT: lw s4, %lo(var+4)(s1)
-; RV32IXQCCMP-FP-NEXT: lw s5, %lo(var+8)(s1)
-; RV32IXQCCMP-FP-NEXT: lw s6, %lo(var+12)(s1)
-; RV32IXQCCMP-FP-NEXT: addi s7, s1, %lo(var)
-; RV32IXQCCMP-FP-NEXT: lw s8, 16(s7)
+; RV32IXQCCMP-FP-NEXT: addi s1, s1, %lo(var)
+; RV32IXQCCMP-FP-NEXT: lw s3, 0(s1)
+; RV32IXQCCMP-FP-NEXT: lw s4, 4(s1)
+; RV32IXQCCMP-FP-NEXT: lw s5, 8(s1)
+; RV32IXQCCMP-FP-NEXT: lw s6, 12(s1)
+; RV32IXQCCMP-FP-NEXT: lw s7, 16(s1)
; RV32IXQCCMP-FP-NEXT: mv a0, s2
; RV32IXQCCMP-FP-NEXT: call callee_void
-; RV32IXQCCMP-FP-NEXT: sw s8, 16(s7)
-; RV32IXQCCMP-FP-NEXT: sw s6, %lo(var+12)(s1)
-; RV32IXQCCMP-FP-NEXT: sw s5, %lo(var+8)(s1)
-; RV32IXQCCMP-FP-NEXT: sw s4, %lo(var+4)(s1)
-; RV32IXQCCMP-FP-NEXT: sw s3, %lo(var)(s1)
+; RV32IXQCCMP-FP-NEXT: sw s7, 16(s1)
+; RV32IXQCCMP-FP-NEXT: sw s6, 12(s1)
+; RV32IXQCCMP-FP-NEXT: sw s5, 8(s1)
+; RV32IXQCCMP-FP-NEXT: sw s4, 4(s1)
+; RV32IXQCCMP-FP-NEXT: sw s3, 0(s1)
; RV32IXQCCMP-FP-NEXT: mv a0, s2
; RV32IXQCCMP-FP-NEXT: addi sp, s0, -48
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 48
-; RV32IXQCCMP-FP-NEXT: qc.cm.pop {ra, s0-s8}, 48
+; RV32IXQCCMP-FP-NEXT: qc.cm.pop {ra, s0-s7}, 48
; RV32IXQCCMP-FP-NEXT: .cfi_restore ra
; RV32IXQCCMP-FP-NEXT: .cfi_restore s0
; RV32IXQCCMP-FP-NEXT: .cfi_restore s1
@@ -832,13 +827,12 @@ define i32 @nocompress(i32 signext %size) {
; RV32IXQCCMP-FP-NEXT: .cfi_restore s5
; RV32IXQCCMP-FP-NEXT: .cfi_restore s6
; RV32IXQCCMP-FP-NEXT: .cfi_restore s7
-; RV32IXQCCMP-FP-NEXT: .cfi_restore s8
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa_offset 0
; RV32IXQCCMP-FP-NEXT: tail callee
;
; RV64IXQCCMP-FP-LABEL: nocompress:
; RV64IXQCCMP-FP: # %bb.0: # %entry
-; RV64IXQCCMP-FP-NEXT: qc.cm.pushfp {ra, s0-s8}, -80
+; RV64IXQCCMP-FP-NEXT: qc.cm.pushfp {ra, s0-s7}, -80
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa_offset 80
; RV64IXQCCMP-FP-NEXT: .cfi_offset ra, -8
; RV64IXQCCMP-FP-NEXT: .cfi_offset s0, -16
@@ -849,7 +843,6 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-FP-NEXT: .cfi_offset s5, -56
; RV64IXQCCMP-FP-NEXT: .cfi_offset s6, -64
; RV64IXQCCMP-FP-NEXT: .cfi_offset s7, -72
-; RV64IXQCCMP-FP-NEXT: .cfi_offset s8, -80
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
; RV64IXQCCMP-FP-NEXT: slli a0, a0, 32
; RV64IXQCCMP-FP-NEXT: srli a0, a0, 32
@@ -858,23 +851,23 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-FP-NEXT: sub s2, sp, a0
; RV64IXQCCMP-FP-NEXT: mv sp, s2
; RV64IXQCCMP-FP-NEXT: lui s1, %hi(var)
-; RV64IXQCCMP-FP-NEXT: lw s3, %lo(var)(s1)
-; RV64IXQCCMP-FP-NEXT: lw s4, %lo(var+4)(s1)
-; RV64IXQCCMP-FP-NEXT: lw s5, %lo(var+8)(s1)
-; RV64IXQCCMP-FP-NEXT: lw s6, %lo(var+12)(s1)
-; RV64IXQCCMP-FP-NEXT: addi s7, s1, %lo(var)
-; RV64IXQCCMP-FP-NEXT: lw s8, 16(s7)
+; RV64IXQCCMP-FP-NEXT: addi s1, s1, %lo(var)
+; RV64IXQCCMP-FP-NEXT: lw s3, 0(s1)
+; RV64IXQCCMP-FP-NEXT: lw s4, 4(s1)
+; RV64IXQCCMP-FP-NEXT: lw s5, 8(s1)
+; RV64IXQCCMP-FP-NEXT: lw s6, 12(s1)
+; RV64IXQCCMP-FP-NEXT: lw s7, 16(s1)
; RV64IXQCCMP-FP-NEXT: mv a0, s2
; RV64IXQCCMP-FP-NEXT: call callee_void
-; RV64IXQCCMP-FP-NEXT: sw s8, 16(s7)
-; RV64IXQCCMP-FP-NEXT: sw s6, %lo(var+12)(s1)
-; RV64IXQCCMP-FP-NEXT: sw s5, %lo(var+8)(s1)
-; RV64IXQCCMP-FP-NEXT: sw s4, %lo(var+4)(s1)
-; RV64IXQCCMP-FP-NEXT: sw s3, %lo(var)(s1)
+; RV64IXQCCMP-FP-NEXT: sw s7, 16(s1)
+; RV64IXQCCMP-FP-NEXT: sw s6, 12(s1)
+; RV64IXQCCMP-FP-NEXT: sw s5, 8(s1)
+; RV64IXQCCMP-FP-NEXT: sw s4, 4(s1)
+; RV64IXQCCMP-FP-NEXT: sw s3, 0(s1)
; RV64IXQCCMP-FP-NEXT: mv a0, s2
; RV64IXQCCMP-FP-NEXT: addi sp, s0, -80
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 80
-; RV64IXQCCMP-FP-NEXT: qc.cm.pop {ra, s0-s8}, 80
+; RV64IXQCCMP-FP-NEXT: qc.cm.pop {ra, s0-s7}, 80
; RV64IXQCCMP-FP-NEXT: .cfi_restore ra
; RV64IXQCCMP-FP-NEXT: .cfi_restore s0
; RV64IXQCCMP-FP-NEXT: .cfi_restore s1
@@ -884,13 +877,12 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-FP-NEXT: .cfi_restore s5
; RV64IXQCCMP-FP-NEXT: .cfi_restore s6
; RV64IXQCCMP-FP-NEXT: .cfi_restore s7
-; RV64IXQCCMP-FP-NEXT: .cfi_restore s8
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa_offset 0
; RV64IXQCCMP-FP-NEXT: tail callee
;
; RV32IXQCCMP-SR-LABEL: nocompress:
; RV32IXQCCMP-SR: # %bb.0: # %entry
-; RV32IXQCCMP-SR-NEXT: qc.cm.pushfp {ra, s0-s8}, -48
+; RV32IXQCCMP-SR-NEXT: qc.cm.pushfp {ra, s0-s7}, -48
; RV32IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 48
; RV32IXQCCMP-SR-NEXT: .cfi_offset ra, -4
; RV32IXQCCMP-SR-NEXT: .cfi_offset s0, -8
@@ -901,30 +893,29 @@ define i32 @nocompress(i32 signext %size) {
; RV32IXQCCMP-SR-NEXT: .cfi_offset s5, -28
; RV32IXQCCMP-SR-NEXT: .cfi_offset s6, -32
; RV32IXQCCMP-SR-NEXT: .cfi_offset s7, -36
-; RV32IXQCCMP-SR-NEXT: .cfi_offset s8, -40
; RV32IXQCCMP-SR-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-SR-NEXT: addi a0, a0, 15
; RV32IXQCCMP-SR-NEXT: andi a0, a0, -16
; RV32IXQCCMP-SR-NEXT: sub s2, sp, a0
; RV32IXQCCMP-SR-NEXT: mv sp, s2
; RV32IXQCCMP-SR-NEXT: lui s1, %hi(var)
-; RV32IXQCCMP-SR-NEXT: lw s3, %lo(var)(s1)
-; RV32IXQCCMP-SR-NEXT: lw s4, %lo(var+4)(s1)
-; RV32IXQCCMP-SR-NEXT: lw s5, %lo(var+8)(s1)
-; RV32IXQCCMP-SR-NEXT: lw s6, %lo(var+12)(s1)
-; RV32IXQCCMP-SR-NEXT: addi s7, s1, %lo(var)
-; RV32IXQCCMP-SR-NEXT: lw s8, 16(s7)
+; RV32IXQCCMP-SR-NEXT: addi s1, s1, %lo(var)
+; RV32IXQCCMP-SR-NEXT: lw s3, 0(s1)
+; RV32IXQCCMP-SR-NEXT: lw s4, 4(s1)
+; RV32IXQCCMP-SR-NEXT: lw s5, 8(s1)
+; RV32IXQCCMP-SR-NEXT: lw s6, 12(s1)
+; RV32IXQCCMP-SR-NEXT: lw s7, 16(s1)
; RV32IXQCCMP-SR-NEXT: mv a0, s2
; RV32IXQCCMP-SR-NEXT: call callee_void
-; RV32IXQCCMP-SR-NEXT: sw s8, 16(s7)
-; RV32IXQCCMP-SR-NEXT: sw s6, %lo(var+12)(s1)
-; RV32IXQCCMP-SR-NEXT: sw s5, %lo(var+8)(s1)
-; RV32IXQCCMP-SR-NEXT: sw s4, %lo(var+4)(s1)
-; RV32IXQCCMP-SR-NEXT: sw s3, %lo(var)(s1)
+; RV32IXQCCMP-SR-NEXT: sw s7, 16(s1)
+; RV32IXQCCMP-SR-NEXT: sw s6, 12(s1)
+; RV32IXQCCMP-SR-NEXT: sw s5, 8(s1)
+; RV32IXQCCMP-SR-NEXT: sw s4, 4(s1)
+; RV32IXQCCMP-SR-NEXT: sw s3, 0(s1)
; RV32IXQCCMP-SR-NEXT: mv a0, s2
; RV32IXQCCMP-SR-NEXT: addi sp, s0, -48
; RV32IXQCCMP-SR-NEXT: .cfi_def_cfa sp, 48
-; RV32IXQCCMP-SR-NEXT: qc.cm.pop {ra, s0-s8}, 48
+; RV32IXQCCMP-SR-NEXT: qc.cm.pop {ra, s0-s7}, 48
; RV32IXQCCMP-SR-NEXT: .cfi_restore ra
; RV32IXQCCMP-SR-NEXT: .cfi_restore s0
; RV32IXQCCMP-SR-NEXT: .cfi_restore s1
@@ -934,13 +925,12 @@ define i32 @nocompress(i32 signext %size) {
; RV32IXQCCMP-SR-NEXT: .cfi_restore s5
; RV32IXQCCMP-SR-NEXT: .cfi_restore s6
; RV32IXQCCMP-SR-NEXT: .cfi_restore s7
-; RV32IXQCCMP-SR-NEXT: .cfi_restore s8
; RV32IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 0
; RV32IXQCCMP-SR-NEXT: tail callee
;
; RV64IXQCCMP-SR-LABEL: nocompress:
; RV64IXQCCMP-SR: # %bb.0: # %entry
-; RV64IXQCCMP-SR-NEXT: qc.cm.pushfp {ra, s0-s8}, -80
+; RV64IXQCCMP-SR-NEXT: qc.cm.pushfp {ra, s0-s7}, -80
; RV64IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 80
; RV64IXQCCMP-SR-NEXT: .cfi_offset ra, -8
; RV64IXQCCMP-SR-NEXT: .cfi_offset s0, -16
@@ -951,7 +941,6 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-SR-NEXT: .cfi_offset s5, -56
; RV64IXQCCMP-SR-NEXT: .cfi_offset s6, -64
; RV64IXQCCMP-SR-NEXT: .cfi_offset s7, -72
-; RV64IXQCCMP-SR-NEXT: .cfi_offset s8, -80
; RV64IXQCCMP-SR-NEXT: .cfi_def_cfa s0, 0
; RV64IXQCCMP-SR-NEXT: slli a0, a0, 32
; RV64IXQCCMP-SR-NEXT: srli a0, a0, 32
@@ -960,23 +949,23 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-SR-NEXT: sub s2, sp, a0
; RV64IXQCCMP-SR-NEXT: mv sp, s2
; RV64IXQCCMP-SR-NEXT: lui s1, %hi(var)
-; RV64IXQCCMP-SR-NEXT: lw s3, %lo(var)(s1)
-; RV64IXQCCMP-SR-NEXT: lw s4, %lo(var+4)(s1)
-; RV64IXQCCMP-SR-NEXT: lw s5, %lo(var+8)(s1)
-; RV64IXQCCMP-SR-NEXT: lw s6, %lo(var+12)(s1)
-; RV64IXQCCMP-SR-NEXT: addi s7, s1, %lo(var)
-; RV64IXQCCMP-SR-NEXT: lw s8, 16(s7)
+; RV64IXQCCMP-SR-NEXT: addi s1, s1, %lo(var)
+; RV64IXQCCMP-SR-NEXT: lw s3, 0(s1)
+; RV64IXQCCMP-SR-NEXT: lw s4, 4(s1)
+; RV64IXQCCMP-SR-NEXT: lw s5, 8(s1)
+; RV64IXQCCMP-SR-NEXT: lw s6, 12(s1)
+; RV64IXQCCMP-SR-NEXT: lw s7, 16(s1)
; RV64IXQCCMP-SR-NEXT: mv a0, s2
; RV64IXQCCMP-SR-NEXT: call callee_void
-; RV64IXQCCMP-SR-NEXT: sw s8, 16(s7)
-; RV64IXQCCMP-SR-NEXT: sw s6, %lo(var+12)(s1)
-; RV64IXQCCMP-SR-NEXT: sw s5, %lo(var+8)(s1)
-; RV64IXQCCMP-SR-NEXT: sw s4, %lo(var+4)(s1)
-; RV64IXQCCMP-SR-NEXT: sw s3, %lo(var)(s1)
+; RV64IXQCCMP-SR-NEXT: sw s7, 16(s1)
+; RV64IXQCCMP-SR-NEXT: sw s6, 12(s1)
+; RV64IXQCCMP-SR-NEXT: sw s5, 8(s1)
+; RV64IXQCCMP-SR-NEXT: sw s4, 4(s1)
+; RV64IXQCCMP-SR-NEXT: sw s3, 0(s1)
; RV64IXQCCMP-SR-NEXT: mv a0, s2
; RV64IXQCCMP-SR-NEXT: addi sp, s0, -80
; RV64IXQCCMP-SR-NEXT: .cfi_def_cfa sp, 80
-; RV64IXQCCMP-SR-NEXT: qc.cm.pop {ra, s0-s8}, 80
+; RV64IXQCCMP-SR-NEXT: qc.cm.pop {ra, s0-s7}, 80
; RV64IXQCCMP-SR-NEXT: .cfi_restore ra
; RV64IXQCCMP-SR-NEXT: .cfi_restore s0
; RV64IXQCCMP-SR-NEXT: .cfi_restore s1
@@ -986,7 +975,6 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-SR-NEXT: .cfi_restore s5
; RV64IXQCCMP-SR-NEXT: .cfi_restore s6
; RV64IXQCCMP-SR-NEXT: .cfi_restore s7
-; RV64IXQCCMP-SR-NEXT: .cfi_restore s8
; RV64IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 0
; RV64IXQCCMP-SR-NEXT: tail callee
entry:
@@ -1148,105 +1136,103 @@ define i32 @varargs(ptr %fmt, ...) {
define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV32IXQCCMP-LABEL: many_args:
; RV32IXQCCMP: # %bb.0: # %entry
-; RV32IXQCCMP-NEXT: qc.cm.push {ra, s0-s4}, -32
+; RV32IXQCCMP-NEXT: qc.cm.push {ra, s0-s3}, -32
; RV32IXQCCMP-NEXT: .cfi_def_cfa_offset 32
; RV32IXQCCMP-NEXT: .cfi_offset s0, -8
; RV32IXQCCMP-NEXT: .cfi_offset s1, -12
; RV32IXQCCMP-NEXT: .cfi_offset s2, -16
; RV32IXQCCMP-NEXT: .cfi_offset s3, -20
-; RV32IXQCCMP-NEXT: .cfi_offset s4, -24
; RV32IXQCCMP-NEXT: lui a0, %hi(var0)
-; RV32IXQCCMP-NEXT: lw a6, %lo(var0)(a0)
-; RV32IXQCCMP-NEXT: lw a7, %lo(var0+4)(a0)
-; RV32IXQCCMP-NEXT: lw t0, %lo(var0+8)(a0)
-; RV32IXQCCMP-NEXT: lw t1, %lo(var0+12)(a0)
-; RV32IXQCCMP-NEXT: addi a5, a0, %lo(var0)
-; RV32IXQCCMP-NEXT: lw t2, 16(a5)
-; RV32IXQCCMP-NEXT: lw t3, 20(a5)
-; RV32IXQCCMP-NEXT: lw t4, 24(a5)
-; RV32IXQCCMP-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-NEXT: lw t6, 48(a5)
-; RV32IXQCCMP-NEXT: lw s2, 52(a5)
-; RV32IXQCCMP-NEXT: lw a3, 56(a5)
-; RV32IXQCCMP-NEXT: lw a4, 60(a5)
-; RV32IXQCCMP-NEXT: lw a1, 64(a5)
-; RV32IXQCCMP-NEXT: lw s0, 68(a5)
-; RV32IXQCCMP-NEXT: lw s3, 32(a5)
-; RV32IXQCCMP-NEXT: lw s4, 36(a5)
-; RV32IXQCCMP-NEXT: lw s1, 40(a5)
-; RV32IXQCCMP-NEXT: lw a2, 44(a5)
-; RV32IXQCCMP-NEXT: sw s0, 68(a5)
-; RV32IXQCCMP-NEXT: sw a1, 64(a5)
-; RV32IXQCCMP-NEXT: sw a4, 60(a5)
-; RV32IXQCCMP-NEXT: sw a3, 56(a5)
-; RV32IXQCCMP-NEXT: sw s2, 52(a5)
-; RV32IXQCCMP-NEXT: sw t6, 48(a5)
-; RV32IXQCCMP-NEXT: sw a2, 44(a5)
-; RV32IXQCCMP-NEXT: sw s1, 40(a5)
-; RV32IXQCCMP-NEXT: sw s4, 36(a5)
-; RV32IXQCCMP-NEXT: sw s3, 32(a5)
-; RV32IXQCCMP-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-NEXT: sw t4, 24(a5)
-; RV32IXQCCMP-NEXT: sw t3, 20(a5)
-; RV32IXQCCMP-NEXT: sw t2, 16(a5)
-; RV32IXQCCMP-NEXT: sw t1, %lo(var0+12)(a0)
-; RV32IXQCCMP-NEXT: sw t0, %lo(var0+8)(a0)
-; RV32IXQCCMP-NEXT: sw a7, %lo(var0+4)(a0)
-; RV32IXQCCMP-NEXT: sw a6, %lo(var0)(a0)
-; RV32IXQCCMP-NEXT: qc.cm.popret {ra, s0-s4}, 32
+; RV32IXQCCMP-NEXT: addi a0, a0, %lo(var0)
+; RV32IXQCCMP-NEXT: lw a6, 0(a0)
+; RV32IXQCCMP-NEXT: lw a7, 4(a0)
+; RV32IXQCCMP-NEXT: lw t0, 8(a0)
+; RV32IXQCCMP-NEXT: lw t1, 12(a0)
+; RV32IXQCCMP-NEXT: lw t2, 16(a0)
+; RV32IXQCCMP-NEXT: lw t3, 20(a0)
+; RV32IXQCCMP-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-NEXT: lw t6, 48(a0)
+; RV32IXQCCMP-NEXT: lw s2, 52(a0)
+; RV32IXQCCMP-NEXT: lw a1, 56(a0)
+; RV32IXQCCMP-NEXT: lw a2, 60(a0)
+; RV32IXQCCMP-NEXT: lw a3, 64(a0)
+; RV32IXQCCMP-NEXT: lw a4, 68(a0)
+; RV32IXQCCMP-NEXT: lw s3, 32(a0)
+; RV32IXQCCMP-NEXT: lw s1, 36(a0)
+; RV32IXQCCMP-NEXT: lw a5, 40(a0)
+; RV32IXQCCMP-NEXT: lw s0, 44(a0)
+; RV32IXQCCMP-NEXT: sw a4, 68(a0)
+; RV32IXQCCMP-NEXT: sw a3, 64(a0)
+; RV32IXQCCMP-NEXT: sw a2, 60(a0)
+; RV32IXQCCMP-NEXT: sw a1, 56(a0)
+; RV32IXQCCMP-NEXT: sw s2, 52(a0)
+; RV32IXQCCMP-NEXT: sw t6, 48(a0)
+; RV32IXQCCMP-NEXT: sw s0, 44(a0)
+; RV32IXQCCMP-NEXT: sw a5, 40(a0)
+; RV32IXQCCMP-NEXT: sw s1, 36(a0)
+; RV32IXQCCMP-NEXT: sw s3, 32(a0)
+; RV32IXQCCMP-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-NEXT: sw t2, 16(a0)
+; RV32IXQCCMP-NEXT: sw t1, 12(a0)
+; RV32IXQCCMP-NEXT: sw t0, 8(a0)
+; RV32IXQCCMP-NEXT: sw a7, 4(a0)
+; RV32IXQCCMP-NEXT: sw a6, 0(a0)
+; RV32IXQCCMP-NEXT: qc.cm.popret {ra, s0-s3}, 32
;
; RV64IXQCCMP-LABEL: many_args:
; RV64IXQCCMP: # %bb.0: # %entry
-; RV64IXQCCMP-NEXT: qc.cm.push {ra, s0-s4}, -48
+; RV64IXQCCMP-NEXT: qc.cm.push {ra, s0-s3}, -48
; RV64IXQCCMP-NEXT: .cfi_def_cfa_offset 48
; RV64IXQCCMP-NEXT: .cfi_offset s0, -16
; RV64IXQCCMP-NEXT: .cfi_offset s1, -24
; RV64IXQCCMP-NEXT: .cfi_offset s2, -32
; RV64IXQCCMP-NEXT: .cfi_offset s3, -40
-; RV64IXQCCMP-NEXT: .cfi_offset s4, -48
; RV64IXQCCMP-NEXT: lui a0, %hi(var0)
-; RV64IXQCCMP-NEXT: lw a6, %lo(var0)(a0)
-; RV64IXQCCMP-NEXT: lw a7, %lo(var0+4)(a0)
-; RV64IXQCCMP-NEXT: lw t0, %lo(var0+8)(a0)
-; RV64IXQCCMP-NEXT: lw t1, %lo(var0+12)(a0)
-; RV64IXQCCMP-NEXT: addi a5, a0, %lo(var0)
-; RV64IXQCCMP-NEXT: lw t2, 16(a5)
-; RV64IXQCCMP-NEXT: lw t3, 20(a5)
-; RV64IXQCCMP-NEXT: lw t4, 24(a5)
-; RV64IXQCCMP-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-NEXT: lw t6, 48(a5)
-; RV64IXQCCMP-NEXT: lw s2, 52(a5)
-; RV64IXQCCMP-NEXT: lw a3, 56(a5)
-; RV64IXQCCMP-NEXT: lw a4, 60(a5)
-; RV64IXQCCMP-NEXT: lw a1, 64(a5)
-; RV64IXQCCMP-NEXT: lw s0, 68(a5)
-; RV64IXQCCMP-NEXT: lw s3, 32(a5)
-; RV64IXQCCMP-NEXT: lw s4, 36(a5)
-; RV64IXQCCMP-NEXT: lw s1, 40(a5)
-; RV64IXQCCMP-NEXT: lw a2, 44(a5)
-; RV64IXQCCMP-NEXT: sw s0, 68(a5)
-; RV64IXQCCMP-NEXT: sw a1, 64(a5)
-; RV64IXQCCMP-NEXT: sw a4, 60(a5)
-; RV64IXQCCMP-NEXT: sw a3, 56(a5)
-; RV64IXQCCMP-NEXT: sw s2, 52(a5)
-; RV64IXQCCMP-NEXT: sw t6, 48(a5)
-; RV64IXQCCMP-NEXT: sw a2, 44(a5)
-; RV64IXQCCMP-NEXT: sw s1, 40(a5)
-; RV64IXQCCMP-NEXT: sw s4, 36(a5)
-; RV64IXQCCMP-NEXT: sw s3, 32(a5)
-; RV64IXQCCMP-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-NEXT: sw t4, 24(a5)
-; RV64IXQCCMP-NEXT: sw t3, 20(a5)
-; RV64IXQCCMP-NEXT: sw t2, 16(a5)
-; RV64IXQCCMP-NEXT: sw t1, %lo(var0+12)(a0)
-; RV64IXQCCMP-NEXT: sw t0, %lo(var0+8)(a0)
-; RV64IXQCCMP-NEXT: sw a7, %lo(var0+4)(a0)
-; RV64IXQCCMP-NEXT: sw a6, %lo(var0)(a0)
-; RV64IXQCCMP-NEXT: qc.cm.popret {ra, s0-s4}, 48
+; RV64IXQCCMP-NEXT: addi a0, a0, %lo(var0)
+; RV64IXQCCMP-NEXT: lw a6, 0(a0)
+; RV64IXQCCMP-NEXT: lw a7, 4(a0)
+; RV64IXQCCMP-NEXT: lw t0, 8(a0)
+; RV64IXQCCMP-NEXT: lw t1, 12(a0)
+; RV64IXQCCMP-NEXT: lw t2, 16(a0)
+; RV64IXQCCMP-NEXT: lw t3, 20(a0)
+; RV64IXQCCMP-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-NEXT: lw t6, 48(a0)
+; RV64IXQCCMP-NEXT: lw s2, 52(a0)
+; RV64IXQCCMP-NEXT: lw a1, 56(a0)
+; RV64IXQCCMP-NEXT: lw a2, 60(a0)
+; RV64IXQCCMP-NEXT: lw a3, 64(a0)
+; RV64IXQCCMP-NEXT: lw a4, 68(a0)
+; RV64IXQCCMP-NEXT: lw s3, 32(a0)
+; RV64IXQCCMP-NEXT: lw s1, 36(a0)
+; RV64IXQCCMP-NEXT: lw a5, 40(a0)
+; RV64IXQCCMP-NEXT: lw s0, 44(a0)
+; RV64IXQCCMP-NEXT: sw a4, 68(a0)
+; RV64IXQCCMP-NEXT: sw a3, 64(a0)
+; RV64IXQCCMP-NEXT: sw a2, 60(a0)
+; RV64IXQCCMP-NEXT: sw a1, 56(a0)
+; RV64IXQCCMP-NEXT: sw s2, 52(a0)
+; RV64IXQCCMP-NEXT: sw t6, 48(a0)
+; RV64IXQCCMP-NEXT: sw s0, 44(a0)
+; RV64IXQCCMP-NEXT: sw a5, 40(a0)
+; RV64IXQCCMP-NEXT: sw s1, 36(a0)
+; RV64IXQCCMP-NEXT: sw s3, 32(a0)
+; RV64IXQCCMP-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-NEXT: sw t2, 16(a0)
+; RV64IXQCCMP-NEXT: sw t1, 12(a0)
+; RV64IXQCCMP-NEXT: sw t0, 8(a0)
+; RV64IXQCCMP-NEXT: sw a7, 4(a0)
+; RV64IXQCCMP-NEXT: sw a6, 0(a0)
+; RV64IXQCCMP-NEXT: qc.cm.popret {ra, s0-s3}, 48
;
; RV32IXQCCMP-FP-LABEL: many_args:
; RV32IXQCCMP-FP: # %bb.0: # %entry
-; RV32IXQCCMP-FP-NEXT: qc.cm.pushfp {ra, s0-s5}, -32
+; RV32IXQCCMP-FP-NEXT: qc.cm.pushfp {ra, s0-s4}, -32
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa_offset 32
; RV32IXQCCMP-FP-NEXT: .cfi_offset ra, -4
; RV32IXQCCMP-FP-NEXT: .cfi_offset s0, -8
@@ -1254,199 +1240,195 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV32IXQCCMP-FP-NEXT: .cfi_offset s2, -16
; RV32IXQCCMP-FP-NEXT: .cfi_offset s3, -20
; RV32IXQCCMP-FP-NEXT: .cfi_offset s4, -24
-; RV32IXQCCMP-FP-NEXT: .cfi_offset s5, -28
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-FP-NEXT: lui a0, %hi(var0)
-; RV32IXQCCMP-FP-NEXT: lw a6, %lo(var0)(a0)
-; RV32IXQCCMP-FP-NEXT: lw a7, %lo(var0+4)(a0)
-; RV32IXQCCMP-FP-NEXT: lw t0, %lo(var0+8)(a0)
-; RV32IXQCCMP-FP-NEXT: lw t1, %lo(var0+12)(a0)
-; RV32IXQCCMP-FP-NEXT: addi a5, a0, %lo(var0)
-; RV32IXQCCMP-FP-NEXT: lw t2, 16(a5)
-; RV32IXQCCMP-FP-NEXT: lw t3, 20(a5)
-; RV32IXQCCMP-FP-NEXT: lw t4, 24(a5)
-; RV32IXQCCMP-FP-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-FP-NEXT: lw t6, 48(a5)
-; RV32IXQCCMP-FP-NEXT: lw s3, 52(a5)
-; RV32IXQCCMP-FP-NEXT: lw s5, 56(a5)
-; RV32IXQCCMP-FP-NEXT: lw a4, 60(a5)
-; RV32IXQCCMP-FP-NEXT: lw a1, 64(a5)
-; RV32IXQCCMP-FP-NEXT: lw s1, 68(a5)
-; RV32IXQCCMP-FP-NEXT: lw s2, 32(a5)
-; RV32IXQCCMP-FP-NEXT: lw s4, 36(a5)
-; RV32IXQCCMP-FP-NEXT: lw a2, 40(a5)
-; RV32IXQCCMP-FP-NEXT: lw a3, 44(a5)
-; RV32IXQCCMP-FP-NEXT: sw s1, 68(a5)
-; RV32IXQCCMP-FP-NEXT: sw a1, 64(a5)
-; RV32IXQCCMP-FP-NEXT: sw a4, 60(a5)
-; RV32IXQCCMP-FP-NEXT: sw s5, 56(a5)
-; RV32IXQCCMP-FP-NEXT: sw s3, 52(a5)
-; RV32IXQCCMP-FP-NEXT: sw t6, 48(a5)
-; RV32IXQCCMP-FP-NEXT: sw a3, 44(a5)
-; RV32IXQCCMP-FP-NEXT: sw a2, 40(a5)
-; RV32IXQCCMP-FP-NEXT: sw s4, 36(a5)
-; RV32IXQCCMP-FP-NEXT: sw s2, 32(a5)
-; RV32IXQCCMP-FP-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-FP-NEXT: sw t4, 24(a5)
-; RV32IXQCCMP-FP-NEXT: sw t3, 20(a5)
-; RV32IXQCCMP-FP-NEXT: sw t2, 16(a5)
-; RV32IXQCCMP-FP-NEXT: sw t1, %lo(var0+12)(a0)
-; RV32IXQCCMP-FP-NEXT: sw t0, %lo(var0+8)(a0)
-; RV32IXQCCMP-FP-NEXT: sw a7, %lo(var0+4)(a0)
-; RV32IXQCCMP-FP-NEXT: sw a6, %lo(var0)(a0)
+; RV32IXQCCMP-FP-NEXT: addi a0, a0, %lo(var0)
+; RV32IXQCCMP-FP-NEXT: lw a6, 0(a0)
+; RV32IXQCCMP-FP-NEXT: lw a7, 4(a0)
+; RV32IXQCCMP-FP-NEXT: lw t0, 8(a0)
+; RV32IXQCCMP-FP-NEXT: lw t1, 12(a0)
+; RV32IXQCCMP-FP-NEXT: lw t2, 16(a0)
+; RV32IXQCCMP-FP-NEXT: lw t3, 20(a0)
+; RV32IXQCCMP-FP-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-FP-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-FP-NEXT: lw t6, 48(a0)
+; RV32IXQCCMP-FP-NEXT: lw s2, 52(a0)
+; RV32IXQCCMP-FP-NEXT: lw s4, 56(a0)
+; RV32IXQCCMP-FP-NEXT: lw a2, 60(a0)
+; RV32IXQCCMP-FP-NEXT: lw a3, 64(a0)
+; RV32IXQCCMP-FP-NEXT: lw a4, 68(a0)
+; RV32IXQCCMP-FP-NEXT: lw s3, 32(a0)
+; RV32IXQCCMP-FP-NEXT: lw a5, 36(a0)
+; RV32IXQCCMP-FP-NEXT: lw s1, 40(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, 44(a0)
+; RV32IXQCCMP-FP-NEXT: sw a4, 68(a0)
+; RV32IXQCCMP-FP-NEXT: sw a3, 64(a0)
+; RV32IXQCCMP-FP-NEXT: sw a2, 60(a0)
+; RV32IXQCCMP-FP-NEXT: sw s4, 56(a0)
+; RV32IXQCCMP-FP-NEXT: sw s2, 52(a0)
+; RV32IXQCCMP-FP-NEXT: sw t6, 48(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, 44(a0)
+; RV32IXQCCMP-FP-NEXT: sw s1, 40(a0)
+; RV32IXQCCMP-FP-NEXT: sw a5, 36(a0)
+; RV32IXQCCMP-FP-NEXT: sw s3, 32(a0)
+; RV32IXQCCMP-FP-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-FP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-FP-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-FP-NEXT: sw t2, 16(a0)
+; RV32IXQCCMP-FP-NEXT: sw t1, 12(a0)
+; RV32IXQCCMP-FP-NEXT: sw t0, 8(a0)
+; RV32IXQCCMP-FP-NEXT: sw a7, 4(a0)
+; RV32IXQCCMP-FP-NEXT: sw a6, 0(a0)
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 32
-; RV32IXQCCMP-FP-NEXT: qc.cm.popret {ra, s0-s5}, 32
+; RV32IXQCCMP-FP-NEXT: qc.cm.popret {ra, s0-s4}, 32
;
; RV64IXQCCMP-FP-LABEL: many_args:
; RV64IXQCCMP-FP: # %bb.0: # %entry
-; RV64IXQCCMP-FP-NEXT: qc.cm.pushfp {ra, s0-s5}, -64
-; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa_offset 64
+; RV64IXQCCMP-FP-NEXT: qc.cm.pushfp {ra, s0-s4}, -48
+; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa_offset 48
; RV64IXQCCMP-FP-NEXT: .cfi_offset ra, -8
; RV64IXQCCMP-FP-NEXT: .cfi_offset s0, -16
; RV64IXQCCMP-FP-NEXT: .cfi_offset s1, -24
; RV64IXQCCMP-FP-NEXT: .cfi_offset s2, -32
; RV64IXQCCMP-FP-NEXT: .cfi_offset s3, -40
; RV64IXQCCMP-FP-NEXT: .cfi_offset s4, -48
-; RV64IXQCCMP-FP-NEXT: .cfi_offset s5, -56
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
; RV64IXQCCMP-FP-NEXT: lui a0, %hi(var0)
-; RV64IXQCCMP-FP-NEXT: lw a6, %lo(var0)(a0)
-; RV64IXQCCMP-FP-NEXT: lw a7, %lo(var0+4)(a0)
-; RV64IXQCCMP-FP-NEXT: lw t0, %lo(var0+8)(a0)
-; RV64IXQCCMP-FP-NEXT: lw t1, %lo(var0+12)(a0)
-; RV64IXQCCMP-FP-NEXT: addi a5, a0, %lo(var0)
-; RV64IXQCCMP-FP-NEXT: lw t2, 16(a5)
-; RV64IXQCCMP-FP-NEXT: lw t3, 20(a5)
-; RV64IXQCCMP-FP-NEXT: lw t4, 24(a5)
-; RV64IXQCCMP-FP-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-FP-NEXT: lw t6, 48(a5)
-; RV64IXQCCMP-FP-NEXT: lw s3, 52(a5)
-; RV64IXQCCMP-FP-NEXT: lw s5, 56(a5)
-; RV64IXQCCMP-FP-NEXT: lw a4, 60(a5)
-; RV64IXQCCMP-FP-NEXT: lw a1, 64(a5)
-; RV64IXQCCMP-FP-NEXT: lw s1, 68(a5)
-; RV64IXQCCMP-FP-NEXT: lw s2, 32(a5)
-; RV64IXQCCMP-FP-NEXT: lw s4, 36(a5)
-; RV64IXQCCMP-FP-NEXT: lw a2, 40(a5)
-; RV64IXQCCMP-FP-NEXT: lw a3, 44(a5)
-; RV64IXQCCMP-FP-NEXT: sw s1, 68(a5)
-; RV64IXQCCMP-FP-NEXT: sw a1, 64(a5)
-; RV64IXQCCMP-FP-NEXT: sw a4, 60(a5)
-; RV64IXQCCMP-FP-NEXT: sw s5, 56(a5)
-; RV64IXQCCMP-FP-NEXT: sw s3, 52(a5)
-; RV64IXQCCMP-FP-NEXT: sw t6, 48(a5)
-; RV64IXQCCMP-FP-NEXT: sw a3, 44(a5)
-; RV64IXQCCMP-FP-NEXT: sw a2, 40(a5)
-; RV64IXQCCMP-FP-NEXT: sw s4, 36(a5)
-; RV64IXQCCMP-FP-NEXT: sw s2, 32(a5)
-; RV64IXQCCMP-FP-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-FP-NEXT: sw t4, 24(a5)
-; RV64IXQCCMP-FP-NEXT: sw t3, 20(a5)
-; RV64IXQCCMP-FP-NEXT: sw t2, 16(a5)
-; RV64IXQCCMP-FP-NEXT: sw t1, %lo(var0+12)(a0)
-; RV64IXQCCMP-FP-NEXT: sw t0, %lo(var0+8)(a0)
-; RV64IXQCCMP-FP-NEXT: sw a7, %lo(var0+4)(a0)
-; RV64IXQCCMP-FP-NEXT: sw a6, %lo(var0)(a0)
-; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 64
-; RV64IXQCCMP-FP-NEXT: qc.cm.popret {ra, s0-s5}, 64
+; RV64IXQCCMP-FP-NEXT: addi a0, a0, %lo(var0)
+; RV64IXQCCMP-FP-NEXT: lw a6, 0(a0)
+; RV64IXQCCMP-FP-NEXT: lw a7, 4(a0)
+; RV64IXQCCMP-FP-NEXT: lw t0, 8(a0)
+; RV64IXQCCMP-FP-NEXT: lw t1, 12(a0)
+; RV64IXQCCMP-FP-NEXT: lw t2, 16(a0)
+; RV64IXQCCMP-FP-NEXT: lw t3, 20(a0)
+; RV64IXQCCMP-FP-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-FP-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-FP-NEXT: lw t6, 48(a0)
+; RV64IXQCCMP-FP-NEXT: lw s2, 52(a0)
+; RV64IXQCCMP-FP-NEXT: lw s4, 56(a0)
+; RV64IXQCCMP-FP-NEXT: lw a2, 60(a0)
+; RV64IXQCCMP-FP-NEXT: lw a3, 64(a0)
+; RV64IXQCCMP-FP-NEXT: lw a4, 68(a0)
+; RV64IXQCCMP-FP-NEXT: lw s3, 32(a0)
+; RV64IXQCCMP-FP-NEXT: lw a5, 36(a0)
+; RV64IXQCCMP-FP-NEXT: lw s1, 40(a0)
+; RV64IXQCCMP-FP-NEXT: lw a1, 44(a0)
+; RV64IXQCCMP-FP-NEXT: sw a4, 68(a0)
+; RV64IXQCCMP-FP-NEXT: sw a3, 64(a0)
+; RV64IXQCCMP-FP-NEXT: sw a2, 60(a0)
+; RV64IXQCCMP-FP-NEXT: sw s4, 56(a0)
+; RV64IXQCCMP-FP-NEXT: sw s2, 52(a0)
+; RV64IXQCCMP-FP-NEXT: sw t6, 48(a0)
+; RV64IXQCCMP-FP-NEXT: sw a1, 44(a0)
+; RV64IXQCCMP-FP-NEXT: sw s1, 40(a0)
+; RV64IXQCCMP-FP-NEXT: sw a5, 36(a0)
+; RV64IXQCCMP-FP-NEXT: sw s3, 32(a0)
+; RV64IXQCCMP-FP-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-FP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-FP-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-FP-NEXT: sw t2, 16(a0)
+; RV64IXQCCMP-FP-NEXT: sw t1, 12(a0)
+; RV64IXQCCMP-FP-NEXT: sw t0, 8(a0)
+; RV64IXQCCMP-FP-NEXT: sw a7, 4(a0)
+; RV64IXQCCMP-FP-NEXT: sw a6, 0(a0)
+; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 48
+; RV64IXQCCMP-FP-NEXT: qc.cm.popret {ra, s0-s4}, 48
;
; RV32IXQCCMP-SR-LABEL: many_args:
; RV32IXQCCMP-SR: # %bb.0: # %entry
-; RV32IXQCCMP-SR-NEXT: qc.cm.push {ra, s0-s4}, -32
+; RV32IXQCCMP-SR-NEXT: qc.cm.push {ra, s0-s3}, -32
; RV32IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 32
; RV32IXQCCMP-SR-NEXT: .cfi_offset s0, -8
; RV32IXQCCMP-SR-NEXT: .cfi_offset s1, -12
; RV32IXQCCMP-SR-NEXT: .cfi_offset s2, -16
; RV32IXQCCMP-SR-NEXT: .cfi_offset s3, -20
-; RV32IXQCCMP-SR-NEXT: .cfi_offset s4, -24
; RV32IXQCCMP-SR-NEXT: lui a0, %hi(var0)
-; RV32IXQCCMP-SR-NEXT: lw a6, %lo(var0)(a0)
-; RV32IXQCCMP-SR-NEXT: lw a7, %lo(var0+4)(a0)
-; RV32IXQCCMP-SR-NEXT: lw t0, %lo(var0+8)(a0)
-; RV32IXQCCMP-SR-NEXT: lw t1, %lo(var0+12)(a0)
-; RV32IXQCCMP-SR-NEXT: addi a5, a0, %lo(var0)
-; RV32IXQCCMP-SR-NEXT: lw t2, 16(a5)
-; RV32IXQCCMP-SR-NEXT: lw t3, 20(a5)
-; RV32IXQCCMP-SR-NEXT: lw t4, 24(a5)
-; RV32IXQCCMP-SR-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-SR-NEXT: lw t6, 48(a5)
-; RV32IXQCCMP-SR-NEXT: lw s2, 52(a5)
-; RV32IXQCCMP-SR-NEXT: lw a3, 56(a5)
-; RV32IXQCCMP-SR-NEXT: lw a4, 60(a5)
-; RV32IXQCCMP-SR-NEXT: lw a1, 64(a5)
-; RV32IXQCCMP-SR-NEXT: lw s0, 68(a5)
-; RV32IXQCCMP-SR-NEXT: lw s3, 32(a5)
-; RV32IXQCCMP-SR-NEXT: lw s4, 36(a5)
-; RV32IXQCCMP-SR-NEXT: lw s1, 40(a5)
-; RV32IXQCCMP-SR-NEXT: lw a2, 44(a5)
-; RV32IXQCCMP-SR-NEXT: sw s0, 68(a5)
-; RV32IXQCCMP-SR-NEXT: sw a1, 64(a5)
-; RV32IXQCCMP-SR-NEXT: sw a4, 60(a5)
-; RV32IXQCCMP-SR-NEXT: sw a3, 56(a5)
-; RV32IXQCCMP-SR-NEXT: sw s2, 52(a5)
-; RV32IXQCCMP-SR-NEXT: sw t6, 48(a5)
-; RV32IXQCCMP-SR-NEXT: sw a2, 44(a5)
-; RV32IXQCCMP-SR-NEXT: sw s1, 40(a5)
-; RV32IXQCCMP-SR-NEXT: sw s4, 36(a5)
-; RV32IXQCCMP-SR-NEXT: sw s3, 32(a5)
-; RV32IXQCCMP-SR-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-SR-NEXT: sw t4, 24(a5)
-; RV32IXQCCMP-SR-NEXT: sw t3, 20(a5)
-; RV32IXQCCMP-SR-NEXT: sw t2, 16(a5)
-; RV32IXQCCMP-SR-NEXT: sw t1, %lo(var0+12)(a0)
-; RV32IXQCCMP-SR-NEXT: sw t0, %lo(var0+8)(a0)
-; RV32IXQCCMP-SR-NEXT: sw a7, %lo(var0+4)(a0)
-; RV32IXQCCMP-SR-NEXT: sw a6, %lo(var0)(a0)
-; RV32IXQCCMP-SR-NEXT: qc.cm.popret {ra, s0-s4}, 32
+; RV32IXQCCMP-SR-NEXT: addi a0, a0, %lo(var0)
+; RV32IXQCCMP-SR-NEXT: lw a6, 0(a0)
+; RV32IXQCCMP-SR-NEXT: lw a7, 4(a0)
+; RV32IXQCCMP-SR-NEXT: lw t0, 8(a0)
+; RV32IXQCCMP-SR-NEXT: lw t1, 12(a0)
+; RV32IXQCCMP-SR-NEXT: lw t2, 16(a0)
+; RV32IXQCCMP-SR-NEXT: lw t3, 20(a0)
+; RV32IXQCCMP-SR-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-SR-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-SR-NEXT: lw t6, 48(a0)
+; RV32IXQCCMP-SR-NEXT: lw s2, 52(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 56(a0)
+; RV32IXQCCMP-SR-NEXT: lw a2, 60(a0)
+; RV32IXQCCMP-SR-NEXT: lw a3, 64(a0)
+; RV32IXQCCMP-SR-NEXT: lw a4, 68(a0)
+; RV32IXQCCMP-SR-NEXT: lw s3, 32(a0)
+; RV32IXQCCMP-SR-NEXT: lw s1, 36(a0)
+; RV32IXQCCMP-SR-NEXT: lw a5, 40(a0)
+; RV32IXQCCMP-SR-NEXT: lw s0, 44(a0)
+; RV32IXQCCMP-SR-NEXT: sw a4, 68(a0)
+; RV32IXQCCMP-SR-NEXT: sw a3, 64(a0)
+; RV32IXQCCMP-SR-NEXT: sw a2, 60(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 56(a0)
+; RV32IXQCCMP-SR-NEXT: sw s2, 52(a0)
+; RV32IXQCCMP-SR-NEXT: sw t6, 48(a0)
+; RV32IXQCCMP-SR-NEXT: sw s0, 44(a0)
+; RV32IXQCCMP-SR-NEXT: sw a5, 40(a0)
+; RV32IXQCCMP-SR-NEXT: sw s1, 36(a0)
+; RV32IXQCCMP-SR-NEXT: sw s3, 32(a0)
+; RV32IXQCCMP-SR-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-SR-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-SR-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-SR-NEXT: sw t2, 16(a0)
+; RV32IXQCCMP-SR-NEXT: sw t1, 12(a0)
+; RV32IXQCCMP-SR-NEXT: sw t0, 8(a0)
+; RV32IXQCCMP-SR-NEXT: sw a7, 4(a0)
+; RV32IXQCCMP-SR-NEXT: sw a6, 0(a0)
+; RV32IXQCCMP-SR-NEXT: qc.cm.popret {ra, s0-s3}, 32
;
; RV64IXQCCMP-SR-LABEL: many_args:
; RV64IXQCCMP-SR: # %bb.0: # %entry
-; RV64IXQCCMP-SR-NEXT: qc.cm.push {ra, s0-s4}, -48
+; RV64IXQCCMP-SR-NEXT: qc.cm.push {ra, s0-s3}, -48
; RV64IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 48
; RV64IXQCCMP-SR-NEXT: .cfi_offset s0, -16
; RV64IXQCCMP-SR-NEXT: .cfi_offset s1, -24
; RV64IXQCCMP-SR-NEXT: .cfi_offset s2, -32
; RV64IXQCCMP-SR-NEXT: .cfi_offset s3, -40
-; RV64IXQCCMP-SR-NEXT: .cfi_offset s4, -48
; RV64IXQCCMP-SR-NEXT: lui a0, %hi(var0)
-; RV64IXQCCMP-SR-NEXT: lw a6, %lo(var0)(a0)
-; RV64IXQCCMP-SR-NEXT: lw a7, %lo(var0+4)(a0)
-; RV64IXQCCMP-SR-NEXT: lw t0, %lo(var0+8)(a0)
-; RV64IXQCCMP-SR-NEXT: lw t1, %lo(var0+12)(a0)
-; RV64IXQCCMP-SR-NEXT: addi a5, a0, %lo(var0)
-; RV64IXQCCMP-SR-NEXT: lw t2, 16(a5)
-; RV64IXQCCMP-SR-NEXT: lw t3, 20(a5)
-; RV64IXQCCMP-SR-NEXT: lw t4, 24(a5)
-; RV64IXQCCMP-SR-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-SR-NEXT: lw t6, 48(a5)
-; RV64IXQCCMP-SR-NEXT: lw s2, 52(a5)
-; RV64IXQCCMP-SR-NEXT: lw a3, 56(a5)
-; RV64IXQCCMP-SR-NEXT: lw a4, 60(a5)
-; RV64IXQCCMP-SR-NEXT: lw a1, 64(a5)
-; RV64IXQCCMP-SR-NEXT: lw s0, 68(a5)
-; RV64IXQCCMP-SR-NEXT: lw s3, 32(a5)
-; RV64IXQCCMP-SR-NEXT: lw s4, 36(a5)
-; RV64IXQCCMP-SR-NEXT: lw s1, 40(a5)
-; RV64IXQCCMP-SR-NEXT: lw a2, 44(a5)
-; RV64IXQCCMP-SR-NEXT: sw s0, 68(a5)
-; RV64IXQCCMP-SR-NEXT: sw a1, 64(a5)
-; RV64IXQCCMP-SR-NEXT: sw a4, 60(a5)
-; RV64IXQCCMP-SR-NEXT: sw a3, 56(a5)
-; RV64IXQCCMP-SR-NEXT: sw s2, 52(a5)
-; RV64IXQCCMP-SR-NEXT: sw t6, 48(a5)
-; RV64IXQCCMP-SR-NEXT: sw a2, 44(a5)
-; RV64IXQCCMP-SR-NEXT: sw s1, 40(a5)
-; RV64IXQCCMP-SR-NEXT: sw s4, 36(a5)
-; RV64IXQCCMP-SR-NEXT: sw s3, 32(a5)
-; RV64IXQCCMP-SR-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-SR-NEXT: sw t4, 24(a5)
-; RV64IXQCCMP-SR-NEXT: sw t3, 20(a5)
-; RV64IXQCCMP-SR-NEXT: sw t2, 16(a5)
-; RV64IXQCCMP-SR-NEXT: sw t1, %lo(var0+12)(a0)
-; RV64IXQCCMP-SR-NEXT: sw t0, %lo(var0+8)(a0)
-; RV64IXQCCMP-SR-NEXT: sw a7, %lo(var0+4)(a0)
-; RV64IXQCCMP-SR-NEXT: sw a6, %lo(var0)(a0)
-; RV64IXQCCMP-SR-NEXT: qc.cm.popret {ra, s0-s4}, 48
+; RV64IXQCCMP-SR-NEXT: addi a0, a0, %lo(var0)
+; RV64IXQCCMP-SR-NEXT: lw a6, 0(a0)
+; RV64IXQCCMP-SR-NEXT: lw a7, 4(a0)
+; RV64IXQCCMP-SR-NEXT: lw t0, 8(a0)
+; RV64IXQCCMP-SR-NEXT: lw t1, 12(a0)
+; RV64IXQCCMP-SR-NEXT: lw t2, 16(a0)
+; RV64IXQCCMP-SR-NEXT: lw t3, 20(a0)
+; RV64IXQCCMP-SR-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-SR-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-SR-NEXT: lw t6, 48(a0)
+; RV64IXQCCMP-SR-NEXT: lw s2, 52(a0)
+; RV64IXQCCMP-SR-NEXT: lw a1, 56(a0)
+; RV64IXQCCMP-SR-NEXT: lw a2, 60(a0)
+; RV64IXQCCMP-SR-NEXT: lw a3, 64(a0)
+; RV64IXQCCMP-SR-NEXT: lw a4, 68(a0)
+; RV64IXQCCMP-SR-NEXT: lw s3, 32(a0)
+; RV64IXQCCMP-SR-NEXT: lw s1, 36(a0)
+; RV64IXQCCMP-SR-NEXT: lw a5, 40(a0)
+; RV64IXQCCMP-SR-NEXT: lw s0, 44(a0)
+; RV64IXQCCMP-SR-NEXT: sw a4, 68(a0)
+; RV64IXQCCMP-SR-NEXT: sw a3, 64(a0)
+; RV64IXQCCMP-SR-NEXT: sw a2, 60(a0)
+; RV64IXQCCMP-SR-NEXT: sw a1, 56(a0)
+; RV64IXQCCMP-SR-NEXT: sw s2, 52(a0)
+; RV64IXQCCMP-SR-NEXT: sw t6, 48(a0)
+; RV64IXQCCMP-SR-NEXT: sw s0, 44(a0)
+; RV64IXQCCMP-SR-NEXT: sw a5, 40(a0)
+; RV64IXQCCMP-SR-NEXT: sw s1, 36(a0)
+; RV64IXQCCMP-SR-NEXT: sw s3, 32(a0)
+; RV64IXQCCMP-SR-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-SR-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-SR-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-SR-NEXT: sw t2, 16(a0)
+; RV64IXQCCMP-SR-NEXT: sw t1, 12(a0)
+; RV64IXQCCMP-SR-NEXT: sw t0, 8(a0)
+; RV64IXQCCMP-SR-NEXT: sw a7, 4(a0)
+; RV64IXQCCMP-SR-NEXT: sw a6, 0(a0)
+; RV64IXQCCMP-SR-NEXT: qc.cm.popret {ra, s0-s3}, 48
entry:
%val = load [18 x i32], ptr @var0
store volatile [18 x i32] %val, ptr @var0
@@ -2127,23 +2109,23 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IXQCCMP-NEXT: .cfi_offset s9, -44
; RV32IXQCCMP-NEXT: .cfi_offset s10, -48
; RV32IXQCCMP-NEXT: .cfi_offset s11, -52
-; RV32IXQCCMP-NEXT: addi sp, sp, -48
-; RV32IXQCCMP-NEXT: .cfi_def_cfa_offset 160
-; RV32IXQCCMP-NEXT: sw t0, 92(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw t1, 88(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw t2, 84(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw a1, 76(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw a2, 72(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw a3, 68(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw a4, 64(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw a5, 60(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw a6, 56(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw a7, 52(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw t3, 48(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw t4, 44(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw t5, 40(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: sw t6, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: addi sp, sp, -32
+; RV32IXQCCMP-NEXT: .cfi_def_cfa_offset 144
+; RV32IXQCCMP-NEXT: sw t0, 76(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw t1, 72(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw t2, 68(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw a1, 60(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw a2, 56(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw a3, 52(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw a4, 48(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw a5, 44(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw a6, 40(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw a7, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw t3, 32(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw t4, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw t5, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: sw t6, 20(sp) # 4-byte Folded Spill
; RV32IXQCCMP-NEXT: .cfi_offset t0, -68
; RV32IXQCCMP-NEXT: .cfi_offset t1, -72
; RV32IXQCCMP-NEXT: .cfi_offset t2, -76
@@ -2159,99 +2141,97 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IXQCCMP-NEXT: .cfi_offset t4, -116
; RV32IXQCCMP-NEXT: .cfi_offset t5, -120
; RV32IXQCCMP-NEXT: .cfi_offset t6, -124
-; RV32IXQCCMP-NEXT: lui t0, %hi(var_test_irq)
-; RV32IXQCCMP-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV32IXQCCMP-NEXT: lw a0, 16(a5)
-; RV32IXQCCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 20(a5)
-; RV32IXQCCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw t4, 24(a5)
-; RV32IXQCCMP-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-NEXT: lw t6, 32(a5)
-; RV32IXQCCMP-NEXT: lw s2, 36(a5)
-; RV32IXQCCMP-NEXT: lw s3, 40(a5)
-; RV32IXQCCMP-NEXT: lw s4, 44(a5)
-; RV32IXQCCMP-NEXT: lw s5, 48(a5)
-; RV32IXQCCMP-NEXT: lw s6, 52(a5)
-; RV32IXQCCMP-NEXT: lw s7, 56(a5)
-; RV32IXQCCMP-NEXT: lw s8, 60(a5)
-; RV32IXQCCMP-NEXT: lw s9, 64(a5)
-; RV32IXQCCMP-NEXT: lw s10, 68(a5)
-; RV32IXQCCMP-NEXT: lw s11, 72(a5)
-; RV32IXQCCMP-NEXT: lw ra, 76(a5)
-; RV32IXQCCMP-NEXT: lw s1, 80(a5)
-; RV32IXQCCMP-NEXT: lw t3, 84(a5)
-; RV32IXQCCMP-NEXT: lw t2, 88(a5)
-; RV32IXQCCMP-NEXT: lw t1, 92(a5)
-; RV32IXQCCMP-NEXT: lw a7, 112(a5)
-; RV32IXQCCMP-NEXT: lw s0, 116(a5)
-; RV32IXQCCMP-NEXT: lw a3, 120(a5)
-; RV32IXQCCMP-NEXT: lw a0, 124(a5)
-; RV32IXQCCMP-NEXT: lw a6, 96(a5)
-; RV32IXQCCMP-NEXT: lw a4, 100(a5)
-; RV32IXQCCMP-NEXT: lw a2, 104(a5)
-; RV32IXQCCMP-NEXT: lw a1, 108(a5)
-; RV32IXQCCMP-NEXT: sw a0, 124(a5)
-; RV32IXQCCMP-NEXT: sw a3, 120(a5)
-; RV32IXQCCMP-NEXT: sw s0, 116(a5)
-; RV32IXQCCMP-NEXT: sw a7, 112(a5)
-; RV32IXQCCMP-NEXT: sw a1, 108(a5)
-; RV32IXQCCMP-NEXT: sw a2, 104(a5)
-; RV32IXQCCMP-NEXT: sw a4, 100(a5)
-; RV32IXQCCMP-NEXT: sw a6, 96(a5)
-; RV32IXQCCMP-NEXT: sw t1, 92(a5)
-; RV32IXQCCMP-NEXT: sw t2, 88(a5)
-; RV32IXQCCMP-NEXT: sw t3, 84(a5)
-; RV32IXQCCMP-NEXT: sw s1, 80(a5)
-; RV32IXQCCMP-NEXT: sw ra, 76(a5)
-; RV32IXQCCMP-NEXT: sw s11, 72(a5)
-; RV32IXQCCMP-NEXT: sw s10, 68(a5)
-; RV32IXQCCMP-NEXT: sw s9, 64(a5)
-; RV32IXQCCMP-NEXT: sw s8, 60(a5)
-; RV32IXQCCMP-NEXT: sw s7, 56(a5)
-; RV32IXQCCMP-NEXT: sw s6, 52(a5)
-; RV32IXQCCMP-NEXT: sw s5, 48(a5)
-; RV32IXQCCMP-NEXT: sw s4, 44(a5)
-; RV32IXQCCMP-NEXT: sw s3, 40(a5)
-; RV32IXQCCMP-NEXT: sw s2, 36(a5)
-; RV32IXQCCMP-NEXT: sw t6, 32(a5)
-; RV32IXQCCMP-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-NEXT: sw t4, 24(a5)
-; RV32IXQCCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 20(a5)
-; RV32IXQCCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 16(a5)
-; RV32IXQCCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-NEXT: lw t0, 92(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw t1, 88(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw t2, 84(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw a1, 76(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw a2, 72(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw a3, 68(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw a4, 64(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw a5, 60(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw a6, 56(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw a7, 52(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw t3, 48(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw t4, 44(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw t5, 40(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: lw t6, 36(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lui a0, %hi(var_test_irq)
+; RV32IXQCCMP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32IXQCCMP-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 4(a0)
+; RV32IXQCCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 8(a0)
+; RV32IXQCCMP-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 12(a0)
+; RV32IXQCCMP-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 16(a0)
+; RV32IXQCCMP-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw t3, 20(a0)
+; RV32IXQCCMP-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-NEXT: lw t6, 32(a0)
+; RV32IXQCCMP-NEXT: lw s2, 36(a0)
+; RV32IXQCCMP-NEXT: lw s3, 40(a0)
+; RV32IXQCCMP-NEXT: lw s4, 44(a0)
+; RV32IXQCCMP-NEXT: lw s5, 48(a0)
+; RV32IXQCCMP-NEXT: lw s6, 52(a0)
+; RV32IXQCCMP-NEXT: lw s7, 56(a0)
+; RV32IXQCCMP-NEXT: lw s8, 60(a0)
+; RV32IXQCCMP-NEXT: lw s9, 64(a0)
+; RV32IXQCCMP-NEXT: lw s10, 68(a0)
+; RV32IXQCCMP-NEXT: lw s11, 72(a0)
+; RV32IXQCCMP-NEXT: lw ra, 76(a0)
+; RV32IXQCCMP-NEXT: lw t2, 80(a0)
+; RV32IXQCCMP-NEXT: lw s0, 84(a0)
+; RV32IXQCCMP-NEXT: lw s1, 88(a0)
+; RV32IXQCCMP-NEXT: lw t1, 92(a0)
+; RV32IXQCCMP-NEXT: lw t0, 112(a0)
+; RV32IXQCCMP-NEXT: lw a5, 116(a0)
+; RV32IXQCCMP-NEXT: lw a3, 120(a0)
+; RV32IXQCCMP-NEXT: lw a1, 124(a0)
+; RV32IXQCCMP-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-NEXT: lw a6, 100(a0)
+; RV32IXQCCMP-NEXT: lw a4, 104(a0)
+; RV32IXQCCMP-NEXT: lw a2, 108(a0)
+; RV32IXQCCMP-NEXT: sw a1, 124(a0)
+; RV32IXQCCMP-NEXT: sw a3, 120(a0)
+; RV32IXQCCMP-NEXT: sw a5, 116(a0)
+; RV32IXQCCMP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-NEXT: sw a2, 108(a0)
+; RV32IXQCCMP-NEXT: sw a4, 104(a0)
+; RV32IXQCCMP-NEXT: sw a6, 100(a0)
+; RV32IXQCCMP-NEXT: sw a7, 96(a0)
+; RV32IXQCCMP-NEXT: sw t1, 92(a0)
+; RV32IXQCCMP-NEXT: sw s1, 88(a0)
+; RV32IXQCCMP-NEXT: sw s0, 84(a0)
+; RV32IXQCCMP-NEXT: sw t2, 80(a0)
+; RV32IXQCCMP-NEXT: sw ra, 76(a0)
+; RV32IXQCCMP-NEXT: sw s11, 72(a0)
+; RV32IXQCCMP-NEXT: sw s10, 68(a0)
+; RV32IXQCCMP-NEXT: sw s9, 64(a0)
+; RV32IXQCCMP-NEXT: sw s8, 60(a0)
+; RV32IXQCCMP-NEXT: sw s7, 56(a0)
+; RV32IXQCCMP-NEXT: sw s6, 52(a0)
+; RV32IXQCCMP-NEXT: sw s5, 48(a0)
+; RV32IXQCCMP-NEXT: sw s4, 44(a0)
+; RV32IXQCCMP-NEXT: sw s3, 40(a0)
+; RV32IXQCCMP-NEXT: sw s2, 36(a0)
+; RV32IXQCCMP-NEXT: sw t6, 32(a0)
+; RV32IXQCCMP-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 16(a0)
+; RV32IXQCCMP-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 12(a0)
+; RV32IXQCCMP-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 8(a0)
+; RV32IXQCCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 4(a0)
+; RV32IXQCCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 0(a0)
+; RV32IXQCCMP-NEXT: lw t0, 76(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw t1, 72(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw t2, 68(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw a1, 60(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw a2, 56(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw a3, 52(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw a4, 48(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw a5, 44(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw a6, 40(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw a7, 36(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw t3, 32(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw t4, 28(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw t5, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: lw t6, 20(sp) # 4-byte Folded Reload
; RV32IXQCCMP-NEXT: .cfi_restore t0
; RV32IXQCCMP-NEXT: .cfi_restore t1
; RV32IXQCCMP-NEXT: .cfi_restore t2
@@ -2267,7 +2247,7 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IXQCCMP-NEXT: .cfi_restore t4
; RV32IXQCCMP-NEXT: .cfi_restore t5
; RV32IXQCCMP-NEXT: .cfi_restore t6
-; RV32IXQCCMP-NEXT: addi sp, sp, 48
+; RV32IXQCCMP-NEXT: addi sp, sp, 32
; RV32IXQCCMP-NEXT: .cfi_def_cfa_offset 112
; RV32IXQCCMP-NEXT: qc.cm.pop {ra, s0-s11}, 112
; RV32IXQCCMP-NEXT: .cfi_restore ra
@@ -2303,23 +2283,23 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IXQCCMP-NEXT: .cfi_offset s9, -88
; RV64IXQCCMP-NEXT: .cfi_offset s10, -96
; RV64IXQCCMP-NEXT: .cfi_offset s11, -104
-; RV64IXQCCMP-NEXT: addi sp, sp, -128
-; RV64IXQCCMP-NEXT: .cfi_def_cfa_offset 288
-; RV64IXQCCMP-NEXT: sd t0, 168(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd t1, 160(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd t2, 152(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd a1, 136(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd a2, 128(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd a3, 120(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd a4, 112(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd a5, 104(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd a6, 96(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd a7, 88(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd t3, 80(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd t4, 72(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd t5, 64(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: sd t6, 56(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: addi sp, sp, -112
+; RV64IXQCCMP-NEXT: .cfi_def_cfa_offset 272
+; RV64IXQCCMP-NEXT: sd t0, 152(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd t1, 144(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd t2, 136(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd a1, 120(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd a2, 112(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd a3, 104(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd a4, 96(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd a5, 88(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd a6, 80(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd a7, 72(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd t3, 64(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd t4, 56(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd t5, 48(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: sd t6, 40(sp) # 8-byte Folded Spill
; RV64IXQCCMP-NEXT: .cfi_offset t0, -120
; RV64IXQCCMP-NEXT: .cfi_offset t1, -128
; RV64IXQCCMP-NEXT: .cfi_offset t2, -136
@@ -2335,99 +2315,97 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IXQCCMP-NEXT: .cfi_offset t4, -216
; RV64IXQCCMP-NEXT: .cfi_offset t5, -224
; RV64IXQCCMP-NEXT: .cfi_offset t6, -232
-; RV64IXQCCMP-NEXT: lui t0, %hi(var_test_irq)
-; RV64IXQCCMP-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV64IXQCCMP-NEXT: lw a0, 16(a5)
-; RV64IXQCCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 20(a5)
-; RV64IXQCCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw t4, 24(a5)
-; RV64IXQCCMP-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-NEXT: lw t6, 32(a5)
-; RV64IXQCCMP-NEXT: lw s2, 36(a5)
-; RV64IXQCCMP-NEXT: lw s3, 40(a5)
-; RV64IXQCCMP-NEXT: lw s4, 44(a5)
-; RV64IXQCCMP-NEXT: lw s5, 48(a5)
-; RV64IXQCCMP-NEXT: lw s6, 52(a5)
-; RV64IXQCCMP-NEXT: lw s7, 56(a5)
-; RV64IXQCCMP-NEXT: lw s8, 60(a5)
-; RV64IXQCCMP-NEXT: lw s9, 64(a5)
-; RV64IXQCCMP-NEXT: lw s10, 68(a5)
-; RV64IXQCCMP-NEXT: lw s11, 72(a5)
-; RV64IXQCCMP-NEXT: lw ra, 76(a5)
-; RV64IXQCCMP-NEXT: lw s1, 80(a5)
-; RV64IXQCCMP-NEXT: lw t3, 84(a5)
-; RV64IXQCCMP-NEXT: lw t2, 88(a5)
-; RV64IXQCCMP-NEXT: lw t1, 92(a5)
-; RV64IXQCCMP-NEXT: lw a7, 112(a5)
-; RV64IXQCCMP-NEXT: lw s0, 116(a5)
-; RV64IXQCCMP-NEXT: lw a3, 120(a5)
-; RV64IXQCCMP-NEXT: lw a0, 124(a5)
-; RV64IXQCCMP-NEXT: lw a6, 96(a5)
-; RV64IXQCCMP-NEXT: lw a4, 100(a5)
-; RV64IXQCCMP-NEXT: lw a2, 104(a5)
-; RV64IXQCCMP-NEXT: lw a1, 108(a5)
-; RV64IXQCCMP-NEXT: sw a0, 124(a5)
-; RV64IXQCCMP-NEXT: sw a3, 120(a5)
-; RV64IXQCCMP-NEXT: sw s0, 116(a5)
-; RV64IXQCCMP-NEXT: sw a7, 112(a5)
-; RV64IXQCCMP-NEXT: sw a1, 108(a5)
-; RV64IXQCCMP-NEXT: sw a2, 104(a5)
-; RV64IXQCCMP-NEXT: sw a4, 100(a5)
-; RV64IXQCCMP-NEXT: sw a6, 96(a5)
-; RV64IXQCCMP-NEXT: sw t1, 92(a5)
-; RV64IXQCCMP-NEXT: sw t2, 88(a5)
-; RV64IXQCCMP-NEXT: sw t3, 84(a5)
-; RV64IXQCCMP-NEXT: sw s1, 80(a5)
-; RV64IXQCCMP-NEXT: sw ra, 76(a5)
-; RV64IXQCCMP-NEXT: sw s11, 72(a5)
-; RV64IXQCCMP-NEXT: sw s10, 68(a5)
-; RV64IXQCCMP-NEXT: sw s9, 64(a5)
-; RV64IXQCCMP-NEXT: sw s8, 60(a5)
-; RV64IXQCCMP-NEXT: sw s7, 56(a5)
-; RV64IXQCCMP-NEXT: sw s6, 52(a5)
-; RV64IXQCCMP-NEXT: sw s5, 48(a5)
-; RV64IXQCCMP-NEXT: sw s4, 44(a5)
-; RV64IXQCCMP-NEXT: sw s3, 40(a5)
-; RV64IXQCCMP-NEXT: sw s2, 36(a5)
-; RV64IXQCCMP-NEXT: sw t6, 32(a5)
-; RV64IXQCCMP-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-NEXT: sw t4, 24(a5)
-; RV64IXQCCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 20(a5)
-; RV64IXQCCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 16(a5)
-; RV64IXQCCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-NEXT: ld t0, 168(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld t1, 160(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld t2, 152(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld a0, 144(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld a1, 136(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld a2, 128(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld a3, 120(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld a4, 112(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld a5, 104(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld a6, 96(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld a7, 88(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld t3, 80(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld t4, 72(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld t5, 64(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: ld t6, 56(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: lui a0, %hi(var_test_irq)
+; RV64IXQCCMP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64IXQCCMP-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 4(a0)
+; RV64IXQCCMP-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 8(a0)
+; RV64IXQCCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 12(a0)
+; RV64IXQCCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 16(a0)
+; RV64IXQCCMP-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw t3, 20(a0)
+; RV64IXQCCMP-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-NEXT: lw t6, 32(a0)
+; RV64IXQCCMP-NEXT: lw s2, 36(a0)
+; RV64IXQCCMP-NEXT: lw s3, 40(a0)
+; RV64IXQCCMP-NEXT: lw s4, 44(a0)
+; RV64IXQCCMP-NEXT: lw s5, 48(a0)
+; RV64IXQCCMP-NEXT: lw s6, 52(a0)
+; RV64IXQCCMP-NEXT: lw s7, 56(a0)
+; RV64IXQCCMP-NEXT: lw s8, 60(a0)
+; RV64IXQCCMP-NEXT: lw s9, 64(a0)
+; RV64IXQCCMP-NEXT: lw s10, 68(a0)
+; RV64IXQCCMP-NEXT: lw s11, 72(a0)
+; RV64IXQCCMP-NEXT: lw ra, 76(a0)
+; RV64IXQCCMP-NEXT: lw t2, 80(a0)
+; RV64IXQCCMP-NEXT: lw s0, 84(a0)
+; RV64IXQCCMP-NEXT: lw s1, 88(a0)
+; RV64IXQCCMP-NEXT: lw t1, 92(a0)
+; RV64IXQCCMP-NEXT: lw t0, 112(a0)
+; RV64IXQCCMP-NEXT: lw a5, 116(a0)
+; RV64IXQCCMP-NEXT: lw a3, 120(a0)
+; RV64IXQCCMP-NEXT: lw a1, 124(a0)
+; RV64IXQCCMP-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-NEXT: lw a6, 100(a0)
+; RV64IXQCCMP-NEXT: lw a4, 104(a0)
+; RV64IXQCCMP-NEXT: lw a2, 108(a0)
+; RV64IXQCCMP-NEXT: sw a1, 124(a0)
+; RV64IXQCCMP-NEXT: sw a3, 120(a0)
+; RV64IXQCCMP-NEXT: sw a5, 116(a0)
+; RV64IXQCCMP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-NEXT: sw a2, 108(a0)
+; RV64IXQCCMP-NEXT: sw a4, 104(a0)
+; RV64IXQCCMP-NEXT: sw a6, 100(a0)
+; RV64IXQCCMP-NEXT: sw a7, 96(a0)
+; RV64IXQCCMP-NEXT: sw t1, 92(a0)
+; RV64IXQCCMP-NEXT: sw s1, 88(a0)
+; RV64IXQCCMP-NEXT: sw s0, 84(a0)
+; RV64IXQCCMP-NEXT: sw t2, 80(a0)
+; RV64IXQCCMP-NEXT: sw ra, 76(a0)
+; RV64IXQCCMP-NEXT: sw s11, 72(a0)
+; RV64IXQCCMP-NEXT: sw s10, 68(a0)
+; RV64IXQCCMP-NEXT: sw s9, 64(a0)
+; RV64IXQCCMP-NEXT: sw s8, 60(a0)
+; RV64IXQCCMP-NEXT: sw s7, 56(a0)
+; RV64IXQCCMP-NEXT: sw s6, 52(a0)
+; RV64IXQCCMP-NEXT: sw s5, 48(a0)
+; RV64IXQCCMP-NEXT: sw s4, 44(a0)
+; RV64IXQCCMP-NEXT: sw s3, 40(a0)
+; RV64IXQCCMP-NEXT: sw s2, 36(a0)
+; RV64IXQCCMP-NEXT: sw t6, 32(a0)
+; RV64IXQCCMP-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 16(a0)
+; RV64IXQCCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 12(a0)
+; RV64IXQCCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 8(a0)
+; RV64IXQCCMP-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 4(a0)
+; RV64IXQCCMP-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 0(a0)
+; RV64IXQCCMP-NEXT: ld t0, 152(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld t1, 144(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld t2, 136(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld a0, 128(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld a1, 120(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld a2, 112(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld a3, 104(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld a4, 96(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld a5, 88(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld a6, 80(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld a7, 72(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld t3, 64(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld t4, 56(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld t5, 48(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: ld t6, 40(sp) # 8-byte Folded Reload
; RV64IXQCCMP-NEXT: .cfi_restore t0
; RV64IXQCCMP-NEXT: .cfi_restore t1
; RV64IXQCCMP-NEXT: .cfi_restore t2
@@ -2443,7 +2421,7 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IXQCCMP-NEXT: .cfi_restore t4
; RV64IXQCCMP-NEXT: .cfi_restore t5
; RV64IXQCCMP-NEXT: .cfi_restore t6
-; RV64IXQCCMP-NEXT: addi sp, sp, 128
+; RV64IXQCCMP-NEXT: addi sp, sp, 112
; RV64IXQCCMP-NEXT: .cfi_def_cfa_offset 160
; RV64IXQCCMP-NEXT: qc.cm.pop {ra, s0-s11}, 160
; RV64IXQCCMP-NEXT: .cfi_restore ra
@@ -2512,86 +2490,84 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IXQCCMP-FP-NEXT: .cfi_offset t5, -120
; RV32IXQCCMP-FP-NEXT: .cfi_offset t6, -124
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
-; RV32IXQCCMP-FP-NEXT: lui t1, %hi(var_test_irq)
-; RV32IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq)(t1)
-; RV32IXQCCMP-FP-NEXT: sw a0, -128(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+4)(t1)
-; RV32IXQCCMP-FP-NEXT: sw a0, -132(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+8)(t1)
-; RV32IXQCCMP-FP-NEXT: sw a0, -136(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+12)(t1)
-; RV32IXQCCMP-FP-NEXT: sw a0, -140(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: addi a5, t1, %lo(var_test_irq)
-; RV32IXQCCMP-FP-NEXT: lw a0, 16(a5)
-; RV32IXQCCMP-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw a0, 20(a5)
-; RV32IXQCCMP-FP-NEXT: sw a0, -148(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw a0, 24(a5)
-; RV32IXQCCMP-FP-NEXT: sw a0, -152(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-FP-NEXT: lw t6, 32(a5)
-; RV32IXQCCMP-FP-NEXT: lw s2, 36(a5)
-; RV32IXQCCMP-FP-NEXT: lw s3, 40(a5)
-; RV32IXQCCMP-FP-NEXT: lw s4, 44(a5)
-; RV32IXQCCMP-FP-NEXT: lw s5, 48(a5)
-; RV32IXQCCMP-FP-NEXT: lw s6, 52(a5)
-; RV32IXQCCMP-FP-NEXT: lw s7, 56(a5)
-; RV32IXQCCMP-FP-NEXT: lw s8, 60(a5)
-; RV32IXQCCMP-FP-NEXT: lw s9, 64(a5)
-; RV32IXQCCMP-FP-NEXT: lw s10, 68(a5)
-; RV32IXQCCMP-FP-NEXT: lw s11, 72(a5)
-; RV32IXQCCMP-FP-NEXT: lw ra, 76(a5)
-; RV32IXQCCMP-FP-NEXT: lw t4, 80(a5)
-; RV32IXQCCMP-FP-NEXT: lw t3, 84(a5)
-; RV32IXQCCMP-FP-NEXT: lw t2, 88(a5)
-; RV32IXQCCMP-FP-NEXT: lw s1, 92(a5)
-; RV32IXQCCMP-FP-NEXT: lw t0, 112(a5)
-; RV32IXQCCMP-FP-NEXT: lw a4, 116(a5)
-; RV32IXQCCMP-FP-NEXT: lw a3, 120(a5)
-; RV32IXQCCMP-FP-NEXT: lw a0, 124(a5)
-; RV32IXQCCMP-FP-NEXT: lw a7, 96(a5)
-; RV32IXQCCMP-FP-NEXT: lw a6, 100(a5)
-; RV32IXQCCMP-FP-NEXT: lw a2, 104(a5)
-; RV32IXQCCMP-FP-NEXT: lw a1, 108(a5)
-; RV32IXQCCMP-FP-NEXT: sw a0, 124(a5)
-; RV32IXQCCMP-FP-NEXT: sw a3, 120(a5)
-; RV32IXQCCMP-FP-NEXT: sw a4, 116(a5)
-; RV32IXQCCMP-FP-NEXT: sw t0, 112(a5)
-; RV32IXQCCMP-FP-NEXT: sw a1, 108(a5)
-; RV32IXQCCMP-FP-NEXT: sw a2, 104(a5)
-; RV32IXQCCMP-FP-NEXT: sw a6, 100(a5)
-; RV32IXQCCMP-FP-NEXT: sw a7, 96(a5)
-; RV32IXQCCMP-FP-NEXT: sw s1, 92(a5)
-; RV32IXQCCMP-FP-NEXT: sw t2, 88(a5)
-; RV32IXQCCMP-FP-NEXT: sw t3, 84(a5)
-; RV32IXQCCMP-FP-NEXT: sw t4, 80(a5)
-; RV32IXQCCMP-FP-NEXT: sw ra, 76(a5)
-; RV32IXQCCMP-FP-NEXT: sw s11, 72(a5)
-; RV32IXQCCMP-FP-NEXT: sw s10, 68(a5)
-; RV32IXQCCMP-FP-NEXT: sw s9, 64(a5)
-; RV32IXQCCMP-FP-NEXT: sw s8, 60(a5)
-; RV32IXQCCMP-FP-NEXT: sw s7, 56(a5)
-; RV32IXQCCMP-FP-NEXT: sw s6, 52(a5)
-; RV32IXQCCMP-FP-NEXT: sw s5, 48(a5)
-; RV32IXQCCMP-FP-NEXT: sw s4, 44(a5)
-; RV32IXQCCMP-FP-NEXT: sw s3, 40(a5)
-; RV32IXQCCMP-FP-NEXT: sw s2, 36(a5)
-; RV32IXQCCMP-FP-NEXT: sw t6, 32(a5)
-; RV32IXQCCMP-FP-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-FP-NEXT: lw a0, -152(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, 24(a5)
-; RV32IXQCCMP-FP-NEXT: lw a0, -148(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, 20(a5)
-; RV32IXQCCMP-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, 16(a5)
-; RV32IXQCCMP-FP-NEXT: lw a0, -140(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+12)(t1)
-; RV32IXQCCMP-FP-NEXT: lw a0, -136(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+8)(t1)
-; RV32IXQCCMP-FP-NEXT: lw a0, -132(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+4)(t1)
-; RV32IXQCCMP-FP-NEXT: lw a0, -128(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq)(t1)
+; RV32IXQCCMP-FP-NEXT: lui a0, %hi(var_test_irq)
+; RV32IXQCCMP-FP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32IXQCCMP-FP-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -128(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw a1, 4(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -132(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw a1, 8(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -136(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw a1, 12(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -140(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw a1, 16(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -144(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw a1, 20(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -148(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-FP-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-FP-NEXT: lw t6, 32(a0)
+; RV32IXQCCMP-FP-NEXT: lw s2, 36(a0)
+; RV32IXQCCMP-FP-NEXT: lw s3, 40(a0)
+; RV32IXQCCMP-FP-NEXT: lw s4, 44(a0)
+; RV32IXQCCMP-FP-NEXT: lw s5, 48(a0)
+; RV32IXQCCMP-FP-NEXT: lw s6, 52(a0)
+; RV32IXQCCMP-FP-NEXT: lw s7, 56(a0)
+; RV32IXQCCMP-FP-NEXT: lw s8, 60(a0)
+; RV32IXQCCMP-FP-NEXT: lw s9, 64(a0)
+; RV32IXQCCMP-FP-NEXT: lw s10, 68(a0)
+; RV32IXQCCMP-FP-NEXT: lw s11, 72(a0)
+; RV32IXQCCMP-FP-NEXT: lw ra, 76(a0)
+; RV32IXQCCMP-FP-NEXT: lw s1, 80(a0)
+; RV32IXQCCMP-FP-NEXT: lw t3, 84(a0)
+; RV32IXQCCMP-FP-NEXT: lw t2, 88(a0)
+; RV32IXQCCMP-FP-NEXT: lw t1, 92(a0)
+; RV32IXQCCMP-FP-NEXT: lw t0, 112(a0)
+; RV32IXQCCMP-FP-NEXT: lw a6, 116(a0)
+; RV32IXQCCMP-FP-NEXT: lw a4, 120(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, 124(a0)
+; RV32IXQCCMP-FP-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-FP-NEXT: lw a5, 100(a0)
+; RV32IXQCCMP-FP-NEXT: lw a3, 104(a0)
+; RV32IXQCCMP-FP-NEXT: lw a2, 108(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, 124(a0)
+; RV32IXQCCMP-FP-NEXT: sw a4, 120(a0)
+; RV32IXQCCMP-FP-NEXT: sw a6, 116(a0)
+; RV32IXQCCMP-FP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-FP-NEXT: sw a2, 108(a0)
+; RV32IXQCCMP-FP-NEXT: sw a3, 104(a0)
+; RV32IXQCCMP-FP-NEXT: sw a5, 100(a0)
+; RV32IXQCCMP-FP-NEXT: sw a7, 96(a0)
+; RV32IXQCCMP-FP-NEXT: sw t1, 92(a0)
+; RV32IXQCCMP-FP-NEXT: sw t2, 88(a0)
+; RV32IXQCCMP-FP-NEXT: sw t3, 84(a0)
+; RV32IXQCCMP-FP-NEXT: sw s1, 80(a0)
+; RV32IXQCCMP-FP-NEXT: sw ra, 76(a0)
+; RV32IXQCCMP-FP-NEXT: sw s11, 72(a0)
+; RV32IXQCCMP-FP-NEXT: sw s10, 68(a0)
+; RV32IXQCCMP-FP-NEXT: sw s9, 64(a0)
+; RV32IXQCCMP-FP-NEXT: sw s8, 60(a0)
+; RV32IXQCCMP-FP-NEXT: sw s7, 56(a0)
+; RV32IXQCCMP-FP-NEXT: sw s6, 52(a0)
+; RV32IXQCCMP-FP-NEXT: sw s5, 48(a0)
+; RV32IXQCCMP-FP-NEXT: sw s4, 44(a0)
+; RV32IXQCCMP-FP-NEXT: sw s3, 40(a0)
+; RV32IXQCCMP-FP-NEXT: sw s2, 36(a0)
+; RV32IXQCCMP-FP-NEXT: sw t6, 32(a0)
+; RV32IXQCCMP-FP-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-FP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -148(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 20(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -144(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 16(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -140(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 12(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -136(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 8(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -132(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 4(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -128(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 0(a0)
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 160
; RV32IXQCCMP-FP-NEXT: lw t0, 92(sp) # 4-byte Folded Reload
; RV32IXQCCMP-FP-NEXT: lw t1, 88(sp) # 4-byte Folded Reload
@@ -2692,86 +2668,84 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IXQCCMP-FP-NEXT: .cfi_offset t5, -224
; RV64IXQCCMP-FP-NEXT: .cfi_offset t6, -232
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
-; RV64IXQCCMP-FP-NEXT: lui t1, %hi(var_test_irq)
-; RV64IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq)(t1)
-; RV64IXQCCMP-FP-NEXT: sd a0, -240(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+4)(t1)
-; RV64IXQCCMP-FP-NEXT: sd a0, -248(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+8)(t1)
-; RV64IXQCCMP-FP-NEXT: sd a0, -256(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+12)(t1)
-; RV64IXQCCMP-FP-NEXT: sd a0, -264(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: addi a5, t1, %lo(var_test_irq)
-; RV64IXQCCMP-FP-NEXT: lw a0, 16(a5)
-; RV64IXQCCMP-FP-NEXT: sd a0, -272(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw a0, 20(a5)
-; RV64IXQCCMP-FP-NEXT: sd a0, -280(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw a0, 24(a5)
-; RV64IXQCCMP-FP-NEXT: sd a0, -288(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-FP-NEXT: lw t6, 32(a5)
-; RV64IXQCCMP-FP-NEXT: lw s2, 36(a5)
-; RV64IXQCCMP-FP-NEXT: lw s3, 40(a5)
-; RV64IXQCCMP-FP-NEXT: lw s4, 44(a5)
-; RV64IXQCCMP-FP-NEXT: lw s5, 48(a5)
-; RV64IXQCCMP-FP-NEXT: lw s6, 52(a5)
-; RV64IXQCCMP-FP-NEXT: lw s7, 56(a5)
-; RV64IXQCCMP-FP-NEXT: lw s8, 60(a5)
-; RV64IXQCCMP-FP-NEXT: lw s9, 64(a5)
-; RV64IXQCCMP-FP-NEXT: lw s10, 68(a5)
-; RV64IXQCCMP-FP-NEXT: lw s11, 72(a5)
-; RV64IXQCCMP-FP-NEXT: lw ra, 76(a5)
-; RV64IXQCCMP-FP-NEXT: lw t4, 80(a5)
-; RV64IXQCCMP-FP-NEXT: lw t3, 84(a5)
-; RV64IXQCCMP-FP-NEXT: lw t2, 88(a5)
-; RV64IXQCCMP-FP-NEXT: lw s1, 92(a5)
-; RV64IXQCCMP-FP-NEXT: lw t0, 112(a5)
-; RV64IXQCCMP-FP-NEXT: lw a4, 116(a5)
-; RV64IXQCCMP-FP-NEXT: lw a3, 120(a5)
-; RV64IXQCCMP-FP-NEXT: lw a0, 124(a5)
-; RV64IXQCCMP-FP-NEXT: lw a7, 96(a5)
-; RV64IXQCCMP-FP-NEXT: lw a6, 100(a5)
-; RV64IXQCCMP-FP-NEXT: lw a2, 104(a5)
-; RV64IXQCCMP-FP-NEXT: lw a1, 108(a5)
-; RV64IXQCCMP-FP-NEXT: sw a0, 124(a5)
-; RV64IXQCCMP-FP-NEXT: sw a3, 120(a5)
-; RV64IXQCCMP-FP-NEXT: sw a4, 116(a5)
-; RV64IXQCCMP-FP-NEXT: sw t0, 112(a5)
-; RV64IXQCCMP-FP-NEXT: sw a1, 108(a5)
-; RV64IXQCCMP-FP-NEXT: sw a2, 104(a5)
-; RV64IXQCCMP-FP-NEXT: sw a6, 100(a5)
-; RV64IXQCCMP-FP-NEXT: sw a7, 96(a5)
-; RV64IXQCCMP-FP-NEXT: sw s1, 92(a5)
-; RV64IXQCCMP-FP-NEXT: sw t2, 88(a5)
-; RV64IXQCCMP-FP-NEXT: sw t3, 84(a5)
-; RV64IXQCCMP-FP-NEXT: sw t4, 80(a5)
-; RV64IXQCCMP-FP-NEXT: sw ra, 76(a5)
-; RV64IXQCCMP-FP-NEXT: sw s11, 72(a5)
-; RV64IXQCCMP-FP-NEXT: sw s10, 68(a5)
-; RV64IXQCCMP-FP-NEXT: sw s9, 64(a5)
-; RV64IXQCCMP-FP-NEXT: sw s8, 60(a5)
-; RV64IXQCCMP-FP-NEXT: sw s7, 56(a5)
-; RV64IXQCCMP-FP-NEXT: sw s6, 52(a5)
-; RV64IXQCCMP-FP-NEXT: sw s5, 48(a5)
-; RV64IXQCCMP-FP-NEXT: sw s4, 44(a5)
-; RV64IXQCCMP-FP-NEXT: sw s3, 40(a5)
-; RV64IXQCCMP-FP-NEXT: sw s2, 36(a5)
-; RV64IXQCCMP-FP-NEXT: sw t6, 32(a5)
-; RV64IXQCCMP-FP-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-FP-NEXT: ld a0, -288(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, 24(a5)
-; RV64IXQCCMP-FP-NEXT: ld a0, -280(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, 20(a5)
-; RV64IXQCCMP-FP-NEXT: ld a0, -272(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, 16(a5)
-; RV64IXQCCMP-FP-NEXT: ld a0, -264(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+12)(t1)
-; RV64IXQCCMP-FP-NEXT: ld a0, -256(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+8)(t1)
-; RV64IXQCCMP-FP-NEXT: ld a0, -248(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+4)(t1)
-; RV64IXQCCMP-FP-NEXT: ld a0, -240(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq)(t1)
+; RV64IXQCCMP-FP-NEXT: lui a0, %hi(var_test_irq)
+; RV64IXQCCMP-FP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64IXQCCMP-FP-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -240(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw a1, 4(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -248(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw a1, 8(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -256(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw a1, 12(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -264(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw a1, 16(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -272(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw a1, 20(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -280(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-FP-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-FP-NEXT: lw t6, 32(a0)
+; RV64IXQCCMP-FP-NEXT: lw s2, 36(a0)
+; RV64IXQCCMP-FP-NEXT: lw s3, 40(a0)
+; RV64IXQCCMP-FP-NEXT: lw s4, 44(a0)
+; RV64IXQCCMP-FP-NEXT: lw s5, 48(a0)
+; RV64IXQCCMP-FP-NEXT: lw s6, 52(a0)
+; RV64IXQCCMP-FP-NEXT: lw s7, 56(a0)
+; RV64IXQCCMP-FP-NEXT: lw s8, 60(a0)
+; RV64IXQCCMP-FP-NEXT: lw s9, 64(a0)
+; RV64IXQCCMP-FP-NEXT: lw s10, 68(a0)
+; RV64IXQCCMP-FP-NEXT: lw s11, 72(a0)
+; RV64IXQCCMP-FP-NEXT: lw ra, 76(a0)
+; RV64IXQCCMP-FP-NEXT: lw s1, 80(a0)
+; RV64IXQCCMP-FP-NEXT: lw t3, 84(a0)
+; RV64IXQCCMP-FP-NEXT: lw t2, 88(a0)
+; RV64IXQCCMP-FP-NEXT: lw t1, 92(a0)
+; RV64IXQCCMP-FP-NEXT: lw t0, 112(a0)
+; RV64IXQCCMP-FP-NEXT: lw a6, 116(a0)
+; RV64IXQCCMP-FP-NEXT: lw a4, 120(a0)
+; RV64IXQCCMP-FP-NEXT: lw a1, 124(a0)
+; RV64IXQCCMP-FP-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-FP-NEXT: lw a5, 100(a0)
+; RV64IXQCCMP-FP-NEXT: lw a3, 104(a0)
+; RV64IXQCCMP-FP-NEXT: lw a2, 108(a0)
+; RV64IXQCCMP-FP-NEXT: sw a1, 124(a0)
+; RV64IXQCCMP-FP-NEXT: sw a4, 120(a0)
+; RV64IXQCCMP-FP-NEXT: sw a6, 116(a0)
+; RV64IXQCCMP-FP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-FP-NEXT: sw a2, 108(a0)
+; RV64IXQCCMP-FP-NEXT: sw a3, 104(a0)
+; RV64IXQCCMP-FP-NEXT: sw a5, 100(a0)
+; RV64IXQCCMP-FP-NEXT: sw a7, 96(a0)
+; RV64IXQCCMP-FP-NEXT: sw t1, 92(a0)
+; RV64IXQCCMP-FP-NEXT: sw t2, 88(a0)
+; RV64IXQCCMP-FP-NEXT: sw t3, 84(a0)
+; RV64IXQCCMP-FP-NEXT: sw s1, 80(a0)
+; RV64IXQCCMP-FP-NEXT: sw ra, 76(a0)
+; RV64IXQCCMP-FP-NEXT: sw s11, 72(a0)
+; RV64IXQCCMP-FP-NEXT: sw s10, 68(a0)
+; RV64IXQCCMP-FP-NEXT: sw s9, 64(a0)
+; RV64IXQCCMP-FP-NEXT: sw s8, 60(a0)
+; RV64IXQCCMP-FP-NEXT: sw s7, 56(a0)
+; RV64IXQCCMP-FP-NEXT: sw s6, 52(a0)
+; RV64IXQCCMP-FP-NEXT: sw s5, 48(a0)
+; RV64IXQCCMP-FP-NEXT: sw s4, 44(a0)
+; RV64IXQCCMP-FP-NEXT: sw s3, 40(a0)
+; RV64IXQCCMP-FP-NEXT: sw s2, 36(a0)
+; RV64IXQCCMP-FP-NEXT: sw t6, 32(a0)
+; RV64IXQCCMP-FP-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-FP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -280(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 20(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -272(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 16(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -264(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 12(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -256(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 8(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -248(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 4(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -240(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 0(a0)
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 288
; RV64IXQCCMP-FP-NEXT: ld t0, 168(sp) # 8-byte Folded Reload
; RV64IXQCCMP-FP-NEXT: ld t1, 160(sp) # 8-byte Folded Reload
@@ -2839,23 +2813,23 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IXQCCMP-SR-NEXT: .cfi_offset s9, -44
; RV32IXQCCMP-SR-NEXT: .cfi_offset s10, -48
; RV32IXQCCMP-SR-NEXT: .cfi_offset s11, -52
-; RV32IXQCCMP-SR-NEXT: addi sp, sp, -48
-; RV32IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 160
-; RV32IXQCCMP-SR-NEXT: sw t0, 92(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw t1, 88(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw t2, 84(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw a1, 76(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw a2, 72(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw a3, 68(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw a4, 64(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw a5, 60(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw a6, 56(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw a7, 52(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw t3, 48(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw t4, 44(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw t5, 40(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: sw t6, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: addi sp, sp, -32
+; RV32IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 144
+; RV32IXQCCMP-SR-NEXT: sw t0, 76(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw t1, 72(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw t2, 68(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw a1, 60(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw a2, 56(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw a3, 52(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw a4, 48(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw a5, 44(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw a6, 40(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw a7, 36(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw t3, 32(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw t4, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw t5, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: sw t6, 20(sp) # 4-byte Folded Spill
; RV32IXQCCMP-SR-NEXT: .cfi_offset t0, -68
; RV32IXQCCMP-SR-NEXT: .cfi_offset t1, -72
; RV32IXQCCMP-SR-NEXT: .cfi_offset t2, -76
@@ -2871,99 +2845,97 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IXQCCMP-SR-NEXT: .cfi_offset t4, -116
; RV32IXQCCMP-SR-NEXT: .cfi_offset t5, -120
; RV32IXQCCMP-SR-NEXT: .cfi_offset t6, -124
-; RV32IXQCCMP-SR-NEXT: lui t0, %hi(var_test_irq)
-; RV32IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-SR-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-SR-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-SR-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-SR-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV32IXQCCMP-SR-NEXT: lw a0, 16(a5)
-; RV32IXQCCMP-SR-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw a0, 20(a5)
-; RV32IXQCCMP-SR-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw t4, 24(a5)
-; RV32IXQCCMP-SR-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-SR-NEXT: lw t6, 32(a5)
-; RV32IXQCCMP-SR-NEXT: lw s2, 36(a5)
-; RV32IXQCCMP-SR-NEXT: lw s3, 40(a5)
-; RV32IXQCCMP-SR-NEXT: lw s4, 44(a5)
-; RV32IXQCCMP-SR-NEXT: lw s5, 48(a5)
-; RV32IXQCCMP-SR-NEXT: lw s6, 52(a5)
-; RV32IXQCCMP-SR-NEXT: lw s7, 56(a5)
-; RV32IXQCCMP-SR-NEXT: lw s8, 60(a5)
-; RV32IXQCCMP-SR-NEXT: lw s9, 64(a5)
-; RV32IXQCCMP-SR-NEXT: lw s10, 68(a5)
-; RV32IXQCCMP-SR-NEXT: lw s11, 72(a5)
-; RV32IXQCCMP-SR-NEXT: lw ra, 76(a5)
-; RV32IXQCCMP-SR-NEXT: lw s1, 80(a5)
-; RV32IXQCCMP-SR-NEXT: lw t3, 84(a5)
-; RV32IXQCCMP-SR-NEXT: lw t2, 88(a5)
-; RV32IXQCCMP-SR-NEXT: lw t1, 92(a5)
-; RV32IXQCCMP-SR-NEXT: lw a7, 112(a5)
-; RV32IXQCCMP-SR-NEXT: lw s0, 116(a5)
-; RV32IXQCCMP-SR-NEXT: lw a3, 120(a5)
-; RV32IXQCCMP-SR-NEXT: lw a0, 124(a5)
-; RV32IXQCCMP-SR-NEXT: lw a6, 96(a5)
-; RV32IXQCCMP-SR-NEXT: lw a4, 100(a5)
-; RV32IXQCCMP-SR-NEXT: lw a2, 104(a5)
-; RV32IXQCCMP-SR-NEXT: lw a1, 108(a5)
-; RV32IXQCCMP-SR-NEXT: sw a0, 124(a5)
-; RV32IXQCCMP-SR-NEXT: sw a3, 120(a5)
-; RV32IXQCCMP-SR-NEXT: sw s0, 116(a5)
-; RV32IXQCCMP-SR-NEXT: sw a7, 112(a5)
-; RV32IXQCCMP-SR-NEXT: sw a1, 108(a5)
-; RV32IXQCCMP-SR-NEXT: sw a2, 104(a5)
-; RV32IXQCCMP-SR-NEXT: sw a4, 100(a5)
-; RV32IXQCCMP-SR-NEXT: sw a6, 96(a5)
-; RV32IXQCCMP-SR-NEXT: sw t1, 92(a5)
-; RV32IXQCCMP-SR-NEXT: sw t2, 88(a5)
-; RV32IXQCCMP-SR-NEXT: sw t3, 84(a5)
-; RV32IXQCCMP-SR-NEXT: sw s1, 80(a5)
-; RV32IXQCCMP-SR-NEXT: sw ra, 76(a5)
-; RV32IXQCCMP-SR-NEXT: sw s11, 72(a5)
-; RV32IXQCCMP-SR-NEXT: sw s10, 68(a5)
-; RV32IXQCCMP-SR-NEXT: sw s9, 64(a5)
-; RV32IXQCCMP-SR-NEXT: sw s8, 60(a5)
-; RV32IXQCCMP-SR-NEXT: sw s7, 56(a5)
-; RV32IXQCCMP-SR-NEXT: sw s6, 52(a5)
-; RV32IXQCCMP-SR-NEXT: sw s5, 48(a5)
-; RV32IXQCCMP-SR-NEXT: sw s4, 44(a5)
-; RV32IXQCCMP-SR-NEXT: sw s3, 40(a5)
-; RV32IXQCCMP-SR-NEXT: sw s2, 36(a5)
-; RV32IXQCCMP-SR-NEXT: sw t6, 32(a5)
-; RV32IXQCCMP-SR-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-SR-NEXT: sw t4, 24(a5)
-; RV32IXQCCMP-SR-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, 20(a5)
-; RV32IXQCCMP-SR-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, 16(a5)
-; RV32IXQCCMP-SR-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-SR-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-SR-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-SR-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-SR-NEXT: lw t0, 92(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw t1, 88(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw t2, 84(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw a1, 76(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw a2, 72(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw a3, 68(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw a4, 64(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw a5, 60(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw a6, 56(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw a7, 52(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw t3, 48(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw t4, 44(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw t5, 40(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: lw t6, 36(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lui a0, %hi(var_test_irq)
+; RV32IXQCCMP-SR-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32IXQCCMP-SR-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: lw a1, 4(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: lw a1, 8(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 8(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: lw a1, 12(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: lw a1, 16(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: lw t3, 20(a0)
+; RV32IXQCCMP-SR-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-SR-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-SR-NEXT: lw t6, 32(a0)
+; RV32IXQCCMP-SR-NEXT: lw s2, 36(a0)
+; RV32IXQCCMP-SR-NEXT: lw s3, 40(a0)
+; RV32IXQCCMP-SR-NEXT: lw s4, 44(a0)
+; RV32IXQCCMP-SR-NEXT: lw s5, 48(a0)
+; RV32IXQCCMP-SR-NEXT: lw s6, 52(a0)
+; RV32IXQCCMP-SR-NEXT: lw s7, 56(a0)
+; RV32IXQCCMP-SR-NEXT: lw s8, 60(a0)
+; RV32IXQCCMP-SR-NEXT: lw s9, 64(a0)
+; RV32IXQCCMP-SR-NEXT: lw s10, 68(a0)
+; RV32IXQCCMP-SR-NEXT: lw s11, 72(a0)
+; RV32IXQCCMP-SR-NEXT: lw ra, 76(a0)
+; RV32IXQCCMP-SR-NEXT: lw t2, 80(a0)
+; RV32IXQCCMP-SR-NEXT: lw s0, 84(a0)
+; RV32IXQCCMP-SR-NEXT: lw s1, 88(a0)
+; RV32IXQCCMP-SR-NEXT: lw t1, 92(a0)
+; RV32IXQCCMP-SR-NEXT: lw t0, 112(a0)
+; RV32IXQCCMP-SR-NEXT: lw a5, 116(a0)
+; RV32IXQCCMP-SR-NEXT: lw a3, 120(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 124(a0)
+; RV32IXQCCMP-SR-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-SR-NEXT: lw a6, 100(a0)
+; RV32IXQCCMP-SR-NEXT: lw a4, 104(a0)
+; RV32IXQCCMP-SR-NEXT: lw a2, 108(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 124(a0)
+; RV32IXQCCMP-SR-NEXT: sw a3, 120(a0)
+; RV32IXQCCMP-SR-NEXT: sw a5, 116(a0)
+; RV32IXQCCMP-SR-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-SR-NEXT: sw a2, 108(a0)
+; RV32IXQCCMP-SR-NEXT: sw a4, 104(a0)
+; RV32IXQCCMP-SR-NEXT: sw a6, 100(a0)
+; RV32IXQCCMP-SR-NEXT: sw a7, 96(a0)
+; RV32IXQCCMP-SR-NEXT: sw t1, 92(a0)
+; RV32IXQCCMP-SR-NEXT: sw s1, 88(a0)
+; RV32IXQCCMP-SR-NEXT: sw s0, 84(a0)
+; RV32IXQCCMP-SR-NEXT: sw t2, 80(a0)
+; RV32IXQCCMP-SR-NEXT: sw ra, 76(a0)
+; RV32IXQCCMP-SR-NEXT: sw s11, 72(a0)
+; RV32IXQCCMP-SR-NEXT: sw s10, 68(a0)
+; RV32IXQCCMP-SR-NEXT: sw s9, 64(a0)
+; RV32IXQCCMP-SR-NEXT: sw s8, 60(a0)
+; RV32IXQCCMP-SR-NEXT: sw s7, 56(a0)
+; RV32IXQCCMP-SR-NEXT: sw s6, 52(a0)
+; RV32IXQCCMP-SR-NEXT: sw s5, 48(a0)
+; RV32IXQCCMP-SR-NEXT: sw s4, 44(a0)
+; RV32IXQCCMP-SR-NEXT: sw s3, 40(a0)
+; RV32IXQCCMP-SR-NEXT: sw s2, 36(a0)
+; RV32IXQCCMP-SR-NEXT: sw t6, 32(a0)
+; RV32IXQCCMP-SR-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-SR-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-SR-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: sw a1, 16(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: sw a1, 12(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 8(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: sw a1, 8(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: sw a1, 4(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: sw a1, 0(a0)
+; RV32IXQCCMP-SR-NEXT: lw t0, 76(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw t1, 72(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw t2, 68(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw a1, 60(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw a2, 56(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw a3, 52(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw a4, 48(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw a5, 44(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw a6, 40(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw a7, 36(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw t3, 32(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw t4, 28(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw t5, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: lw t6, 20(sp) # 4-byte Folded Reload
; RV32IXQCCMP-SR-NEXT: .cfi_restore t0
; RV32IXQCCMP-SR-NEXT: .cfi_restore t1
; RV32IXQCCMP-SR-NEXT: .cfi_restore t2
@@ -2979,7 +2951,7 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IXQCCMP-SR-NEXT: .cfi_restore t4
; RV32IXQCCMP-SR-NEXT: .cfi_restore t5
; RV32IXQCCMP-SR-NEXT: .cfi_restore t6
-; RV32IXQCCMP-SR-NEXT: addi sp, sp, 48
+; RV32IXQCCMP-SR-NEXT: addi sp, sp, 32
; RV32IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 112
; RV32IXQCCMP-SR-NEXT: qc.cm.pop {ra, s0-s11}, 112
; RV32IXQCCMP-SR-NEXT: .cfi_restore ra
@@ -3015,23 +2987,23 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IXQCCMP-SR-NEXT: .cfi_offset s9, -88
; RV64IXQCCMP-SR-NEXT: .cfi_offset s10, -96
; RV64IXQCCMP-SR-NEXT: .cfi_offset s11, -104
-; RV64IXQCCMP-SR-NEXT: addi sp, sp, -128
-; RV64IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 288
-; RV64IXQCCMP-SR-NEXT: sd t0, 168(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd t1, 160(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd t2, 152(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd a1, 136(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd a2, 128(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd a3, 120(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd a4, 112(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd a5, 104(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd a6, 96(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd a7, 88(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd t3, 80(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd t4, 72(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd t5, 64(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: sd t6, 56(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: addi sp, sp, -112
+; RV64IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 272
+; RV64IXQCCMP-SR-NEXT: sd t0, 152(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd t1, 144(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd t2, 136(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd a1, 120(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd a2, 112(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd a3, 104(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd a4, 96(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd a5, 88(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd a6, 80(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd a7, 72(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd t3, 64(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd t4, 56(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd t5, 48(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: sd t6, 40(sp) # 8-byte Folded Spill
; RV64IXQCCMP-SR-NEXT: .cfi_offset t0, -120
; RV64IXQCCMP-SR-NEXT: .cfi_offset t1, -128
; RV64IXQCCMP-SR-NEXT: .cfi_offset t2, -136
@@ -3047,99 +3019,97 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IXQCCMP-SR-NEXT: .cfi_offset t4, -216
; RV64IXQCCMP-SR-NEXT: .cfi_offset t5, -224
; RV64IXQCCMP-SR-NEXT: .cfi_offset t6, -232
-; RV64IXQCCMP-SR-NEXT: lui t0, %hi(var_test_irq)
-; RV64IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-SR-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-SR-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-SR-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-SR-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV64IXQCCMP-SR-NEXT: lw a0, 16(a5)
-; RV64IXQCCMP-SR-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw a0, 20(a5)
-; RV64IXQCCMP-SR-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw t4, 24(a5)
-; RV64IXQCCMP-SR-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-SR-NEXT: lw t6, 32(a5)
-; RV64IXQCCMP-SR-NEXT: lw s2, 36(a5)
-; RV64IXQCCMP-SR-NEXT: lw s3, 40(a5)
-; RV64IXQCCMP-SR-NEXT: lw s4, 44(a5)
-; RV64IXQCCMP-SR-NEXT: lw s5, 48(a5)
-; RV64IXQCCMP-SR-NEXT: lw s6, 52(a5)
-; RV64IXQCCMP-SR-NEXT: lw s7, 56(a5)
-; RV64IXQCCMP-SR-NEXT: lw s8, 60(a5)
-; RV64IXQCCMP-SR-NEXT: lw s9, 64(a5)
-; RV64IXQCCMP-SR-NEXT: lw s10, 68(a5)
-; RV64IXQCCMP-SR-NEXT: lw s11, 72(a5)
-; RV64IXQCCMP-SR-NEXT: lw ra, 76(a5)
-; RV64IXQCCMP-SR-NEXT: lw s1, 80(a5)
-; RV64IXQCCMP-SR-NEXT: lw t3, 84(a5)
-; RV64IXQCCMP-SR-NEXT: lw t2, 88(a5)
-; RV64IXQCCMP-SR-NEXT: lw t1, 92(a5)
-; RV64IXQCCMP-SR-NEXT: lw a7, 112(a5)
-; RV64IXQCCMP-SR-NEXT: lw s0, 116(a5)
-; RV64IXQCCMP-SR-NEXT: lw a3, 120(a5)
-; RV64IXQCCMP-SR-NEXT: lw a0, 124(a5)
-; RV64IXQCCMP-SR-NEXT: lw a6, 96(a5)
-; RV64IXQCCMP-SR-NEXT: lw a4, 100(a5)
-; RV64IXQCCMP-SR-NEXT: lw a2, 104(a5)
-; RV64IXQCCMP-SR-NEXT: lw a1, 108(a5)
-; RV64IXQCCMP-SR-NEXT: sw a0, 124(a5)
-; RV64IXQCCMP-SR-NEXT: sw a3, 120(a5)
-; RV64IXQCCMP-SR-NEXT: sw s0, 116(a5)
-; RV64IXQCCMP-SR-NEXT: sw a7, 112(a5)
-; RV64IXQCCMP-SR-NEXT: sw a1, 108(a5)
-; RV64IXQCCMP-SR-NEXT: sw a2, 104(a5)
-; RV64IXQCCMP-SR-NEXT: sw a4, 100(a5)
-; RV64IXQCCMP-SR-NEXT: sw a6, 96(a5)
-; RV64IXQCCMP-SR-NEXT: sw t1, 92(a5)
-; RV64IXQCCMP-SR-NEXT: sw t2, 88(a5)
-; RV64IXQCCMP-SR-NEXT: sw t3, 84(a5)
-; RV64IXQCCMP-SR-NEXT: sw s1, 80(a5)
-; RV64IXQCCMP-SR-NEXT: sw ra, 76(a5)
-; RV64IXQCCMP-SR-NEXT: sw s11, 72(a5)
-; RV64IXQCCMP-SR-NEXT: sw s10, 68(a5)
-; RV64IXQCCMP-SR-NEXT: sw s9, 64(a5)
-; RV64IXQCCMP-SR-NEXT: sw s8, 60(a5)
-; RV64IXQCCMP-SR-NEXT: sw s7, 56(a5)
-; RV64IXQCCMP-SR-NEXT: sw s6, 52(a5)
-; RV64IXQCCMP-SR-NEXT: sw s5, 48(a5)
-; RV64IXQCCMP-SR-NEXT: sw s4, 44(a5)
-; RV64IXQCCMP-SR-NEXT: sw s3, 40(a5)
-; RV64IXQCCMP-SR-NEXT: sw s2, 36(a5)
-; RV64IXQCCMP-SR-NEXT: sw t6, 32(a5)
-; RV64IXQCCMP-SR-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-SR-NEXT: sw t4, 24(a5)
-; RV64IXQCCMP-SR-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, 20(a5)
-; RV64IXQCCMP-SR-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, 16(a5)
-; RV64IXQCCMP-SR-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-SR-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-SR-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-SR-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-SR-NEXT: ld t0, 168(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld t1, 160(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld t2, 152(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld a0, 144(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld a1, 136(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld a2, 128(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld a3, 120(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld a4, 112(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld a5, 104(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld a6, 96(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld a7, 88(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld t3, 80(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld t4, 72(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld t5, 64(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: ld t6, 56(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: lui a0, %hi(var_test_irq)
+; RV64IXQCCMP-SR-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64IXQCCMP-SR-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-SR-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: lw a1, 4(a0)
+; RV64IXQCCMP-SR-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: lw a1, 8(a0)
+; RV64IXQCCMP-SR-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: lw a1, 12(a0)
+; RV64IXQCCMP-SR-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: lw a1, 16(a0)
+; RV64IXQCCMP-SR-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: lw t3, 20(a0)
+; RV64IXQCCMP-SR-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-SR-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-SR-NEXT: lw t6, 32(a0)
+; RV64IXQCCMP-SR-NEXT: lw s2, 36(a0)
+; RV64IXQCCMP-SR-NEXT: lw s3, 40(a0)
+; RV64IXQCCMP-SR-NEXT: lw s4, 44(a0)
+; RV64IXQCCMP-SR-NEXT: lw s5, 48(a0)
+; RV64IXQCCMP-SR-NEXT: lw s6, 52(a0)
+; RV64IXQCCMP-SR-NEXT: lw s7, 56(a0)
+; RV64IXQCCMP-SR-NEXT: lw s8, 60(a0)
+; RV64IXQCCMP-SR-NEXT: lw s9, 64(a0)
+; RV64IXQCCMP-SR-NEXT: lw s10, 68(a0)
+; RV64IXQCCMP-SR-NEXT: lw s11, 72(a0)
+; RV64IXQCCMP-SR-NEXT: lw ra, 76(a0)
+; RV64IXQCCMP-SR-NEXT: lw t2, 80(a0)
+; RV64IXQCCMP-SR-NEXT: lw s0, 84(a0)
+; RV64IXQCCMP-SR-NEXT: lw s1, 88(a0)
+; RV64IXQCCMP-SR-NEXT: lw t1, 92(a0)
+; RV64IXQCCMP-SR-NEXT: lw t0, 112(a0)
+; RV64IXQCCMP-SR-NEXT: lw a5, 116(a0)
+; RV64IXQCCMP-SR-NEXT: lw a3, 120(a0)
+; RV64IXQCCMP-SR-NEXT: lw a1, 124(a0)
+; RV64IXQCCMP-SR-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-SR-NEXT: lw a6, 100(a0)
+; RV64IXQCCMP-SR-NEXT: lw a4, 104(a0)
+; RV64IXQCCMP-SR-NEXT: lw a2, 108(a0)
+; RV64IXQCCMP-SR-NEXT: sw a1, 124(a0)
+; RV64IXQCCMP-SR-NEXT: sw a3, 120(a0)
+; RV64IXQCCMP-SR-NEXT: sw a5, 116(a0)
+; RV64IXQCCMP-SR-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-SR-NEXT: sw a2, 108(a0)
+; RV64IXQCCMP-SR-NEXT: sw a4, 104(a0)
+; RV64IXQCCMP-SR-NEXT: sw a6, 100(a0)
+; RV64IXQCCMP-SR-NEXT: sw a7, 96(a0)
+; RV64IXQCCMP-SR-NEXT: sw t1, 92(a0)
+; RV64IXQCCMP-SR-NEXT: sw s1, 88(a0)
+; RV64IXQCCMP-SR-NEXT: sw s0, 84(a0)
+; RV64IXQCCMP-SR-NEXT: sw t2, 80(a0)
+; RV64IXQCCMP-SR-NEXT: sw ra, 76(a0)
+; RV64IXQCCMP-SR-NEXT: sw s11, 72(a0)
+; RV64IXQCCMP-SR-NEXT: sw s10, 68(a0)
+; RV64IXQCCMP-SR-NEXT: sw s9, 64(a0)
+; RV64IXQCCMP-SR-NEXT: sw s8, 60(a0)
+; RV64IXQCCMP-SR-NEXT: sw s7, 56(a0)
+; RV64IXQCCMP-SR-NEXT: sw s6, 52(a0)
+; RV64IXQCCMP-SR-NEXT: sw s5, 48(a0)
+; RV64IXQCCMP-SR-NEXT: sw s4, 44(a0)
+; RV64IXQCCMP-SR-NEXT: sw s3, 40(a0)
+; RV64IXQCCMP-SR-NEXT: sw s2, 36(a0)
+; RV64IXQCCMP-SR-NEXT: sw t6, 32(a0)
+; RV64IXQCCMP-SR-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-SR-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-SR-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-SR-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: sw a1, 16(a0)
+; RV64IXQCCMP-SR-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: sw a1, 12(a0)
+; RV64IXQCCMP-SR-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: sw a1, 8(a0)
+; RV64IXQCCMP-SR-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: sw a1, 4(a0)
+; RV64IXQCCMP-SR-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: sw a1, 0(a0)
+; RV64IXQCCMP-SR-NEXT: ld t0, 152(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld t1, 144(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld t2, 136(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld a0, 128(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld a1, 120(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld a2, 112(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld a3, 104(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld a4, 96(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld a5, 88(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld a6, 80(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld a7, 72(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld t3, 64(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld t4, 56(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld t5, 48(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: ld t6, 40(sp) # 8-byte Folded Reload
; RV64IXQCCMP-SR-NEXT: .cfi_restore t0
; RV64IXQCCMP-SR-NEXT: .cfi_restore t1
; RV64IXQCCMP-SR-NEXT: .cfi_restore t2
@@ -3155,7 +3125,7 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IXQCCMP-SR-NEXT: .cfi_restore t4
; RV64IXQCCMP-SR-NEXT: .cfi_restore t5
; RV64IXQCCMP-SR-NEXT: .cfi_restore t6
-; RV64IXQCCMP-SR-NEXT: addi sp, sp, 128
+; RV64IXQCCMP-SR-NEXT: addi sp, sp, 112
; RV64IXQCCMP-SR-NEXT: .cfi_def_cfa_offset 160
; RV64IXQCCMP-SR-NEXT: qc.cm.pop {ra, s0-s11}, 160
; RV64IXQCCMP-SR-NEXT: .cfi_restore ra
@@ -3196,84 +3166,82 @@ define void @callee_no_irq() {
; RV32IXQCCMP-NEXT: .cfi_offset s9, -44
; RV32IXQCCMP-NEXT: .cfi_offset s10, -48
; RV32IXQCCMP-NEXT: .cfi_offset s11, -52
-; RV32IXQCCMP-NEXT: lui t0, %hi(var_test_irq)
-; RV32IXQCCMP-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV32IXQCCMP-NEXT: lw a0, 16(a5)
-; RV32IXQCCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw a0, 20(a5)
-; RV32IXQCCMP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw t4, 24(a5)
-; RV32IXQCCMP-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-NEXT: lw t6, 32(a5)
-; RV32IXQCCMP-NEXT: lw s2, 36(a5)
-; RV32IXQCCMP-NEXT: lw s3, 40(a5)
-; RV32IXQCCMP-NEXT: lw s4, 44(a5)
-; RV32IXQCCMP-NEXT: lw s5, 48(a5)
-; RV32IXQCCMP-NEXT: lw s6, 52(a5)
-; RV32IXQCCMP-NEXT: lw s7, 56(a5)
-; RV32IXQCCMP-NEXT: lw s8, 60(a5)
-; RV32IXQCCMP-NEXT: lw s9, 64(a5)
-; RV32IXQCCMP-NEXT: lw s10, 68(a5)
-; RV32IXQCCMP-NEXT: lw s11, 72(a5)
-; RV32IXQCCMP-NEXT: lw ra, 76(a5)
-; RV32IXQCCMP-NEXT: lw s1, 80(a5)
-; RV32IXQCCMP-NEXT: lw t3, 84(a5)
-; RV32IXQCCMP-NEXT: lw t2, 88(a5)
-; RV32IXQCCMP-NEXT: lw t1, 92(a5)
-; RV32IXQCCMP-NEXT: lw a7, 112(a5)
-; RV32IXQCCMP-NEXT: lw s0, 116(a5)
-; RV32IXQCCMP-NEXT: lw a3, 120(a5)
-; RV32IXQCCMP-NEXT: lw a0, 124(a5)
-; RV32IXQCCMP-NEXT: lw a6, 96(a5)
-; RV32IXQCCMP-NEXT: lw a4, 100(a5)
-; RV32IXQCCMP-NEXT: lw a2, 104(a5)
-; RV32IXQCCMP-NEXT: lw a1, 108(a5)
-; RV32IXQCCMP-NEXT: sw a0, 124(a5)
-; RV32IXQCCMP-NEXT: sw a3, 120(a5)
-; RV32IXQCCMP-NEXT: sw s0, 116(a5)
-; RV32IXQCCMP-NEXT: sw a7, 112(a5)
-; RV32IXQCCMP-NEXT: sw a1, 108(a5)
-; RV32IXQCCMP-NEXT: sw a2, 104(a5)
-; RV32IXQCCMP-NEXT: sw a4, 100(a5)
-; RV32IXQCCMP-NEXT: sw a6, 96(a5)
-; RV32IXQCCMP-NEXT: sw t1, 92(a5)
-; RV32IXQCCMP-NEXT: sw t2, 88(a5)
-; RV32IXQCCMP-NEXT: sw t3, 84(a5)
-; RV32IXQCCMP-NEXT: sw s1, 80(a5)
-; RV32IXQCCMP-NEXT: sw ra, 76(a5)
-; RV32IXQCCMP-NEXT: sw s11, 72(a5)
-; RV32IXQCCMP-NEXT: sw s10, 68(a5)
-; RV32IXQCCMP-NEXT: sw s9, 64(a5)
-; RV32IXQCCMP-NEXT: sw s8, 60(a5)
-; RV32IXQCCMP-NEXT: sw s7, 56(a5)
-; RV32IXQCCMP-NEXT: sw s6, 52(a5)
-; RV32IXQCCMP-NEXT: sw s5, 48(a5)
-; RV32IXQCCMP-NEXT: sw s4, 44(a5)
-; RV32IXQCCMP-NEXT: sw s3, 40(a5)
-; RV32IXQCCMP-NEXT: sw s2, 36(a5)
-; RV32IXQCCMP-NEXT: sw t6, 32(a5)
-; RV32IXQCCMP-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-NEXT: sw t4, 24(a5)
-; RV32IXQCCMP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 20(a5)
-; RV32IXQCCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, 16(a5)
-; RV32IXQCCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-NEXT: sw a0, %lo(var_test_irq)(t0)
+; RV32IXQCCMP-NEXT: lui a0, %hi(var_test_irq)
+; RV32IXQCCMP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32IXQCCMP-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 4(a0)
+; RV32IXQCCMP-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 8(a0)
+; RV32IXQCCMP-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 12(a0)
+; RV32IXQCCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw a1, 16(a0)
+; RV32IXQCCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-NEXT: lw t3, 20(a0)
+; RV32IXQCCMP-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-NEXT: lw t6, 32(a0)
+; RV32IXQCCMP-NEXT: lw s2, 36(a0)
+; RV32IXQCCMP-NEXT: lw s3, 40(a0)
+; RV32IXQCCMP-NEXT: lw s4, 44(a0)
+; RV32IXQCCMP-NEXT: lw s5, 48(a0)
+; RV32IXQCCMP-NEXT: lw s6, 52(a0)
+; RV32IXQCCMP-NEXT: lw s7, 56(a0)
+; RV32IXQCCMP-NEXT: lw s8, 60(a0)
+; RV32IXQCCMP-NEXT: lw s9, 64(a0)
+; RV32IXQCCMP-NEXT: lw s10, 68(a0)
+; RV32IXQCCMP-NEXT: lw s11, 72(a0)
+; RV32IXQCCMP-NEXT: lw ra, 76(a0)
+; RV32IXQCCMP-NEXT: lw t2, 80(a0)
+; RV32IXQCCMP-NEXT: lw s0, 84(a0)
+; RV32IXQCCMP-NEXT: lw s1, 88(a0)
+; RV32IXQCCMP-NEXT: lw t1, 92(a0)
+; RV32IXQCCMP-NEXT: lw t0, 112(a0)
+; RV32IXQCCMP-NEXT: lw a5, 116(a0)
+; RV32IXQCCMP-NEXT: lw a3, 120(a0)
+; RV32IXQCCMP-NEXT: lw a1, 124(a0)
+; RV32IXQCCMP-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-NEXT: lw a6, 100(a0)
+; RV32IXQCCMP-NEXT: lw a4, 104(a0)
+; RV32IXQCCMP-NEXT: lw a2, 108(a0)
+; RV32IXQCCMP-NEXT: sw a1, 124(a0)
+; RV32IXQCCMP-NEXT: sw a3, 120(a0)
+; RV32IXQCCMP-NEXT: sw a5, 116(a0)
+; RV32IXQCCMP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-NEXT: sw a2, 108(a0)
+; RV32IXQCCMP-NEXT: sw a4, 104(a0)
+; RV32IXQCCMP-NEXT: sw a6, 100(a0)
+; RV32IXQCCMP-NEXT: sw a7, 96(a0)
+; RV32IXQCCMP-NEXT: sw t1, 92(a0)
+; RV32IXQCCMP-NEXT: sw s1, 88(a0)
+; RV32IXQCCMP-NEXT: sw s0, 84(a0)
+; RV32IXQCCMP-NEXT: sw t2, 80(a0)
+; RV32IXQCCMP-NEXT: sw ra, 76(a0)
+; RV32IXQCCMP-NEXT: sw s11, 72(a0)
+; RV32IXQCCMP-NEXT: sw s10, 68(a0)
+; RV32IXQCCMP-NEXT: sw s9, 64(a0)
+; RV32IXQCCMP-NEXT: sw s8, 60(a0)
+; RV32IXQCCMP-NEXT: sw s7, 56(a0)
+; RV32IXQCCMP-NEXT: sw s6, 52(a0)
+; RV32IXQCCMP-NEXT: sw s5, 48(a0)
+; RV32IXQCCMP-NEXT: sw s4, 44(a0)
+; RV32IXQCCMP-NEXT: sw s3, 40(a0)
+; RV32IXQCCMP-NEXT: sw s2, 36(a0)
+; RV32IXQCCMP-NEXT: sw t6, 32(a0)
+; RV32IXQCCMP-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 16(a0)
+; RV32IXQCCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 12(a0)
+; RV32IXQCCMP-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 8(a0)
+; RV32IXQCCMP-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 4(a0)
+; RV32IXQCCMP-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-NEXT: sw a1, 0(a0)
; RV32IXQCCMP-NEXT: qc.cm.popret {ra, s0-s11}, 96
;
; RV64IXQCCMP-LABEL: callee_no_irq:
@@ -3293,84 +3261,82 @@ define void @callee_no_irq() {
; RV64IXQCCMP-NEXT: .cfi_offset s9, -88
; RV64IXQCCMP-NEXT: .cfi_offset s10, -96
; RV64IXQCCMP-NEXT: .cfi_offset s11, -104
-; RV64IXQCCMP-NEXT: lui t0, %hi(var_test_irq)
-; RV64IXQCCMP-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV64IXQCCMP-NEXT: lw a0, 16(a5)
-; RV64IXQCCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw a0, 20(a5)
-; RV64IXQCCMP-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw t4, 24(a5)
-; RV64IXQCCMP-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-NEXT: lw t6, 32(a5)
-; RV64IXQCCMP-NEXT: lw s2, 36(a5)
-; RV64IXQCCMP-NEXT: lw s3, 40(a5)
-; RV64IXQCCMP-NEXT: lw s4, 44(a5)
-; RV64IXQCCMP-NEXT: lw s5, 48(a5)
-; RV64IXQCCMP-NEXT: lw s6, 52(a5)
-; RV64IXQCCMP-NEXT: lw s7, 56(a5)
-; RV64IXQCCMP-NEXT: lw s8, 60(a5)
-; RV64IXQCCMP-NEXT: lw s9, 64(a5)
-; RV64IXQCCMP-NEXT: lw s10, 68(a5)
-; RV64IXQCCMP-NEXT: lw s11, 72(a5)
-; RV64IXQCCMP-NEXT: lw ra, 76(a5)
-; RV64IXQCCMP-NEXT: lw s1, 80(a5)
-; RV64IXQCCMP-NEXT: lw t3, 84(a5)
-; RV64IXQCCMP-NEXT: lw t2, 88(a5)
-; RV64IXQCCMP-NEXT: lw t1, 92(a5)
-; RV64IXQCCMP-NEXT: lw a7, 112(a5)
-; RV64IXQCCMP-NEXT: lw s0, 116(a5)
-; RV64IXQCCMP-NEXT: lw a3, 120(a5)
-; RV64IXQCCMP-NEXT: lw a0, 124(a5)
-; RV64IXQCCMP-NEXT: lw a6, 96(a5)
-; RV64IXQCCMP-NEXT: lw a4, 100(a5)
-; RV64IXQCCMP-NEXT: lw a2, 104(a5)
-; RV64IXQCCMP-NEXT: lw a1, 108(a5)
-; RV64IXQCCMP-NEXT: sw a0, 124(a5)
-; RV64IXQCCMP-NEXT: sw a3, 120(a5)
-; RV64IXQCCMP-NEXT: sw s0, 116(a5)
-; RV64IXQCCMP-NEXT: sw a7, 112(a5)
-; RV64IXQCCMP-NEXT: sw a1, 108(a5)
-; RV64IXQCCMP-NEXT: sw a2, 104(a5)
-; RV64IXQCCMP-NEXT: sw a4, 100(a5)
-; RV64IXQCCMP-NEXT: sw a6, 96(a5)
-; RV64IXQCCMP-NEXT: sw t1, 92(a5)
-; RV64IXQCCMP-NEXT: sw t2, 88(a5)
-; RV64IXQCCMP-NEXT: sw t3, 84(a5)
-; RV64IXQCCMP-NEXT: sw s1, 80(a5)
-; RV64IXQCCMP-NEXT: sw ra, 76(a5)
-; RV64IXQCCMP-NEXT: sw s11, 72(a5)
-; RV64IXQCCMP-NEXT: sw s10, 68(a5)
-; RV64IXQCCMP-NEXT: sw s9, 64(a5)
-; RV64IXQCCMP-NEXT: sw s8, 60(a5)
-; RV64IXQCCMP-NEXT: sw s7, 56(a5)
-; RV64IXQCCMP-NEXT: sw s6, 52(a5)
-; RV64IXQCCMP-NEXT: sw s5, 48(a5)
-; RV64IXQCCMP-NEXT: sw s4, 44(a5)
-; RV64IXQCCMP-NEXT: sw s3, 40(a5)
-; RV64IXQCCMP-NEXT: sw s2, 36(a5)
-; RV64IXQCCMP-NEXT: sw t6, 32(a5)
-; RV64IXQCCMP-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-NEXT: sw t4, 24(a5)
-; RV64IXQCCMP-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 20(a5)
-; RV64IXQCCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, 16(a5)
-; RV64IXQCCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-NEXT: sw a0, %lo(var_test_irq)(t0)
+; RV64IXQCCMP-NEXT: lui a0, %hi(var_test_irq)
+; RV64IXQCCMP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64IXQCCMP-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-NEXT: sd a1, 40(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 4(a0)
+; RV64IXQCCMP-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 8(a0)
+; RV64IXQCCMP-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 12(a0)
+; RV64IXQCCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw a1, 16(a0)
+; RV64IXQCCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-NEXT: lw t3, 20(a0)
+; RV64IXQCCMP-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-NEXT: lw t6, 32(a0)
+; RV64IXQCCMP-NEXT: lw s2, 36(a0)
+; RV64IXQCCMP-NEXT: lw s3, 40(a0)
+; RV64IXQCCMP-NEXT: lw s4, 44(a0)
+; RV64IXQCCMP-NEXT: lw s5, 48(a0)
+; RV64IXQCCMP-NEXT: lw s6, 52(a0)
+; RV64IXQCCMP-NEXT: lw s7, 56(a0)
+; RV64IXQCCMP-NEXT: lw s8, 60(a0)
+; RV64IXQCCMP-NEXT: lw s9, 64(a0)
+; RV64IXQCCMP-NEXT: lw s10, 68(a0)
+; RV64IXQCCMP-NEXT: lw s11, 72(a0)
+; RV64IXQCCMP-NEXT: lw ra, 76(a0)
+; RV64IXQCCMP-NEXT: lw t2, 80(a0)
+; RV64IXQCCMP-NEXT: lw s0, 84(a0)
+; RV64IXQCCMP-NEXT: lw s1, 88(a0)
+; RV64IXQCCMP-NEXT: lw t1, 92(a0)
+; RV64IXQCCMP-NEXT: lw t0, 112(a0)
+; RV64IXQCCMP-NEXT: lw a5, 116(a0)
+; RV64IXQCCMP-NEXT: lw a3, 120(a0)
+; RV64IXQCCMP-NEXT: lw a1, 124(a0)
+; RV64IXQCCMP-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-NEXT: lw a6, 100(a0)
+; RV64IXQCCMP-NEXT: lw a4, 104(a0)
+; RV64IXQCCMP-NEXT: lw a2, 108(a0)
+; RV64IXQCCMP-NEXT: sw a1, 124(a0)
+; RV64IXQCCMP-NEXT: sw a3, 120(a0)
+; RV64IXQCCMP-NEXT: sw a5, 116(a0)
+; RV64IXQCCMP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-NEXT: sw a2, 108(a0)
+; RV64IXQCCMP-NEXT: sw a4, 104(a0)
+; RV64IXQCCMP-NEXT: sw a6, 100(a0)
+; RV64IXQCCMP-NEXT: sw a7, 96(a0)
+; RV64IXQCCMP-NEXT: sw t1, 92(a0)
+; RV64IXQCCMP-NEXT: sw s1, 88(a0)
+; RV64IXQCCMP-NEXT: sw s0, 84(a0)
+; RV64IXQCCMP-NEXT: sw t2, 80(a0)
+; RV64IXQCCMP-NEXT: sw ra, 76(a0)
+; RV64IXQCCMP-NEXT: sw s11, 72(a0)
+; RV64IXQCCMP-NEXT: sw s10, 68(a0)
+; RV64IXQCCMP-NEXT: sw s9, 64(a0)
+; RV64IXQCCMP-NEXT: sw s8, 60(a0)
+; RV64IXQCCMP-NEXT: sw s7, 56(a0)
+; RV64IXQCCMP-NEXT: sw s6, 52(a0)
+; RV64IXQCCMP-NEXT: sw s5, 48(a0)
+; RV64IXQCCMP-NEXT: sw s4, 44(a0)
+; RV64IXQCCMP-NEXT: sw s3, 40(a0)
+; RV64IXQCCMP-NEXT: sw s2, 36(a0)
+; RV64IXQCCMP-NEXT: sw t6, 32(a0)
+; RV64IXQCCMP-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 16(a0)
+; RV64IXQCCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 12(a0)
+; RV64IXQCCMP-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 8(a0)
+; RV64IXQCCMP-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 4(a0)
+; RV64IXQCCMP-NEXT: ld a1, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-NEXT: sw a1, 0(a0)
; RV64IXQCCMP-NEXT: qc.cm.popret {ra, s0-s11}, 160
;
; RV32IXQCCMP-FP-LABEL: callee_no_irq:
@@ -3391,86 +3357,84 @@ define void @callee_no_irq() {
; RV32IXQCCMP-FP-NEXT: .cfi_offset s10, -48
; RV32IXQCCMP-FP-NEXT: .cfi_offset s11, -52
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
-; RV32IXQCCMP-FP-NEXT: lui t1, %hi(var_test_irq)
-; RV32IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq)(t1)
-; RV32IXQCCMP-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+4)(t1)
-; RV32IXQCCMP-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+8)(t1)
-; RV32IXQCCMP-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+12)(t1)
-; RV32IXQCCMP-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: addi a5, t1, %lo(var_test_irq)
-; RV32IXQCCMP-FP-NEXT: lw a0, 16(a5)
-; RV32IXQCCMP-FP-NEXT: sw a0, -84(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw a0, 20(a5)
-; RV32IXQCCMP-FP-NEXT: sw a0, -88(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw a0, 24(a5)
-; RV32IXQCCMP-FP-NEXT: sw a0, -92(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-FP-NEXT: lw t6, 32(a5)
-; RV32IXQCCMP-FP-NEXT: lw s2, 36(a5)
-; RV32IXQCCMP-FP-NEXT: lw s3, 40(a5)
-; RV32IXQCCMP-FP-NEXT: lw s4, 44(a5)
-; RV32IXQCCMP-FP-NEXT: lw s5, 48(a5)
-; RV32IXQCCMP-FP-NEXT: lw s6, 52(a5)
-; RV32IXQCCMP-FP-NEXT: lw s7, 56(a5)
-; RV32IXQCCMP-FP-NEXT: lw s8, 60(a5)
-; RV32IXQCCMP-FP-NEXT: lw s9, 64(a5)
-; RV32IXQCCMP-FP-NEXT: lw s10, 68(a5)
-; RV32IXQCCMP-FP-NEXT: lw s11, 72(a5)
-; RV32IXQCCMP-FP-NEXT: lw ra, 76(a5)
-; RV32IXQCCMP-FP-NEXT: lw t4, 80(a5)
-; RV32IXQCCMP-FP-NEXT: lw t3, 84(a5)
-; RV32IXQCCMP-FP-NEXT: lw t2, 88(a5)
-; RV32IXQCCMP-FP-NEXT: lw s1, 92(a5)
-; RV32IXQCCMP-FP-NEXT: lw t0, 112(a5)
-; RV32IXQCCMP-FP-NEXT: lw a4, 116(a5)
-; RV32IXQCCMP-FP-NEXT: lw a3, 120(a5)
-; RV32IXQCCMP-FP-NEXT: lw a0, 124(a5)
-; RV32IXQCCMP-FP-NEXT: lw a7, 96(a5)
-; RV32IXQCCMP-FP-NEXT: lw a6, 100(a5)
-; RV32IXQCCMP-FP-NEXT: lw a2, 104(a5)
-; RV32IXQCCMP-FP-NEXT: lw a1, 108(a5)
-; RV32IXQCCMP-FP-NEXT: sw a0, 124(a5)
-; RV32IXQCCMP-FP-NEXT: sw a3, 120(a5)
-; RV32IXQCCMP-FP-NEXT: sw a4, 116(a5)
-; RV32IXQCCMP-FP-NEXT: sw t0, 112(a5)
-; RV32IXQCCMP-FP-NEXT: sw a1, 108(a5)
-; RV32IXQCCMP-FP-NEXT: sw a2, 104(a5)
-; RV32IXQCCMP-FP-NEXT: sw a6, 100(a5)
-; RV32IXQCCMP-FP-NEXT: sw a7, 96(a5)
-; RV32IXQCCMP-FP-NEXT: sw s1, 92(a5)
-; RV32IXQCCMP-FP-NEXT: sw t2, 88(a5)
-; RV32IXQCCMP-FP-NEXT: sw t3, 84(a5)
-; RV32IXQCCMP-FP-NEXT: sw t4, 80(a5)
-; RV32IXQCCMP-FP-NEXT: sw ra, 76(a5)
-; RV32IXQCCMP-FP-NEXT: sw s11, 72(a5)
-; RV32IXQCCMP-FP-NEXT: sw s10, 68(a5)
-; RV32IXQCCMP-FP-NEXT: sw s9, 64(a5)
-; RV32IXQCCMP-FP-NEXT: sw s8, 60(a5)
-; RV32IXQCCMP-FP-NEXT: sw s7, 56(a5)
-; RV32IXQCCMP-FP-NEXT: sw s6, 52(a5)
-; RV32IXQCCMP-FP-NEXT: sw s5, 48(a5)
-; RV32IXQCCMP-FP-NEXT: sw s4, 44(a5)
-; RV32IXQCCMP-FP-NEXT: sw s3, 40(a5)
-; RV32IXQCCMP-FP-NEXT: sw s2, 36(a5)
-; RV32IXQCCMP-FP-NEXT: sw t6, 32(a5)
-; RV32IXQCCMP-FP-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-FP-NEXT: lw a0, -92(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, 24(a5)
-; RV32IXQCCMP-FP-NEXT: lw a0, -88(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, 20(a5)
-; RV32IXQCCMP-FP-NEXT: lw a0, -84(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, 16(a5)
-; RV32IXQCCMP-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+12)(t1)
-; RV32IXQCCMP-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+8)(t1)
-; RV32IXQCCMP-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+4)(t1)
-; RV32IXQCCMP-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
-; RV32IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq)(t1)
+; RV32IXQCCMP-FP-NEXT: lui a0, %hi(var_test_irq)
+; RV32IXQCCMP-FP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32IXQCCMP-FP-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -68(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw a1, 4(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -72(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw a1, 8(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -76(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw a1, 12(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -80(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw a1, 16(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -84(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw a1, 20(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, -88(s0) # 4-byte Folded Spill
+; RV32IXQCCMP-FP-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-FP-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-FP-NEXT: lw t6, 32(a0)
+; RV32IXQCCMP-FP-NEXT: lw s2, 36(a0)
+; RV32IXQCCMP-FP-NEXT: lw s3, 40(a0)
+; RV32IXQCCMP-FP-NEXT: lw s4, 44(a0)
+; RV32IXQCCMP-FP-NEXT: lw s5, 48(a0)
+; RV32IXQCCMP-FP-NEXT: lw s6, 52(a0)
+; RV32IXQCCMP-FP-NEXT: lw s7, 56(a0)
+; RV32IXQCCMP-FP-NEXT: lw s8, 60(a0)
+; RV32IXQCCMP-FP-NEXT: lw s9, 64(a0)
+; RV32IXQCCMP-FP-NEXT: lw s10, 68(a0)
+; RV32IXQCCMP-FP-NEXT: lw s11, 72(a0)
+; RV32IXQCCMP-FP-NEXT: lw ra, 76(a0)
+; RV32IXQCCMP-FP-NEXT: lw s1, 80(a0)
+; RV32IXQCCMP-FP-NEXT: lw t3, 84(a0)
+; RV32IXQCCMP-FP-NEXT: lw t2, 88(a0)
+; RV32IXQCCMP-FP-NEXT: lw t1, 92(a0)
+; RV32IXQCCMP-FP-NEXT: lw t0, 112(a0)
+; RV32IXQCCMP-FP-NEXT: lw a6, 116(a0)
+; RV32IXQCCMP-FP-NEXT: lw a4, 120(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, 124(a0)
+; RV32IXQCCMP-FP-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-FP-NEXT: lw a5, 100(a0)
+; RV32IXQCCMP-FP-NEXT: lw a3, 104(a0)
+; RV32IXQCCMP-FP-NEXT: lw a2, 108(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, 124(a0)
+; RV32IXQCCMP-FP-NEXT: sw a4, 120(a0)
+; RV32IXQCCMP-FP-NEXT: sw a6, 116(a0)
+; RV32IXQCCMP-FP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-FP-NEXT: sw a2, 108(a0)
+; RV32IXQCCMP-FP-NEXT: sw a3, 104(a0)
+; RV32IXQCCMP-FP-NEXT: sw a5, 100(a0)
+; RV32IXQCCMP-FP-NEXT: sw a7, 96(a0)
+; RV32IXQCCMP-FP-NEXT: sw t1, 92(a0)
+; RV32IXQCCMP-FP-NEXT: sw t2, 88(a0)
+; RV32IXQCCMP-FP-NEXT: sw t3, 84(a0)
+; RV32IXQCCMP-FP-NEXT: sw s1, 80(a0)
+; RV32IXQCCMP-FP-NEXT: sw ra, 76(a0)
+; RV32IXQCCMP-FP-NEXT: sw s11, 72(a0)
+; RV32IXQCCMP-FP-NEXT: sw s10, 68(a0)
+; RV32IXQCCMP-FP-NEXT: sw s9, 64(a0)
+; RV32IXQCCMP-FP-NEXT: sw s8, 60(a0)
+; RV32IXQCCMP-FP-NEXT: sw s7, 56(a0)
+; RV32IXQCCMP-FP-NEXT: sw s6, 52(a0)
+; RV32IXQCCMP-FP-NEXT: sw s5, 48(a0)
+; RV32IXQCCMP-FP-NEXT: sw s4, 44(a0)
+; RV32IXQCCMP-FP-NEXT: sw s3, 40(a0)
+; RV32IXQCCMP-FP-NEXT: sw s2, 36(a0)
+; RV32IXQCCMP-FP-NEXT: sw t6, 32(a0)
+; RV32IXQCCMP-FP-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-FP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -88(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 20(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -84(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 16(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -80(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 12(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -76(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 8(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -72(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 4(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, -68(s0) # 4-byte Folded Reload
+; RV32IXQCCMP-FP-NEXT: sw a1, 0(a0)
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 96
; RV32IXQCCMP-FP-NEXT: qc.cm.popret {ra, s0-s11}, 96
;
@@ -3491,92 +3455,86 @@ define void @callee_no_irq() {
; RV64IXQCCMP-FP-NEXT: .cfi_offset s9, -88
; RV64IXQCCMP-FP-NEXT: .cfi_offset s10, -96
; RV64IXQCCMP-FP-NEXT: .cfi_offset s11, -104
-; RV64IXQCCMP-FP-NEXT: addi sp, sp, -16
-; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa_offset 176
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
-; RV64IXQCCMP-FP-NEXT: lui t1, %hi(var_test_irq)
-; RV64IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq)(t1)
-; RV64IXQCCMP-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+4)(t1)
-; RV64IXQCCMP-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+8)(t1)
-; RV64IXQCCMP-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw a0, %lo(var_test_irq+12)(t1)
-; RV64IXQCCMP-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: addi a5, t1, %lo(var_test_irq)
-; RV64IXQCCMP-FP-NEXT: lw a0, 16(a5)
-; RV64IXQCCMP-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw a0, 20(a5)
-; RV64IXQCCMP-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw a0, 24(a5)
-; RV64IXQCCMP-FP-NEXT: sd a0, -168(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-FP-NEXT: lw t6, 32(a5)
-; RV64IXQCCMP-FP-NEXT: lw s2, 36(a5)
-; RV64IXQCCMP-FP-NEXT: lw s3, 40(a5)
-; RV64IXQCCMP-FP-NEXT: lw s4, 44(a5)
-; RV64IXQCCMP-FP-NEXT: lw s5, 48(a5)
-; RV64IXQCCMP-FP-NEXT: lw s6, 52(a5)
-; RV64IXQCCMP-FP-NEXT: lw s7, 56(a5)
-; RV64IXQCCMP-FP-NEXT: lw s8, 60(a5)
-; RV64IXQCCMP-FP-NEXT: lw s9, 64(a5)
-; RV64IXQCCMP-FP-NEXT: lw s10, 68(a5)
-; RV64IXQCCMP-FP-NEXT: lw s11, 72(a5)
-; RV64IXQCCMP-FP-NEXT: lw ra, 76(a5)
-; RV64IXQCCMP-FP-NEXT: lw t4, 80(a5)
-; RV64IXQCCMP-FP-NEXT: lw t3, 84(a5)
-; RV64IXQCCMP-FP-NEXT: lw t2, 88(a5)
-; RV64IXQCCMP-FP-NEXT: lw s1, 92(a5)
-; RV64IXQCCMP-FP-NEXT: lw t0, 112(a5)
-; RV64IXQCCMP-FP-NEXT: lw a4, 116(a5)
-; RV64IXQCCMP-FP-NEXT: lw a3, 120(a5)
-; RV64IXQCCMP-FP-NEXT: lw a0, 124(a5)
-; RV64IXQCCMP-FP-NEXT: lw a7, 96(a5)
-; RV64IXQCCMP-FP-NEXT: lw a6, 100(a5)
-; RV64IXQCCMP-FP-NEXT: lw a2, 104(a5)
-; RV64IXQCCMP-FP-NEXT: lw a1, 108(a5)
-; RV64IXQCCMP-FP-NEXT: sw a0, 124(a5)
-; RV64IXQCCMP-FP-NEXT: sw a3, 120(a5)
-; RV64IXQCCMP-FP-NEXT: sw a4, 116(a5)
-; RV64IXQCCMP-FP-NEXT: sw t0, 112(a5)
-; RV64IXQCCMP-FP-NEXT: sw a1, 108(a5)
-; RV64IXQCCMP-FP-NEXT: sw a2, 104(a5)
-; RV64IXQCCMP-FP-NEXT: sw a6, 100(a5)
-; RV64IXQCCMP-FP-NEXT: sw a7, 96(a5)
-; RV64IXQCCMP-FP-NEXT: sw s1, 92(a5)
-; RV64IXQCCMP-FP-NEXT: sw t2, 88(a5)
-; RV64IXQCCMP-FP-NEXT: sw t3, 84(a5)
-; RV64IXQCCMP-FP-NEXT: sw t4, 80(a5)
-; RV64IXQCCMP-FP-NEXT: sw ra, 76(a5)
-; RV64IXQCCMP-FP-NEXT: sw s11, 72(a5)
-; RV64IXQCCMP-FP-NEXT: sw s10, 68(a5)
-; RV64IXQCCMP-FP-NEXT: sw s9, 64(a5)
-; RV64IXQCCMP-FP-NEXT: sw s8, 60(a5)
-; RV64IXQCCMP-FP-NEXT: sw s7, 56(a5)
-; RV64IXQCCMP-FP-NEXT: sw s6, 52(a5)
-; RV64IXQCCMP-FP-NEXT: sw s5, 48(a5)
-; RV64IXQCCMP-FP-NEXT: sw s4, 44(a5)
-; RV64IXQCCMP-FP-NEXT: sw s3, 40(a5)
-; RV64IXQCCMP-FP-NEXT: sw s2, 36(a5)
-; RV64IXQCCMP-FP-NEXT: sw t6, 32(a5)
-; RV64IXQCCMP-FP-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-FP-NEXT: ld a0, -168(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, 24(a5)
-; RV64IXQCCMP-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, 20(a5)
-; RV64IXQCCMP-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, 16(a5)
-; RV64IXQCCMP-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+12)(t1)
-; RV64IXQCCMP-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+8)(t1)
-; RV64IXQCCMP-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq+4)(t1)
-; RV64IXQCCMP-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload
-; RV64IXQCCMP-FP-NEXT: sw a0, %lo(var_test_irq)(t1)
-; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 176
-; RV64IXQCCMP-FP-NEXT: addi sp, sp, 16
-; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa_offset 160
+; RV64IXQCCMP-FP-NEXT: lui a0, %hi(var_test_irq)
+; RV64IXQCCMP-FP-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64IXQCCMP-FP-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -120(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw a1, 4(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -128(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw a1, 8(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -136(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw a1, 12(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -144(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw a1, 16(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -152(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw a1, 20(a0)
+; RV64IXQCCMP-FP-NEXT: sd a1, -160(s0) # 8-byte Folded Spill
+; RV64IXQCCMP-FP-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-FP-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-FP-NEXT: lw t6, 32(a0)
+; RV64IXQCCMP-FP-NEXT: lw s2, 36(a0)
+; RV64IXQCCMP-FP-NEXT: lw s3, 40(a0)
+; RV64IXQCCMP-FP-NEXT: lw s4, 44(a0)
+; RV64IXQCCMP-FP-NEXT: lw s5, 48(a0)
+; RV64IXQCCMP-FP-NEXT: lw s6, 52(a0)
+; RV64IXQCCMP-FP-NEXT: lw s7, 56(a0)
+; RV64IXQCCMP-FP-NEXT: lw s8, 60(a0)
+; RV64IXQCCMP-FP-NEXT: lw s9, 64(a0)
+; RV64IXQCCMP-FP-NEXT: lw s10, 68(a0)
+; RV64IXQCCMP-FP-NEXT: lw s11, 72(a0)
+; RV64IXQCCMP-FP-NEXT: lw ra, 76(a0)
+; RV64IXQCCMP-FP-NEXT: lw s1, 80(a0)
+; RV64IXQCCMP-FP-NEXT: lw t3, 84(a0)
+; RV64IXQCCMP-FP-NEXT: lw t2, 88(a0)
+; RV64IXQCCMP-FP-NEXT: lw t1, 92(a0)
+; RV64IXQCCMP-FP-NEXT: lw t0, 112(a0)
+; RV64IXQCCMP-FP-NEXT: lw a6, 116(a0)
+; RV64IXQCCMP-FP-NEXT: lw a4, 120(a0)
+; RV64IXQCCMP-FP-NEXT: lw a1, 124(a0)
+; RV64IXQCCMP-FP-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-FP-NEXT: lw a5, 100(a0)
+; RV64IXQCCMP-FP-NEXT: lw a3, 104(a0)
+; RV64IXQCCMP-FP-NEXT: lw a2, 108(a0)
+; RV64IXQCCMP-FP-NEXT: sw a1, 124(a0)
+; RV64IXQCCMP-FP-NEXT: sw a4, 120(a0)
+; RV64IXQCCMP-FP-NEXT: sw a6, 116(a0)
+; RV64IXQCCMP-FP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-FP-NEXT: sw a2, 108(a0)
+; RV64IXQCCMP-FP-NEXT: sw a3, 104(a0)
+; RV64IXQCCMP-FP-NEXT: sw a5, 100(a0)
+; RV64IXQCCMP-FP-NEXT: sw a7, 96(a0)
+; RV64IXQCCMP-FP-NEXT: sw t1, 92(a0)
+; RV64IXQCCMP-FP-NEXT: sw t2, 88(a0)
+; RV64IXQCCMP-FP-NEXT: sw t3, 84(a0)
+; RV64IXQCCMP-FP-NEXT: sw s1, 80(a0)
+; RV64IXQCCMP-FP-NEXT: sw ra, 76(a0)
+; RV64IXQCCMP-FP-NEXT: sw s11, 72(a0)
+; RV64IXQCCMP-FP-NEXT: sw s10, 68(a0)
+; RV64IXQCCMP-FP-NEXT: sw s9, 64(a0)
+; RV64IXQCCMP-FP-NEXT: sw s8, 60(a0)
+; RV64IXQCCMP-FP-NEXT: sw s7, 56(a0)
+; RV64IXQCCMP-FP-NEXT: sw s6, 52(a0)
+; RV64IXQCCMP-FP-NEXT: sw s5, 48(a0)
+; RV64IXQCCMP-FP-NEXT: sw s4, 44(a0)
+; RV64IXQCCMP-FP-NEXT: sw s3, 40(a0)
+; RV64IXQCCMP-FP-NEXT: sw s2, 36(a0)
+; RV64IXQCCMP-FP-NEXT: sw t6, 32(a0)
+; RV64IXQCCMP-FP-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-FP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -160(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 20(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -152(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 16(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -144(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 12(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -136(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 8(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -128(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 4(a0)
+; RV64IXQCCMP-FP-NEXT: ld a1, -120(s0) # 8-byte Folded Reload
+; RV64IXQCCMP-FP-NEXT: sw a1, 0(a0)
+; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 160
; RV64IXQCCMP-FP-NEXT: qc.cm.popret {ra, s0-s11}, 160
;
; RV32IXQCCMP-SR-LABEL: callee_no_irq:
@@ -3596,84 +3554,82 @@ define void @callee_no_irq() {
; RV32IXQCCMP-SR-NEXT: .cfi_offset s9, -44
; RV32IXQCCMP-SR-NEXT: .cfi_offset s10, -48
; RV32IXQCCMP-SR-NEXT: .cfi_offset s11, -52
-; RV32IXQCCMP-SR-NEXT: lui t0, %hi(var_test_irq)
-; RV32IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV32IXQCCMP-SR-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-SR-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-SR-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-SR-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV32IXQCCMP-SR-NEXT: lw a0, 16(a5)
-; RV32IXQCCMP-SR-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw a0, 20(a5)
-; RV32IXQCCMP-SR-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw t4, 24(a5)
-; RV32IXQCCMP-SR-NEXT: lw t5, 28(a5)
-; RV32IXQCCMP-SR-NEXT: lw t6, 32(a5)
-; RV32IXQCCMP-SR-NEXT: lw s2, 36(a5)
-; RV32IXQCCMP-SR-NEXT: lw s3, 40(a5)
-; RV32IXQCCMP-SR-NEXT: lw s4, 44(a5)
-; RV32IXQCCMP-SR-NEXT: lw s5, 48(a5)
-; RV32IXQCCMP-SR-NEXT: lw s6, 52(a5)
-; RV32IXQCCMP-SR-NEXT: lw s7, 56(a5)
-; RV32IXQCCMP-SR-NEXT: lw s8, 60(a5)
-; RV32IXQCCMP-SR-NEXT: lw s9, 64(a5)
-; RV32IXQCCMP-SR-NEXT: lw s10, 68(a5)
-; RV32IXQCCMP-SR-NEXT: lw s11, 72(a5)
-; RV32IXQCCMP-SR-NEXT: lw ra, 76(a5)
-; RV32IXQCCMP-SR-NEXT: lw s1, 80(a5)
-; RV32IXQCCMP-SR-NEXT: lw t3, 84(a5)
-; RV32IXQCCMP-SR-NEXT: lw t2, 88(a5)
-; RV32IXQCCMP-SR-NEXT: lw t1, 92(a5)
-; RV32IXQCCMP-SR-NEXT: lw a7, 112(a5)
-; RV32IXQCCMP-SR-NEXT: lw s0, 116(a5)
-; RV32IXQCCMP-SR-NEXT: lw a3, 120(a5)
-; RV32IXQCCMP-SR-NEXT: lw a0, 124(a5)
-; RV32IXQCCMP-SR-NEXT: lw a6, 96(a5)
-; RV32IXQCCMP-SR-NEXT: lw a4, 100(a5)
-; RV32IXQCCMP-SR-NEXT: lw a2, 104(a5)
-; RV32IXQCCMP-SR-NEXT: lw a1, 108(a5)
-; RV32IXQCCMP-SR-NEXT: sw a0, 124(a5)
-; RV32IXQCCMP-SR-NEXT: sw a3, 120(a5)
-; RV32IXQCCMP-SR-NEXT: sw s0, 116(a5)
-; RV32IXQCCMP-SR-NEXT: sw a7, 112(a5)
-; RV32IXQCCMP-SR-NEXT: sw a1, 108(a5)
-; RV32IXQCCMP-SR-NEXT: sw a2, 104(a5)
-; RV32IXQCCMP-SR-NEXT: sw a4, 100(a5)
-; RV32IXQCCMP-SR-NEXT: sw a6, 96(a5)
-; RV32IXQCCMP-SR-NEXT: sw t1, 92(a5)
-; RV32IXQCCMP-SR-NEXT: sw t2, 88(a5)
-; RV32IXQCCMP-SR-NEXT: sw t3, 84(a5)
-; RV32IXQCCMP-SR-NEXT: sw s1, 80(a5)
-; RV32IXQCCMP-SR-NEXT: sw ra, 76(a5)
-; RV32IXQCCMP-SR-NEXT: sw s11, 72(a5)
-; RV32IXQCCMP-SR-NEXT: sw s10, 68(a5)
-; RV32IXQCCMP-SR-NEXT: sw s9, 64(a5)
-; RV32IXQCCMP-SR-NEXT: sw s8, 60(a5)
-; RV32IXQCCMP-SR-NEXT: sw s7, 56(a5)
-; RV32IXQCCMP-SR-NEXT: sw s6, 52(a5)
-; RV32IXQCCMP-SR-NEXT: sw s5, 48(a5)
-; RV32IXQCCMP-SR-NEXT: sw s4, 44(a5)
-; RV32IXQCCMP-SR-NEXT: sw s3, 40(a5)
-; RV32IXQCCMP-SR-NEXT: sw s2, 36(a5)
-; RV32IXQCCMP-SR-NEXT: sw t6, 32(a5)
-; RV32IXQCCMP-SR-NEXT: sw t5, 28(a5)
-; RV32IXQCCMP-SR-NEXT: sw t4, 24(a5)
-; RV32IXQCCMP-SR-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, 20(a5)
-; RV32IXQCCMP-SR-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, 16(a5)
-; RV32IXQCCMP-SR-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV32IXQCCMP-SR-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV32IXQCCMP-SR-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV32IXQCCMP-SR-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
-; RV32IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq)(t0)
+; RV32IXQCCMP-SR-NEXT: lui a0, %hi(var_test_irq)
+; RV32IXQCCMP-SR-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV32IXQCCMP-SR-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 28(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: lw a1, 4(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 24(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: lw a1, 8(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 20(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: lw a1, 12(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: lw a1, 16(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
+; RV32IXQCCMP-SR-NEXT: lw t3, 20(a0)
+; RV32IXQCCMP-SR-NEXT: lw t4, 24(a0)
+; RV32IXQCCMP-SR-NEXT: lw t5, 28(a0)
+; RV32IXQCCMP-SR-NEXT: lw t6, 32(a0)
+; RV32IXQCCMP-SR-NEXT: lw s2, 36(a0)
+; RV32IXQCCMP-SR-NEXT: lw s3, 40(a0)
+; RV32IXQCCMP-SR-NEXT: lw s4, 44(a0)
+; RV32IXQCCMP-SR-NEXT: lw s5, 48(a0)
+; RV32IXQCCMP-SR-NEXT: lw s6, 52(a0)
+; RV32IXQCCMP-SR-NEXT: lw s7, 56(a0)
+; RV32IXQCCMP-SR-NEXT: lw s8, 60(a0)
+; RV32IXQCCMP-SR-NEXT: lw s9, 64(a0)
+; RV32IXQCCMP-SR-NEXT: lw s10, 68(a0)
+; RV32IXQCCMP-SR-NEXT: lw s11, 72(a0)
+; RV32IXQCCMP-SR-NEXT: lw ra, 76(a0)
+; RV32IXQCCMP-SR-NEXT: lw t2, 80(a0)
+; RV32IXQCCMP-SR-NEXT: lw s0, 84(a0)
+; RV32IXQCCMP-SR-NEXT: lw s1, 88(a0)
+; RV32IXQCCMP-SR-NEXT: lw t1, 92(a0)
+; RV32IXQCCMP-SR-NEXT: lw t0, 112(a0)
+; RV32IXQCCMP-SR-NEXT: lw a5, 116(a0)
+; RV32IXQCCMP-SR-NEXT: lw a3, 120(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 124(a0)
+; RV32IXQCCMP-SR-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-SR-NEXT: lw a6, 100(a0)
+; RV32IXQCCMP-SR-NEXT: lw a4, 104(a0)
+; RV32IXQCCMP-SR-NEXT: lw a2, 108(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 124(a0)
+; RV32IXQCCMP-SR-NEXT: sw a3, 120(a0)
+; RV32IXQCCMP-SR-NEXT: sw a5, 116(a0)
+; RV32IXQCCMP-SR-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-SR-NEXT: sw a2, 108(a0)
+; RV32IXQCCMP-SR-NEXT: sw a4, 104(a0)
+; RV32IXQCCMP-SR-NEXT: sw a6, 100(a0)
+; RV32IXQCCMP-SR-NEXT: sw a7, 96(a0)
+; RV32IXQCCMP-SR-NEXT: sw t1, 92(a0)
+; RV32IXQCCMP-SR-NEXT: sw s1, 88(a0)
+; RV32IXQCCMP-SR-NEXT: sw s0, 84(a0)
+; RV32IXQCCMP-SR-NEXT: sw t2, 80(a0)
+; RV32IXQCCMP-SR-NEXT: sw ra, 76(a0)
+; RV32IXQCCMP-SR-NEXT: sw s11, 72(a0)
+; RV32IXQCCMP-SR-NEXT: sw s10, 68(a0)
+; RV32IXQCCMP-SR-NEXT: sw s9, 64(a0)
+; RV32IXQCCMP-SR-NEXT: sw s8, 60(a0)
+; RV32IXQCCMP-SR-NEXT: sw s7, 56(a0)
+; RV32IXQCCMP-SR-NEXT: sw s6, 52(a0)
+; RV32IXQCCMP-SR-NEXT: sw s5, 48(a0)
+; RV32IXQCCMP-SR-NEXT: sw s4, 44(a0)
+; RV32IXQCCMP-SR-NEXT: sw s3, 40(a0)
+; RV32IXQCCMP-SR-NEXT: sw s2, 36(a0)
+; RV32IXQCCMP-SR-NEXT: sw t6, 32(a0)
+; RV32IXQCCMP-SR-NEXT: sw t5, 28(a0)
+; RV32IXQCCMP-SR-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-SR-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: sw a1, 16(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: sw a1, 12(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 20(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: sw a1, 8(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 24(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: sw a1, 4(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 28(sp) # 4-byte Folded Reload
+; RV32IXQCCMP-SR-NEXT: sw a1, 0(a0)
; RV32IXQCCMP-SR-NEXT: qc.cm.popret {ra, s0-s11}, 96
;
; RV64IXQCCMP-SR-LABEL: callee_no_irq:
@@ -3693,84 +3649,82 @@ define void @callee_no_irq() {
; RV64IXQCCMP-SR-NEXT: .cfi_offset s9, -88
; RV64IXQCCMP-SR-NEXT: .cfi_offset s10, -96
; RV64IXQCCMP-SR-NEXT: .cfi_offset s11, -104
-; RV64IXQCCMP-SR-NEXT: lui t0, %hi(var_test_irq)
-; RV64IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq)(t0)
-; RV64IXQCCMP-SR-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-SR-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-SR-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-SR-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: addi a5, t0, %lo(var_test_irq)
-; RV64IXQCCMP-SR-NEXT: lw a0, 16(a5)
-; RV64IXQCCMP-SR-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw a0, 20(a5)
-; RV64IXQCCMP-SR-NEXT: sd a0, 0(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw t4, 24(a5)
-; RV64IXQCCMP-SR-NEXT: lw t5, 28(a5)
-; RV64IXQCCMP-SR-NEXT: lw t6, 32(a5)
-; RV64IXQCCMP-SR-NEXT: lw s2, 36(a5)
-; RV64IXQCCMP-SR-NEXT: lw s3, 40(a5)
-; RV64IXQCCMP-SR-NEXT: lw s4, 44(a5)
-; RV64IXQCCMP-SR-NEXT: lw s5, 48(a5)
-; RV64IXQCCMP-SR-NEXT: lw s6, 52(a5)
-; RV64IXQCCMP-SR-NEXT: lw s7, 56(a5)
-; RV64IXQCCMP-SR-NEXT: lw s8, 60(a5)
-; RV64IXQCCMP-SR-NEXT: lw s9, 64(a5)
-; RV64IXQCCMP-SR-NEXT: lw s10, 68(a5)
-; RV64IXQCCMP-SR-NEXT: lw s11, 72(a5)
-; RV64IXQCCMP-SR-NEXT: lw ra, 76(a5)
-; RV64IXQCCMP-SR-NEXT: lw s1, 80(a5)
-; RV64IXQCCMP-SR-NEXT: lw t3, 84(a5)
-; RV64IXQCCMP-SR-NEXT: lw t2, 88(a5)
-; RV64IXQCCMP-SR-NEXT: lw t1, 92(a5)
-; RV64IXQCCMP-SR-NEXT: lw a7, 112(a5)
-; RV64IXQCCMP-SR-NEXT: lw s0, 116(a5)
-; RV64IXQCCMP-SR-NEXT: lw a3, 120(a5)
-; RV64IXQCCMP-SR-NEXT: lw a0, 124(a5)
-; RV64IXQCCMP-SR-NEXT: lw a6, 96(a5)
-; RV64IXQCCMP-SR-NEXT: lw a4, 100(a5)
-; RV64IXQCCMP-SR-NEXT: lw a2, 104(a5)
-; RV64IXQCCMP-SR-NEXT: lw a1, 108(a5)
-; RV64IXQCCMP-SR-NEXT: sw a0, 124(a5)
-; RV64IXQCCMP-SR-NEXT: sw a3, 120(a5)
-; RV64IXQCCMP-SR-NEXT: sw s0, 116(a5)
-; RV64IXQCCMP-SR-NEXT: sw a7, 112(a5)
-; RV64IXQCCMP-SR-NEXT: sw a1, 108(a5)
-; RV64IXQCCMP-SR-NEXT: sw a2, 104(a5)
-; RV64IXQCCMP-SR-NEXT: sw a4, 100(a5)
-; RV64IXQCCMP-SR-NEXT: sw a6, 96(a5)
-; RV64IXQCCMP-SR-NEXT: sw t1, 92(a5)
-; RV64IXQCCMP-SR-NEXT: sw t2, 88(a5)
-; RV64IXQCCMP-SR-NEXT: sw t3, 84(a5)
-; RV64IXQCCMP-SR-NEXT: sw s1, 80(a5)
-; RV64IXQCCMP-SR-NEXT: sw ra, 76(a5)
-; RV64IXQCCMP-SR-NEXT: sw s11, 72(a5)
-; RV64IXQCCMP-SR-NEXT: sw s10, 68(a5)
-; RV64IXQCCMP-SR-NEXT: sw s9, 64(a5)
-; RV64IXQCCMP-SR-NEXT: sw s8, 60(a5)
-; RV64IXQCCMP-SR-NEXT: sw s7, 56(a5)
-; RV64IXQCCMP-SR-NEXT: sw s6, 52(a5)
-; RV64IXQCCMP-SR-NEXT: sw s5, 48(a5)
-; RV64IXQCCMP-SR-NEXT: sw s4, 44(a5)
-; RV64IXQCCMP-SR-NEXT: sw s3, 40(a5)
-; RV64IXQCCMP-SR-NEXT: sw s2, 36(a5)
-; RV64IXQCCMP-SR-NEXT: sw t6, 32(a5)
-; RV64IXQCCMP-SR-NEXT: sw t5, 28(a5)
-; RV64IXQCCMP-SR-NEXT: sw t4, 24(a5)
-; RV64IXQCCMP-SR-NEXT: ld a0, 0(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, 20(a5)
-; RV64IXQCCMP-SR-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, 16(a5)
-; RV64IXQCCMP-SR-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+12)(t0)
-; RV64IXQCCMP-SR-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+8)(t0)
-; RV64IXQCCMP-SR-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq+4)(t0)
-; RV64IXQCCMP-SR-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
-; RV64IXQCCMP-SR-NEXT: sw a0, %lo(var_test_irq)(t0)
+; RV64IXQCCMP-SR-NEXT: lui a0, %hi(var_test_irq)
+; RV64IXQCCMP-SR-NEXT: addi a0, a0, %lo(var_test_irq)
+; RV64IXQCCMP-SR-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-SR-NEXT: sd a1, 40(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: lw a1, 4(a0)
+; RV64IXQCCMP-SR-NEXT: sd a1, 32(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: lw a1, 8(a0)
+; RV64IXQCCMP-SR-NEXT: sd a1, 24(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: lw a1, 12(a0)
+; RV64IXQCCMP-SR-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: lw a1, 16(a0)
+; RV64IXQCCMP-SR-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; RV64IXQCCMP-SR-NEXT: lw t3, 20(a0)
+; RV64IXQCCMP-SR-NEXT: lw t4, 24(a0)
+; RV64IXQCCMP-SR-NEXT: lw t5, 28(a0)
+; RV64IXQCCMP-SR-NEXT: lw t6, 32(a0)
+; RV64IXQCCMP-SR-NEXT: lw s2, 36(a0)
+; RV64IXQCCMP-SR-NEXT: lw s3, 40(a0)
+; RV64IXQCCMP-SR-NEXT: lw s4, 44(a0)
+; RV64IXQCCMP-SR-NEXT: lw s5, 48(a0)
+; RV64IXQCCMP-SR-NEXT: lw s6, 52(a0)
+; RV64IXQCCMP-SR-NEXT: lw s7, 56(a0)
+; RV64IXQCCMP-SR-NEXT: lw s8, 60(a0)
+; RV64IXQCCMP-SR-NEXT: lw s9, 64(a0)
+; RV64IXQCCMP-SR-NEXT: lw s10, 68(a0)
+; RV64IXQCCMP-SR-NEXT: lw s11, 72(a0)
+; RV64IXQCCMP-SR-NEXT: lw ra, 76(a0)
+; RV64IXQCCMP-SR-NEXT: lw t2, 80(a0)
+; RV64IXQCCMP-SR-NEXT: lw s0, 84(a0)
+; RV64IXQCCMP-SR-NEXT: lw s1, 88(a0)
+; RV64IXQCCMP-SR-NEXT: lw t1, 92(a0)
+; RV64IXQCCMP-SR-NEXT: lw t0, 112(a0)
+; RV64IXQCCMP-SR-NEXT: lw a5, 116(a0)
+; RV64IXQCCMP-SR-NEXT: lw a3, 120(a0)
+; RV64IXQCCMP-SR-NEXT: lw a1, 124(a0)
+; RV64IXQCCMP-SR-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-SR-NEXT: lw a6, 100(a0)
+; RV64IXQCCMP-SR-NEXT: lw a4, 104(a0)
+; RV64IXQCCMP-SR-NEXT: lw a2, 108(a0)
+; RV64IXQCCMP-SR-NEXT: sw a1, 124(a0)
+; RV64IXQCCMP-SR-NEXT: sw a3, 120(a0)
+; RV64IXQCCMP-SR-NEXT: sw a5, 116(a0)
+; RV64IXQCCMP-SR-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-SR-NEXT: sw a2, 108(a0)
+; RV64IXQCCMP-SR-NEXT: sw a4, 104(a0)
+; RV64IXQCCMP-SR-NEXT: sw a6, 100(a0)
+; RV64IXQCCMP-SR-NEXT: sw a7, 96(a0)
+; RV64IXQCCMP-SR-NEXT: sw t1, 92(a0)
+; RV64IXQCCMP-SR-NEXT: sw s1, 88(a0)
+; RV64IXQCCMP-SR-NEXT: sw s0, 84(a0)
+; RV64IXQCCMP-SR-NEXT: sw t2, 80(a0)
+; RV64IXQCCMP-SR-NEXT: sw ra, 76(a0)
+; RV64IXQCCMP-SR-NEXT: sw s11, 72(a0)
+; RV64IXQCCMP-SR-NEXT: sw s10, 68(a0)
+; RV64IXQCCMP-SR-NEXT: sw s9, 64(a0)
+; RV64IXQCCMP-SR-NEXT: sw s8, 60(a0)
+; RV64IXQCCMP-SR-NEXT: sw s7, 56(a0)
+; RV64IXQCCMP-SR-NEXT: sw s6, 52(a0)
+; RV64IXQCCMP-SR-NEXT: sw s5, 48(a0)
+; RV64IXQCCMP-SR-NEXT: sw s4, 44(a0)
+; RV64IXQCCMP-SR-NEXT: sw s3, 40(a0)
+; RV64IXQCCMP-SR-NEXT: sw s2, 36(a0)
+; RV64IXQCCMP-SR-NEXT: sw t6, 32(a0)
+; RV64IXQCCMP-SR-NEXT: sw t5, 28(a0)
+; RV64IXQCCMP-SR-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-SR-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-SR-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: sw a1, 16(a0)
+; RV64IXQCCMP-SR-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: sw a1, 12(a0)
+; RV64IXQCCMP-SR-NEXT: ld a1, 24(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: sw a1, 8(a0)
+; RV64IXQCCMP-SR-NEXT: ld a1, 32(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: sw a1, 4(a0)
+; RV64IXQCCMP-SR-NEXT: ld a1, 40(sp) # 8-byte Folded Reload
+; RV64IXQCCMP-SR-NEXT: sw a1, 0(a0)
; RV64IXQCCMP-SR-NEXT: qc.cm.popret {ra, s0-s11}, 160
%val = load [32 x i32], ptr @var_test_irq
store volatile [32 x i32] %val, ptr @var_test_irq
diff --git a/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll b/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
index 988bb6ffb8915..b48e039dd30a4 100644
--- a/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
+++ b/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
@@ -502,16 +502,16 @@ define void @test7() nounwind {
; RV32I-LABEL: test7:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, %hi(arr1)
-; RV32I-NEXT: sw zero, %lo(arr1)(a0)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: sw zero, 0(a0)
; RV32I-NEXT: sw zero, 4(a0)
; RV32I-NEXT: ret
;
; RV32IXQCILSM-LABEL: test7:
; RV32IXQCILSM: # %bb.0:
; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
-; RV32IXQCILSM-NEXT: sw zero, %lo(arr1)(a0)
; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: sw zero, 0(a0)
; RV32IXQCILSM-NEXT: sw zero, 4(a0)
; RV32IXQCILSM-NEXT: ret
tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 8, i1 false)
@@ -535,25 +535,25 @@ define void @test7a_unalign() nounwind {
; RV32I-LABEL: test7a_unalign:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
-; RV32I-NEXT: li a1, -1
-; RV32I-NEXT: sw a1, %lo(arr1)(a0)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: li a1, -1
+; RV32I-NEXT: sb a1, 16(a0)
+; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a1, 12(a0)
-; RV32I-NEXT: sb a1, 16(a0)
; RV32I-NEXT: ret
;
; RV32IXQCILSM-LABEL: test7a_unalign:
; RV32IXQCILSM: # %bb.0: # %entry
; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
-; RV32IXQCILSM-NEXT: li a1, -1
-; RV32IXQCILSM-NEXT: sw a1, %lo(arr1)(a0)
; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: li a1, -1
+; RV32IXQCILSM-NEXT: sb a1, 16(a0)
+; RV32IXQCILSM-NEXT: sw a1, 0(a0)
; RV32IXQCILSM-NEXT: sw a1, 4(a0)
; RV32IXQCILSM-NEXT: sw a1, 8(a0)
; RV32IXQCILSM-NEXT: sw a1, 12(a0)
-; RV32IXQCILSM-NEXT: sb a1, 16(a0)
; RV32IXQCILSM-NEXT: ret
entry:
tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 -1, i32 17, i1 false)
@@ -656,8 +656,8 @@ define void @test8() nounwind {
; RV32I-LABEL: test8:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
-; RV32I-NEXT: sw zero, %lo(arr1)(a0)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: sw zero, 0(a0)
; RV32I-NEXT: sw zero, 4(a0)
; RV32I-NEXT: sw zero, 8(a0)
; RV32I-NEXT: sw zero, 12(a0)
@@ -666,8 +666,8 @@ define void @test8() nounwind {
; RV32IXQCILSM-LABEL: test8:
; RV32IXQCILSM: # %bb.0: # %entry
; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
-; RV32IXQCILSM-NEXT: sw zero, %lo(arr1)(a0)
; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: sw zero, 0(a0)
; RV32IXQCILSM-NEXT: sw zero, 4(a0)
; RV32IXQCILSM-NEXT: sw zero, 8(a0)
; RV32IXQCILSM-NEXT: sw zero, 12(a0)
@@ -681,29 +681,29 @@ define void @test9() nounwind {
; RV32I-LABEL: test9:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(arr1)
-; RV32I-NEXT: sw zero, %lo(arr1)(a0)
; RV32I-NEXT: addi a0, a0, %lo(arr1)
+; RV32I-NEXT: sw zero, 16(a0)
; RV32I-NEXT: sw zero, 20(a0)
; RV32I-NEXT: sw zero, 24(a0)
; RV32I-NEXT: sw zero, 28(a0)
+; RV32I-NEXT: sw zero, 0(a0)
; RV32I-NEXT: sw zero, 4(a0)
; RV32I-NEXT: sw zero, 8(a0)
; RV32I-NEXT: sw zero, 12(a0)
-; RV32I-NEXT: sw zero, 16(a0)
; RV32I-NEXT: ret
;
; RV32IXQCILSM-LABEL: test9:
; RV32IXQCILSM: # %bb.0: # %entry
; RV32IXQCILSM-NEXT: lui a0, %hi(arr1)
-; RV32IXQCILSM-NEXT: sw zero, %lo(arr1)(a0)
; RV32IXQCILSM-NEXT: addi a0, a0, %lo(arr1)
+; RV32IXQCILSM-NEXT: sw zero, 16(a0)
; RV32IXQCILSM-NEXT: sw zero, 20(a0)
; RV32IXQCILSM-NEXT: sw zero, 24(a0)
; RV32IXQCILSM-NEXT: sw zero, 28(a0)
+; RV32IXQCILSM-NEXT: sw zero, 0(a0)
; RV32IXQCILSM-NEXT: sw zero, 4(a0)
; RV32IXQCILSM-NEXT: sw zero, 8(a0)
; RV32IXQCILSM-NEXT: sw zero, 12(a0)
-; RV32IXQCILSM-NEXT: sw zero, 16(a0)
; RV32IXQCILSM-NEXT: ret
entry:
tail call void @llvm.memset.p0.i32(ptr align 4 @arr1, i8 0, i32 32, i1 false)
diff --git a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
index 1ef37f73b3b08..c561b6ddb1add 100644
--- a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
+++ b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
@@ -219,31 +219,31 @@ define void @foo7(ptr nocapture %p) nounwind {
; RV32ZDINX-LABEL: foo7:
; RV32ZDINX: # %bb.0: # %entry
; RV32ZDINX-NEXT: lui a1, %hi(d)
-; RV32ZDINX-NEXT: addi a2, a1, %lo(d)
-; RV32ZDINX-NEXT: lw a1, %lo(d+4)(a1)
-; RV32ZDINX-NEXT: lw a2, 8(a2)
+; RV32ZDINX-NEXT: addi a1, a1, %lo(d)
+; RV32ZDINX-NEXT: lw a2, 8(a1)
+; RV32ZDINX-NEXT: lw a1, 4(a1)
; RV32ZDINX-NEXT: addi a3, a0, 2044
-; RV32ZDINX-NEXT: sw a1, 2044(a0)
; RV32ZDINX-NEXT: sw a2, 4(a3)
+; RV32ZDINX-NEXT: sw a1, 2044(a0)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo7:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: lui a1, %hi(d)
-; RV32ZDINXUALIGNED-NEXT: addi a2, a1, %lo(d)
-; RV32ZDINXUALIGNED-NEXT: lw a1, %lo(d+4)(a1)
-; RV32ZDINXUALIGNED-NEXT: lw a2, 8(a2)
+; RV32ZDINXUALIGNED-NEXT: addi a1, a1, %lo(d)
+; RV32ZDINXUALIGNED-NEXT: lw a2, 8(a1)
+; RV32ZDINXUALIGNED-NEXT: lw a1, 4(a1)
; RV32ZDINXUALIGNED-NEXT: addi a3, a0, 2044
-; RV32ZDINXUALIGNED-NEXT: sw a1, 2044(a0)
; RV32ZDINXUALIGNED-NEXT: sw a2, 4(a3)
+; RV32ZDINXUALIGNED-NEXT: sw a1, 2044(a0)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo7:
; RV64ZDINX: # %bb.0: # %entry
; RV64ZDINX-NEXT: lui a1, %hi(d)
-; RV64ZDINX-NEXT: addi a2, a1, %lo(d)
-; RV64ZDINX-NEXT: lw a2, 8(a2)
-; RV64ZDINX-NEXT: lwu a1, %lo(d+4)(a1)
+; RV64ZDINX-NEXT: addi a1, a1, %lo(d)
+; RV64ZDINX-NEXT: lw a2, 8(a1)
+; RV64ZDINX-NEXT: lwu a1, 4(a1)
; RV64ZDINX-NEXT: slli a2, a2, 32
; RV64ZDINX-NEXT: or a1, a2, a1
; RV64ZDINX-NEXT: sd a1, 2044(a0)
@@ -260,28 +260,28 @@ define void @foo8(ptr %p) nounwind {
; RV32ZDINX-LABEL: foo8:
; RV32ZDINX: # %bb.0: # %entry
; RV32ZDINX-NEXT: addi sp, sp, -16
-; RV32ZDINX-NEXT: sw a0, 8(sp)
; RV32ZDINX-NEXT: addi a1, a0, 2044
-; RV32ZDINX-NEXT: lw a0, 2044(a0)
+; RV32ZDINX-NEXT: lw a2, 2044(a0)
; RV32ZDINX-NEXT: lw a1, 4(a1)
-; RV32ZDINX-NEXT: lui a2, %hi(d)
-; RV32ZDINX-NEXT: addi a3, a2, %lo(d)
-; RV32ZDINX-NEXT: sw a0, %lo(d+4)(a2)
-; RV32ZDINX-NEXT: sw a1, 8(a3)
+; RV32ZDINX-NEXT: sw a0, 8(sp)
+; RV32ZDINX-NEXT: lui a0, %hi(d)
+; RV32ZDINX-NEXT: addi a0, a0, %lo(d)
+; RV32ZDINX-NEXT: sw a2, 4(a0)
+; RV32ZDINX-NEXT: sw a1, 8(a0)
; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo8:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: addi sp, sp, -16
-; RV32ZDINXUALIGNED-NEXT: sw a0, 8(sp)
; RV32ZDINXUALIGNED-NEXT: addi a1, a0, 2044
-; RV32ZDINXUALIGNED-NEXT: lw a0, 2044(a0)
+; RV32ZDINXUALIGNED-NEXT: lw a2, 2044(a0)
; RV32ZDINXUALIGNED-NEXT: lw a1, 4(a1)
-; RV32ZDINXUALIGNED-NEXT: lui a2, %hi(d)
-; RV32ZDINXUALIGNED-NEXT: addi a3, a2, %lo(d)
-; RV32ZDINXUALIGNED-NEXT: sw a0, %lo(d+4)(a2)
-; RV32ZDINXUALIGNED-NEXT: sw a1, 8(a3)
+; RV32ZDINXUALIGNED-NEXT: sw a0, 8(sp)
+; RV32ZDINXUALIGNED-NEXT: lui a0, %hi(d)
+; RV32ZDINXUALIGNED-NEXT: addi a0, a0, %lo(d)
+; RV32ZDINXUALIGNED-NEXT: sw a2, 4(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a1, 8(a0)
; RV32ZDINXUALIGNED-NEXT: addi sp, sp, 16
; RV32ZDINXUALIGNED-NEXT: ret
;
@@ -291,10 +291,10 @@ define void @foo8(ptr %p) nounwind {
; RV64ZDINX-NEXT: ld a1, 2044(a0)
; RV64ZDINX-NEXT: sd a0, 8(sp)
; RV64ZDINX-NEXT: lui a0, %hi(d)
-; RV64ZDINX-NEXT: addi a2, a0, %lo(d)
-; RV64ZDINX-NEXT: sw a1, %lo(d+4)(a0)
-; RV64ZDINX-NEXT: srli a1, a1, 32
-; RV64ZDINX-NEXT: sw a1, 8(a2)
+; RV64ZDINX-NEXT: addi a0, a0, %lo(d)
+; RV64ZDINX-NEXT: srli a2, a1, 32
+; RV64ZDINX-NEXT: sw a1, 4(a0)
+; RV64ZDINX-NEXT: sw a2, 8(a0)
; RV64ZDINX-NEXT: addi sp, sp, 16
; RV64ZDINX-NEXT: ret
entry:
@@ -314,31 +314,31 @@ define void @foo9(ptr nocapture %p) nounwind {
; RV32ZDINX-LABEL: foo9:
; RV32ZDINX: # %bb.0: # %entry
; RV32ZDINX-NEXT: lui a1, %hi(e)
-; RV32ZDINX-NEXT: addi a2, a1, %lo(e)
-; RV32ZDINX-NEXT: lw a1, %lo(e)(a1)
-; RV32ZDINX-NEXT: lw a2, 4(a2)
+; RV32ZDINX-NEXT: addi a1, a1, %lo(e)
+; RV32ZDINX-NEXT: lw a2, 4(a1)
+; RV32ZDINX-NEXT: lw a1, 0(a1)
; RV32ZDINX-NEXT: addi a3, a0, 2044
-; RV32ZDINX-NEXT: sw a1, 2044(a0)
; RV32ZDINX-NEXT: sw a2, 4(a3)
+; RV32ZDINX-NEXT: sw a1, 2044(a0)
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo9:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: lui a1, %hi(e)
-; RV32ZDINXUALIGNED-NEXT: addi a2, a1, %lo(e)
-; RV32ZDINXUALIGNED-NEXT: lw a1, %lo(e)(a1)
-; RV32ZDINXUALIGNED-NEXT: lw a2, 4(a2)
+; RV32ZDINXUALIGNED-NEXT: addi a1, a1, %lo(e)
+; RV32ZDINXUALIGNED-NEXT: lw a2, 4(a1)
+; RV32ZDINXUALIGNED-NEXT: lw a1, 0(a1)
; RV32ZDINXUALIGNED-NEXT: addi a3, a0, 2044
-; RV32ZDINXUALIGNED-NEXT: sw a1, 2044(a0)
; RV32ZDINXUALIGNED-NEXT: sw a2, 4(a3)
+; RV32ZDINXUALIGNED-NEXT: sw a1, 2044(a0)
; RV32ZDINXUALIGNED-NEXT: ret
;
; RV64ZDINX-LABEL: foo9:
; RV64ZDINX: # %bb.0: # %entry
; RV64ZDINX-NEXT: lui a1, %hi(e)
-; RV64ZDINX-NEXT: addi a2, a1, %lo(e)
-; RV64ZDINX-NEXT: lw a2, 4(a2)
-; RV64ZDINX-NEXT: lwu a1, %lo(e)(a1)
+; RV64ZDINX-NEXT: addi a1, a1, %lo(e)
+; RV64ZDINX-NEXT: lw a2, 4(a1)
+; RV64ZDINX-NEXT: lwu a1, 0(a1)
; RV64ZDINX-NEXT: slli a2, a2, 32
; RV64ZDINX-NEXT: or a1, a2, a1
; RV64ZDINX-NEXT: sd a1, 2044(a0)
@@ -354,28 +354,28 @@ define void @foo10(ptr %p) nounwind {
; RV32ZDINX-LABEL: foo10:
; RV32ZDINX: # %bb.0: # %entry
; RV32ZDINX-NEXT: addi sp, sp, -16
+; RV32ZDINX-NEXT: addi a1, a0, 2044
+; RV32ZDINX-NEXT: lw a2, 2044(a0)
+; RV32ZDINX-NEXT: lw a1, 4(a1)
; RV32ZDINX-NEXT: sw a0, 8(sp)
-; RV32ZDINX-NEXT: lw a1, 2044(a0)
-; RV32ZDINX-NEXT: addi a0, a0, 2044
-; RV32ZDINX-NEXT: lw a0, 4(a0)
-; RV32ZDINX-NEXT: lui a2, %hi(e)
-; RV32ZDINX-NEXT: sw a1, %lo(e)(a2)
-; RV32ZDINX-NEXT: addi a1, a2, %lo(e)
-; RV32ZDINX-NEXT: sw a0, 4(a1)
+; RV32ZDINX-NEXT: lui a0, %hi(e)
+; RV32ZDINX-NEXT: addi a0, a0, %lo(e)
+; RV32ZDINX-NEXT: sw a2, 0(a0)
+; RV32ZDINX-NEXT: sw a1, 4(a0)
; RV32ZDINX-NEXT: addi sp, sp, 16
; RV32ZDINX-NEXT: ret
;
; RV32ZDINXUALIGNED-LABEL: foo10:
; RV32ZDINXUALIGNED: # %bb.0: # %entry
; RV32ZDINXUALIGNED-NEXT: addi sp, sp, -16
+; RV32ZDINXUALIGNED-NEXT: addi a1, a0, 2044
+; RV32ZDINXUALIGNED-NEXT: lw a2, 2044(a0)
+; RV32ZDINXUALIGNED-NEXT: lw a1, 4(a1)
; RV32ZDINXUALIGNED-NEXT: sw a0, 8(sp)
-; RV32ZDINXUALIGNED-NEXT: lw a1, 2044(a0)
-; RV32ZDINXUALIGNED-NEXT: addi a0, a0, 2044
-; RV32ZDINXUALIGNED-NEXT: lw a0, 4(a0)
-; RV32ZDINXUALIGNED-NEXT: lui a2, %hi(e)
-; RV32ZDINXUALIGNED-NEXT: sw a1, %lo(e)(a2)
-; RV32ZDINXUALIGNED-NEXT: addi a1, a2, %lo(e)
-; RV32ZDINXUALIGNED-NEXT: sw a0, 4(a1)
+; RV32ZDINXUALIGNED-NEXT: lui a0, %hi(e)
+; RV32ZDINXUALIGNED-NEXT: addi a0, a0, %lo(e)
+; RV32ZDINXUALIGNED-NEXT: sw a2, 0(a0)
+; RV32ZDINXUALIGNED-NEXT: sw a1, 4(a0)
; RV32ZDINXUALIGNED-NEXT: addi sp, sp, 16
; RV32ZDINXUALIGNED-NEXT: ret
;
@@ -385,10 +385,10 @@ define void @foo10(ptr %p) nounwind {
; RV64ZDINX-NEXT: ld a1, 2044(a0)
; RV64ZDINX-NEXT: sd a0, 8(sp)
; RV64ZDINX-NEXT: lui a0, %hi(e)
-; RV64ZDINX-NEXT: sw a1, %lo(e)(a0)
; RV64ZDINX-NEXT: addi a0, a0, %lo(e)
-; RV64ZDINX-NEXT: srli a1, a1, 32
-; RV64ZDINX-NEXT: sw a1, 4(a0)
+; RV64ZDINX-NEXT: srli a2, a1, 32
+; RV64ZDINX-NEXT: sw a1, 0(a0)
+; RV64ZDINX-NEXT: sw a2, 4(a0)
; RV64ZDINX-NEXT: addi sp, sp, 16
; RV64ZDINX-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
index abd49d6bf7575..4a78ea3a1688a 100644
--- a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
+++ b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
@@ -8,11 +8,11 @@ define dso_local i32 @test_zext_i8() nounwind {
; RV32I-LABEL: test_zext_i8:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(bytes)
-; RV32I-NEXT: lbu a1, %lo(bytes)(a0)
+; RV32I-NEXT: addi a0, a0, %lo(bytes)
+; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: li a2, 136
; RV32I-NEXT: bne a1, a2, .LBB0_3
; RV32I-NEXT: # %bb.1: # %entry
-; RV32I-NEXT: addi a0, a0, %lo(bytes)
; RV32I-NEXT: lbu a0, 1(a0)
; RV32I-NEXT: li a1, 7
; RV32I-NEXT: bne a0, a1, .LBB0_3
@@ -43,12 +43,12 @@ define dso_local i32 @test_zext_i16() nounwind {
; RV32I-LABEL: test_zext_i16:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(shorts)
-; RV32I-NEXT: lhu a1, %lo(shorts)(a0)
+; RV32I-NEXT: addi a0, a0, %lo(shorts)
+; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -120
; RV32I-NEXT: bne a1, a2, .LBB1_3
; RV32I-NEXT: # %bb.1: # %entry
-; RV32I-NEXT: addi a0, a0, %lo(shorts)
; RV32I-NEXT: lhu a0, 2(a0)
; RV32I-NEXT: li a1, 7
; RV32I-NEXT: bne a0, a1, .LBB1_3
>From aa2c56c436599bccec5560aa66f4fff243337bab Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 2 Sep 2025 08:30:42 -0700
Subject: [PATCH 2/3] Update llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Co-authored-by: Luke Lau <luke_lau at icloud.com>
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index c5b68ccd1ba8d..e4172df2a77af 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2974,7 +2974,8 @@ bool isRegImmLoadOrStore(SDNode *User, SDValue Add) {
return true;
}
-// To prevent SelectAddrRegImm from folding offsets that conflicts with the
+// To prevent SelectAddrRegImm from folding offsets that conflict with the
+// fusion of PseudoMovAddr, check if the offset of every use of a given address
// fusion of PseudoMovAddr, check if the offset of every use of a given address
// is within the alignment.
bool RISCVDAGToDAGISel::areOffsetsWithinAlignment(SDValue Addr,
>From 5433c0b42308ff1af5f41ceacb6fd46869e9eb23 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 3 Sep 2025 17:01:34 -0700
Subject: [PATCH 3/3] Address review comments
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 40 +++++++++++----------
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e4172df2a77af..f7ad3cc1633d1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2952,31 +2952,35 @@ static bool isWorthFoldingAdd(SDValue Add) {
}
bool isRegImmLoadOrStore(SDNode *User, SDValue Add) {
- // If the user is a load or store, then the offset is 0.
- if (User->getOpcode() != ISD::LOAD && User->getOpcode() != ISD::STORE &&
- User->getOpcode() != RISCVISD::LD_RV32 &&
- User->getOpcode() != RISCVISD::SD_RV32 &&
- User->getOpcode() != ISD::ATOMIC_LOAD &&
- User->getOpcode() != ISD::ATOMIC_STORE)
- return false;
-
- // Don't allow stores of the value. It must be used as the address.
- if (User->getOpcode() == ISD::STORE &&
- cast<StoreSDNode>(User)->getValue() == Add)
- return false;
- if (User->getOpcode() == RISCVISD::SD_RV32 &&
- (User->getOperand(0) == Add || User->getOperand(1) == Add))
- return false;
- if (User->getOpcode() == ISD::ATOMIC_STORE &&
- cast<AtomicSDNode>(User)->getVal() == Add)
+ switch (User->getOpcode()) {
+ default:
return false;
+ case ISD::LOAD:
+ case RISCVISD::LD_RV32:
+ case ISD::ATOMIC_LOAD:
+ break;
+ case ISD::STORE:
+ // Don't allow stores of Add. It must only be used as the address.
+ if (cast<StoreSDNode>(User)->getValue() == Add)
+ return false;
+ break;
+ case RISCVISD::SD_RV32:
+ // Don't allow stores of Add. It must only be used as the address.
+ if (User->getOperand(0) == Add || User->getOperand(1) == Add)
+ return false;
+ break;
+ case ISD::ATOMIC_STORE:
+ // Don't allow stores of Add. It must only be used as the address.
+ if (cast<AtomicSDNode>(User)->getVal() == Add)
+ return false;
+ break;
+ }
return true;
}
// To prevent SelectAddrRegImm from folding offsets that conflict with the
// fusion of PseudoMovAddr, check if the offset of every use of a given address
-// fusion of PseudoMovAddr, check if the offset of every use of a given address
// is within the alignment.
bool RISCVDAGToDAGISel::areOffsetsWithinAlignment(SDValue Addr,
Align Alignment) {
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