[llvm] [AArch64][SME] Introduce CHECK_MATCHING_VL pseudo for streaming transitions (PR #157510)

[Benjamin Maxwell via llvm-commits]

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@@ -9147,7 +9197,40 @@ SDValue AArch64TargetLowering::changeStreamingMode(SelectionDAG &DAG, SDLoc DL,
   if (InGlue)
     Ops.push_back(InGlue);
 
-  return DAG.getNode(Opcode, DL, DAG.getVTList(MVT::Other, MVT::Glue), Ops);
+  if (!HasSVECC)
+    return DAG.getNode(Opcode, DL, DAG.getVTList(MVT::Other, MVT::Glue), Ops);
+
+  auto GetCheckVL = [&](SDValue Chain, SDValue InGlue = SDValue()) -> SDValue {
+    SmallVector<SDValue, 2> Ops = {Chain};
+    if (InGlue)
+      Ops.push_back(InGlue);
+    return SDValue(DAG.getMachineNode(AArch64::CHECK_MATCHING_VL, DL,
+                                      DAG.getVTList(MVT::Other, MVT::Glue),
+                                      Ops),
+                   0);
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MacDue wrote:

We don't typically directly emit the machine node in SDAG. The standard thing would be to create an `AArch64ISD::CHECK_MATCHING_VL` + a pattern to lower it to the pseudo in table-gen.

An example is something like:
https://github.com/llvm/llvm-project/blob/819aa3521ead28abaa9df6b35dca0529f4524fb8/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td#L108-L111

https://github.com/llvm/llvm-project/pull/157510