[llvm] [AArch64] Correct SCVTF/UCVTF instructions for vector input (PR #152974)

[Amina Chabane via llvm-commits]

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@@ -5520,7 +5520,6 @@ multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPa
     let Inst{31} = 1; // 64-bit FPR flag
     let Inst{23-22} = 0b00; // 32-bit FPR flag
   }
-
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Amichaxx wrote:

Removed now.

https://github.com/llvm/llvm-project/pull/152974