[llvm] [AArch64] Correct SCVTF/UCVTF instructions for vector input (PR #152974)

[Eli Friedman via llvm-commits]

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@@ -202,10 +196,8 @@ define float @scvtf_f32i64_neg(<2 x i64> %x) {
  ret float %conv
 }
 
-; This test does not give the indended result of scvtf s0, d0
-; This is due to the input being loaded as a 2 item vector and
-; therefore using vector inputs that do not match the pattern
-; This test will be fixed in a future revision
+; <1 x float> is illegal on AArch64 and is widened to <2 x float>.
+; This widening introduces the extra insert/extract/zeroing instructions.
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efriedma-quic wrote:

Not really related to this patch, but scvtf zeros the high bits of the register.  So theoretically we should be able to pattern-match the extra zeroing operation.  Not sure if it's worth spending the time to implement.

https://github.com/llvm/llvm-project/pull/152974