[llvm] [X86] X86TargetLowering::computeKnownBitsForTargetNode - add X86ISD::VPMADD52L\H handling (PR #156349)

[Simon Pilgrim via llvm-commits]

=?utf-8?b?6buD5ZyL5bqt?= <we3223 at gmail.com>,william <we3223 at gmail.com>,william
 <we3223 at gmail.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/156349 at github.com>


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@@ -38997,6 +38997,28 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     }
     break;
   }
+  case X86ISD::VPMADD52L:
+  case X86ISD::VPMADD52H: {
+    EVT VT = Op.getValueType();
+    if (!VT.isVector() || VT.getScalarSizeInBits() != 64) {
----------------
RKSimon wrote:

this should never happen - so just assert instead:
```
assert(Op.getValueType().isVector() && Op.getValueType().getScalarType() == MVT::i64 && "Unexpected VPMADD52 type");
```

https://github.com/llvm/llvm-project/pull/156349