[llvm] [RISCV] Use C.ADD when OR is not compressible due to register restriction (PR #156044)

[Craig Topper via llvm-commits]

topperc wrote:

I spoke with Philip earlier. We believe the transforms done by RISCVOptWInstrs invalidate the Disjoint flag, but don't clear the flag. For example, we can no longer guarantee the upper bits are disjoint if we optimize based on demanded bits.

I'm not sure the intended transform in this patch is violated by RISCVOptWInstrs I just know the flag itself does not accurately describe the upper bits as it should.

https://github.com/llvm/llvm-project/pull/156044