[llvm] [AArch64] Lower zero cycle FPR zeroing (PR #156261)

[David Green via llvm-commits]

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@@ -5469,8 +5469,24 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   // Copies between GPR64 and FPR64.
   if (AArch64::FPR64RegClass.contains(DestReg) &&
       AArch64::GPR64RegClass.contains(SrcReg)) {
-    BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
-        .addReg(SrcReg, getKillRegState(KillSrc));
+    if (AArch64::XZR == SrcReg &&
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davemgreen wrote:

Could this just generate a FMOVD0? Same for the S variant - it would help centralize the logic.

https://github.com/llvm/llvm-project/pull/156261