[llvm] [AArch64][GlobalISel] Add codegen for simd fpcvt instructions (PR #156892)

[via llvm-commits]

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@@ -5257,6 +5294,52 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string IN
   def : Pat<(i64 (to_int_sat_gi f64:$Rn)),
             (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
 
+  // For global-isel we can use register classes to determine
+  // which FCVT instruction to use.
+  let Predicates = [HasFPRCVT] in {
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Lukacma wrote:

Apologies. I have forgotten to regenerate tests and let a bug slip by. It is fixed now so you should be able to see that without these patterns we have suboptimal codegen.

https://github.com/llvm/llvm-project/pull/156892