[llvm] [AArch64][GlobalISel] Add codegen for simd fpcvt instructions (PR #156892)

[via llvm-commits]

================
@@ -7949,6 +7950,21 @@ multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm> {
   }
 }
 
+let mayRaiseFPException = 1, Uses = [FPCR] in
+multiclass SIMDFPTwoScalarFCVT<bit U, bit S, bits<5> opc, string asm,
+                               SDPatternOperator OpN> {
+  let Predicates = [HasNEONandIsStreamingSafe], FastISelShouldIgnore = 1  in {
----------------
Lukacma wrote:

I added it because it fails with FastISel. I didn't really investigate why it fails, as I thought FastISel is not really important.

They are under Scalar single-precision and double-precision section on the webpage

https://github.com/llvm/llvm-project/pull/156892