[llvm] [AArch64][GlobalISel] Add codegen for simd fpcvt instructions (PR #156892)

[via llvm-commits]

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@@ -5301,6 +5384,32 @@ multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
   def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>;
   def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>;
 
+  // For global-isel we can use register classes to determine
+  // which FCVT instruction to use.
+  let Predicates = [HasFPRCVT] in {
+  def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # SHr) $Rn)>;
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CarolineConcatto wrote:

Why do we need these patterns, nothing changes when they are removed.

https://github.com/llvm/llvm-project/pull/156892