[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Chris Jackson via llvm-commits]

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@@ -14592,6 +14674,37 @@ SITargetLowering::performExtractVectorEltCombine(SDNode *N,
     return DAG.getNode(Vec.getOpcode(), SL, ResVT, Elt);
   }
 
+  // (extract_vector_element (and {y0, y1}, (build_vector 0x1f, 0x1f)), index)
+  // -> (and (extract_vector_element {y0, y1}, index), 0x1f)
+  // There are optimisations to transform 64-bit shifts into 32-bit shifts
+  // depending on the shift operand. See e.g. performSraCombine().
+  // This combine ensures that the optimisation is compatible with v2i32
+  // legalised AND.
+  // TODO: Consider if additional improvements can be made by generalising to
+  // other constants and vector types.
+  if (VecVT == MVT::v2i32 && Vec->getOpcode() == ISD::AND &&
+      Vec->getOperand(1)->getOpcode() == ISD::BUILD_VECTOR) {
+    SDValue BV = Vec->getOperand(1);
+
+    ConstantSDNode *BV0 = dyn_cast<ConstantSDNode>(BV->getOperand(0));
+    ConstantSDNode *BV1 = dyn_cast<ConstantSDNode>(BV->getOperand(1));
+
+    if (!BV0 || !BV1 || BV->getConstantOperandVal(0) != 0x1f ||
+        BV->getConstantOperandVal(1) != 0x1f)
+      return SDValue();
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chrisjbris wrote:

getSplatValue() Doesn't appear to be available here.

https://github.com/llvm/llvm-project/pull/140694