[llvm] [VectorCombine] foldSelectShuffle - early-out cases where the max vector register width isn't large enough (PR #157430)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/157430

>From 31a537aacc36c1f44f6f32985ba6be2135d9a193 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Mon, 8 Sep 2025 12:27:39 +0100
Subject: [PATCH 1/2] [VectorCombine] foldSelectShuffle - early-out cases where
 the max vector register width isn't large enough

Technically this could happen with vector units that can't handle all legal scalar widths - but good enough to use a generic crash test without a suitable target

Fixes #157335
---
 llvm/lib/Transforms/Vectorize/VectorCombine.cpp |  2 ++
 llvm/test/Transforms/VectorCombine/pr157335.ll  | 11 +++++++++++
 2 files changed, 13 insertions(+)
 create mode 100644 llvm/test/Transforms/VectorCombine/pr157335.ll

diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 7a0b7ad57a493..9dd1532d1b230 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -3903,6 +3903,8 @@ bool VectorCombine::foldSelectShuffle(Instruction &I, bool FromReduction) {
   unsigned MaxVectorSize =
       TTI.getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector);
   unsigned MaxElementsInVector = MaxVectorSize / ElementSize;
+  if (MaxElementsInVector == 0)
+    return false;
   // When there are multiple shufflevector operations on the same input,
   // especially when the vector length is larger than the register size,
   // identical shuffle patterns may occur across different groups of elements.
diff --git a/llvm/test/Transforms/VectorCombine/pr157335.ll b/llvm/test/Transforms/VectorCombine/pr157335.ll
new file mode 100644
index 0000000000000..e942a996d016f
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/pr157335.ll
@@ -0,0 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=vector-combine -S %s | FileCheck %s
+
+define <2 x double> @PR157335() {
+  %v0 = fmul <2 x double> zeroinitializer, zeroinitializer
+  %v1 = fmul <2 x double> zeroinitializer, zeroinitializer
+  %v2 = fsub <2 x double> %v0, %v1
+  %v3 = fadd <2 x double> %v0, %v1
+  %v4 = shufflevector <2 x double> %v2, <2 x double> %v3, <2 x i32> <i32 0, i32 3>
+  ret <2 x double> %v4
+}
\ No newline at end of file

>From 1d000102d172c7dac1fe047f6aa4c114721c8ebd Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Mon, 8 Sep 2025 12:31:11 +0100
Subject: [PATCH 2/2] Regenerate test

---
 llvm/test/Transforms/VectorCombine/pr157335.ll | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/llvm/test/Transforms/VectorCombine/pr157335.ll b/llvm/test/Transforms/VectorCombine/pr157335.ll
index e942a996d016f..57eb1362d8995 100644
--- a/llvm/test/Transforms/VectorCombine/pr157335.ll
+++ b/llvm/test/Transforms/VectorCombine/pr157335.ll
@@ -2,10 +2,18 @@
 ; RUN: opt -passes=vector-combine -S %s | FileCheck %s
 
 define <2 x double> @PR157335() {
+; CHECK-LABEL: @PR157335(
+; CHECK-NEXT:    [[V0:%.*]] = fmul <2 x double> zeroinitializer, zeroinitializer
+; CHECK-NEXT:    [[V1:%.*]] = fmul <2 x double> zeroinitializer, zeroinitializer
+; CHECK-NEXT:    [[V2:%.*]] = fsub <2 x double> [[V0]], [[V1]]
+; CHECK-NEXT:    [[V3:%.*]] = fadd <2 x double> [[V0]], [[V1]]
+; CHECK-NEXT:    [[V4:%.*]] = shufflevector <2 x double> [[V2]], <2 x double> [[V3]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    ret <2 x double> [[V4]]
+;
   %v0 = fmul <2 x double> zeroinitializer, zeroinitializer
   %v1 = fmul <2 x double> zeroinitializer, zeroinitializer
   %v2 = fsub <2 x double> %v0, %v1
   %v3 = fadd <2 x double> %v0, %v1
   %v4 = shufflevector <2 x double> %v2, <2 x double> %v3, <2 x i32> <i32 0, i32 3>
   ret <2 x double> %v4
-}
\ No newline at end of file
+}