[llvm] [AArch64] Correct SCVTF/UCVTF instructions for vector input (PR #152974)
Amina Chabane via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 8 03:40:40 PDT 2025
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@@ -5520,6 +5520,11 @@ multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPa
let Inst{31} = 1; // 64-bit FPR flag
let Inst{23-22} = 0b00; // 32-bit FPR flag
}
+ def : Pat<(v1f64 (extract_subvector (v2f64 (node (v2i64 (sext (v2i32 V64:$Rn))))), (i64 0))),
+ (!cast<Instruction>(NAME # DSr) (EXTRACT_SUBREG V64:$Rn, ssub))>;
+
+ def : Pat<(v1f64 (extract_subvector (v2f64 (node (v2i64 (zext (v2i32 V64:$Rn))))), (i64 0))),
+ (!cast<Instruction>(NAME # DSr) (EXTRACT_SUBREG V64:$Rn, ssub))>;
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Amichaxx wrote:
Patterns have since been removed. I've ensured the new ones I've added are aligned.
https://github.com/llvm/llvm-project/pull/152974
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