[llvm] [RISCV] Replace undef with poison, NFC (PR #157396)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 8 00:29:56 PDT 2025
github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {undef deprecator}-->
:warning: undef deprecator found issues in your code. :warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git diff -U0 --pickaxe-regex -S '([^a-zA-Z0-9#_-]undef[^a-zA-Z0-9_-]|UndefValue::get)' 'HEAD~1' HEAD llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/ret.ll llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-bf16-err.ll llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-f16-err.ll llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll llvm/test/CodeGen/RISCV/double-calling-conv.ll llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll llvm/test/CodeGen/RISCV/rvv/commutable.ll llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compress-fp.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compress-int.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-extract-subvector.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-negative.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll llvm/test/CodeGen/RISCV/rvv/frm-insert.ll llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll llvm/test/CodeGen/RISCV/rvv/masked-load-int-e64.ll llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll llvm/test/CodeGen/RISCV/rvv/masked-tama.ll llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll llvm/test/CodeGen/RISCV/rvv/pr106109.ll llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll llvm/test/CodeGen/RISCV/rvv/vaadd.ll llvm/test/CodeGen/RISCV/rvv/vaaddu.ll llvm/test/CodeGen/RISCV/rvv/vadc.ll llvm/test/CodeGen/RISCV/rvv/vadd.ll llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll llvm/test/CodeGen/RISCV/rvv/vand.ll llvm/test/CodeGen/RISCV/rvv/vandn.ll llvm/test/CodeGen/RISCV/rvv/variant-cc.ll llvm/test/CodeGen/RISCV/rvv/vasub.ll llvm/test/CodeGen/RISCV/rvv/vasubu.ll llvm/test/CodeGen/RISCV/rvv/vbrev.ll llvm/test/CodeGen/RISCV/rvv/vbrev8.ll llvm/test/CodeGen/RISCV/rvv/vclmul.ll llvm/test/CodeGen/RISCV/rvv/vclmulh.ll llvm/test/CodeGen/RISCV/rvv/vclz.ll llvm/test/CodeGen/RISCV/rvv/vcpopv.ll llvm/test/CodeGen/RISCV/rvv/vctz.ll llvm/test/CodeGen/RISCV/rvv/vdiv.ll llvm/test/CodeGen/RISCV/rvv/vdivu.ll llvm/test/CodeGen/RISCV/rvv/vector-compress.ll llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll llvm/test/CodeGen/RISCV/rvv/vfadd.ll llvm/test/CodeGen/RISCV/rvv/vfclass.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfdiv.ll llvm/test/CodeGen/RISCV/rvv/vfmax.ll llvm/test/CodeGen/RISCV/rvv/vfmerge.ll llvm/test/CodeGen/RISCV/rvv/vfmin.ll llvm/test/CodeGen/RISCV/rvv/vfmul.ll llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvtbf16-f-f.ll llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll llvm/test/CodeGen/RISCV/rvv/vfrec7.ll llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll llvm/test/CodeGen/RISCV/rvv/vfrsub.ll llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll llvm/test/CodeGen/RISCV/rvv/vfsub.ll llvm/test/CodeGen/RISCV/rvv/vfwadd.ll llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvtbf16-f-f.ll llvm/test/CodeGen/RISCV/rvv/vfwmul.ll llvm/test/CodeGen/RISCV/rvv/vfwsub.ll llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll llvm/test/CodeGen/RISCV/rvv/vid.ll llvm/test/CodeGen/RISCV/rvv/viota.ll llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll llvm/test/CodeGen/RISCV/rvv/vle.ll llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll llvm/test/CodeGen/RISCV/rvv/vleff.ll llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll llvm/test/CodeGen/RISCV/rvv/vloxei.ll llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/vlse.ll llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll llvm/test/CodeGen/RISCV/rvv/vluxei.ll llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/vmax.ll llvm/test/CodeGen/RISCV/rvv/vmaxu.ll llvm/test/CodeGen/RISCV/rvv/vmerge.ll llvm/test/CodeGen/RISCV/rvv/vmin.ll llvm/test/CodeGen/RISCV/rvv/vminu.ll llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll llvm/test/CodeGen/RISCV/rvv/vmul.ll llvm/test/CodeGen/RISCV/rvv/vmulh.ll llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll llvm/test/CodeGen/RISCV/rvv/vmulhu.ll llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll llvm/test/CodeGen/RISCV/rvv/vnclip.ll llvm/test/CodeGen/RISCV/rvv/vnclipu.ll llvm/test/CodeGen/RISCV/rvv/vnsra.ll llvm/test/CodeGen/RISCV/rvv/vnsrl.ll llvm/test/CodeGen/RISCV/rvv/vor.ll llvm/test/CodeGen/RISCV/rvv/vrem.ll llvm/test/CodeGen/RISCV/rvv/vremu.ll llvm/test/CodeGen/RISCV/rvv/vrev8.ll llvm/test/CodeGen/RISCV/rvv/vrgather.ll llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll llvm/test/CodeGen/RISCV/rvv/vrol.ll llvm/test/CodeGen/RISCV/rvv/vror.ll llvm/test/CodeGen/RISCV/rvv/vrsub.ll llvm/test/CodeGen/RISCV/rvv/vsadd.ll llvm/test/CodeGen/RISCV/rvv/vsaddu.ll llvm/test/CodeGen/RISCV/rvv/vsbc.ll llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll llvm/test/CodeGen/RISCV/rvv/vsext.ll llvm/test/CodeGen/RISCV/rvv/vslide1down-constant-vl-rv32.ll llvm/test/CodeGen/RISCV/rvv/vslide1down.ll llvm/test/CodeGen/RISCV/rvv/vslide1up-constant-vl-rv32.ll llvm/test/CodeGen/RISCV/rvv/vslide1up.ll llvm/test/CodeGen/RISCV/rvv/vsll.ll llvm/test/CodeGen/RISCV/rvv/vsm3me.ll llvm/test/CodeGen/RISCV/rvv/vsm4k.ll llvm/test/CodeGen/RISCV/rvv/vsmul.ll llvm/test/CodeGen/RISCV/rvv/vsra.ll llvm/test/CodeGen/RISCV/rvv/vsrl.ll llvm/test/CodeGen/RISCV/rvv/vssub.ll llvm/test/CodeGen/RISCV/rvv/vssubu.ll llvm/test/CodeGen/RISCV/rvv/vsub.ll llvm/test/CodeGen/RISCV/rvv/vwadd.ll llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll llvm/test/CodeGen/RISCV/rvv/vwaddu.ll llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll llvm/test/CodeGen/RISCV/rvv/vwmul.ll llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll llvm/test/CodeGen/RISCV/rvv/vwmulu.ll llvm/test/CodeGen/RISCV/rvv/vwsll.ll llvm/test/CodeGen/RISCV/rvv/vwsub.ll llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll llvm/test/CodeGen/RISCV/rvv/vwsubu.ll llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll llvm/test/CodeGen/RISCV/rvv/vxor.ll llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll llvm/test/CodeGen/RISCV/rvv/vzext.ll llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll llvm/test/CodeGen/RISCV/vararg.ll llvm/test/CodeGen/RISCV/xcvmem.ll
``````````
</details>
The following files introduce new uses of undef:
- llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
[Undef](https://llvm.org/docs/LangRef.html#undefined-values) is now deprecated and should only be used in the rare cases where no replacement is possible. For example, a load of uninitialized memory yields `undef`. You should use `poison` values for placeholders instead.
In tests, avoid using `undef` and having tests that trigger undefined behavior. If you need an operand with some unimportant value, you can add a new argument to the function and use that instead.
For example, this is considered a bad practice:
```llvm
define void @fn() {
...
br i1 undef, ...
}
```
Please use the following instead:
```llvm
define void @fn(i1 %cond) {
...
br i1 %cond, ...
}
```
Please refer to the [Undefined Behavior Manual](https://llvm.org/docs/UndefinedBehavior.html) for more information.
https://github.com/llvm/llvm-project/pull/157396
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