[llvm] fd93dc5 - [SLP]Correctly schedule standalone schedule data, which is part of tree entry
Alexey Bataev via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 7 17:08:54 PDT 2025
Author: Alexey Bataev
Date: 2025-09-07T17:08:37-07:00
New Revision: fd93dc5ac515557f30c9a569c73f6ebfd9b3039b
URL: https://github.com/llvm/llvm-project/commit/fd93dc5ac515557f30c9a569c73f6ebfd9b3039b
DIFF: https://github.com/llvm/llvm-project/commit/fd93dc5ac515557f30c9a569c73f6ebfd9b3039b.diff
LOG: [SLP]Correctly schedule standalone schedule data, which is part of tree entry
If a standalone schedule data relates to a vectorized instruction, still
need to schedule it as a part of pseudo-bundle to correctly handle
dependencies between its child nodes.
Added:
llvm/test/Transforms/SLPVectorizer/X86/parent-node-non-schedulable.ll
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 805e7ea118eb7..4e90c1d5b9e1f 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -5574,7 +5574,23 @@ class BoUpSLP {
if (auto *SD = dyn_cast<ScheduleData>(Data)) {
SD->setScheduled(/*Scheduled=*/true);
LLVM_DEBUG(dbgs() << "SLP: schedule " << *SD << "\n");
- ProcessBundleMember(SD, {});
+ SmallVector<std::unique_ptr<ScheduleBundle>> PseudoBundles;
+ SmallVector<ScheduleBundle *> Bundles;
+ Instruction *In = SD->getInst();
+ if (R.isVectorized(In)) {
+ ArrayRef<TreeEntry *> Entries = R.getTreeEntries(In);
+ for (TreeEntry *TE : Entries) {
+ if (!isa<ExtractValueInst, ExtractElementInst, CallBase>(In) &&
+ In->getNumOperands() != TE->getNumOperands())
+ continue;
+ auto &BundlePtr =
+ PseudoBundles.emplace_back(std::make_unique<ScheduleBundle>());
+ BundlePtr->setTreeEntry(TE);
+ BundlePtr->add(SD);
+ Bundles.push_back(BundlePtr.get());
+ }
+ }
+ ProcessBundleMember(SD, Bundles);
} else {
ScheduleBundle &Bundle = *cast<ScheduleBundle>(Data);
Bundle.setScheduled(/*Scheduled=*/true);
@@ -20853,23 +20869,7 @@ BoUpSLP::BlockScheduling::tryScheduleBundle(ArrayRef<Value *> VL, BoUpSLP *SLP,
for (Value *V : VL) {
if (S.isNonSchedulable(V))
continue;
- // For copybales with parent nodes, which do not need to be scheduled, the
- // parents should not be commutative, otherwise may incorrectly handle deps
- // because of the potential reordering of commutative operations.
- if ((S.isCopyableElement(V) && EI.UserTE && !EI.UserTE->isGather() &&
- EI.UserTE->hasState() && EI.UserTE->doesNotNeedToSchedule() &&
- any_of(EI.UserTE->Scalars,
- [&](Value *V) {
- if (isa<PoisonValue>(V))
- return false;
- auto *I = dyn_cast<Instruction>(V);
- return isCommutative(
- (I && EI.UserTE->isAltShuffle())
- ? EI.UserTE->getMatchingMainOpOrAltOp(I)
- : EI.UserTE->getMainOp(),
- V);
- })) ||
- !extendSchedulingRegion(V, S)) {
+ if (!extendSchedulingRegion(V, S)) {
// If the scheduling region got new instructions at the lower end (or it
// is a new region for the first bundle). This makes it necessary to
// recalculate all dependencies.
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
index fbfc05f40d63a..4c931e46bd8fd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
@@ -4,20 +4,15 @@
define i64 @test(ptr %a) {
; CHECK-LABEL: define i64 @test(
; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 0, 0
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[A]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 0
-; CHECK-NEXT: [[TMP4:%.*]] = add i64 1, [[TMP1]]
-; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 0, 1
-; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 0, 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i64> <i64 poison, i64 0, i64 0, i64 0>, i64 [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i64> zeroinitializer, [[TMP7]]
+; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i64> <i64 0, i64 0, i64 0, i64 1>, [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <6 x i64> [[TMP5]], <6 x i64> <i64 0, i64 0, i64 undef, i64 undef, i64 undef, i64 undef>, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 6, i32 7>
; CHECK-NEXT: br label %[[BB7:.*]]
; CHECK: [[BB7]]:
-; CHECK-NEXT: [[TMP8:%.*]] = phi i64 [ [[TMP3]], [[TMP0:%.*]] ]
-; CHECK-NEXT: [[TMP9:%.*]] = phi i64 [ 0, [[TMP0]] ]
-; CHECK-NEXT: [[TMP10:%.*]] = phi i64 [ [[TMP6]], [[TMP0]] ]
-; CHECK-NEXT: [[TMP11:%.*]] = phi i64 [ [[TMP5]], [[TMP0]] ]
-; CHECK-NEXT: [[TMP12:%.*]] = phi i64 [ 0, [[TMP0]] ]
-; CHECK-NEXT: [[TMP13:%.*]] = phi i64 [ [[TMP4]], [[TMP0]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = phi <6 x i64> [ [[TMP6]], [[TMP0:%.*]] ]
; CHECK-NEXT: ret i64 0
;
%1 = add i64 0, 0
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/parent-node-non-schedulable.ll b/llvm/test/Transforms/SLPVectorizer/X86/parent-node-non-schedulable.ll
new file mode 100644
index 0000000000000..7c8cb02f28c63
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/parent-node-non-schedulable.ll
@@ -0,0 +1,172 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -S -mtriple=i686-unknown-linux-android29 -mattr=+sse2 < %s | FileCheck %s
+
+define void @test(ptr %0, i64 %1, i64 %2, i1 %3, i64 %4, i64 %5) {
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: ptr [[TMP0:%.*]], i64 [[TMP1:%.*]], i64 [[TMP2:%.*]], i1 [[TMP3:%.*]], i64 [[TMP4:%.*]], i64 [[TMP5:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 240
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 128
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i64> poison, i64 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i64> [[TMP9]], <4 x i64> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i64> <i64 1, i64 1, i64 1, i64 poison>, i64 [[TMP2]], i32 3
+; CHECK-NEXT: [[TMP12:%.*]] = add <4 x i64> [[TMP10]], [[TMP11]]
+; CHECK-NEXT: [[TMP13:%.*]] = load <2 x i64>, ptr [[TMP7]], align 4
+; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr null, align 4
+; CHECK-NEXT: [[TMP15:%.*]] = load <2 x i64>, ptr [[TMP8]], align 4
+; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x i64> [[TMP13]], <2 x i64> [[TMP15]], <6 x i32> <i32 0, i32 1, i32 poison, i32 3, i32 2, i32 2>
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <6 x i64> poison, i64 [[TMP14]], i32 0
+; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <6 x i64> [[TMP17]], <6 x i64> poison, <6 x i32> <i32 poison, i32 poison, i32 0, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <6 x i64> [[TMP16]], <6 x i64> [[TMP18]], <6 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5>
+; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <4 x i64> [[TMP10]], <4 x i64> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 0>
+; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <6 x i64> [[TMP20]], <6 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, <6 x i32> <i32 6, i32 7, i32 8, i32 9, i32 10, i32 0>
+; CHECK-NEXT: [[TMP22:%.*]] = add <6 x i64> [[TMP19]], [[TMP21]]
+; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <2 x i64> [[TMP13]], <2 x i64> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i64> [[TMP10]], <4 x i64> [[TMP23]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+; CHECK-NEXT: [[TMP25:%.*]] = sub <4 x i64> zeroinitializer, [[TMP24]]
+; CHECK-NEXT: [[TMP26:%.*]] = sub <6 x i64> zeroinitializer, [[TMP22]]
+; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <6 x i64> [[TMP19]], <6 x i64> poison, <2 x i32> <i32 2, i32 2>
+; CHECK-NEXT: [[TMP28:%.*]] = add <2 x i64> [[TMP27]], splat (i64 1)
+; CHECK-NEXT: [[TMP29:%.*]] = ashr <2 x i64> [[TMP28]], splat (i64 14)
+; CHECK-NEXT: [[TMP30:%.*]] = shufflevector <6 x i64> [[TMP26]], <6 x i64> poison, <14 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP31:%.*]] = shufflevector <4 x i64> [[TMP12]], <4 x i64> poison, <14 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP32:%.*]] = shufflevector <14 x i64> [[TMP30]], <14 x i64> [[TMP31]], <14 x i32> <i32 14, i32 15, i32 16, i32 17, i32 poison, i32 poison, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP33:%.*]] = shufflevector <4 x i64> [[TMP25]], <4 x i64> poison, <14 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP34:%.*]] = shufflevector <14 x i64> [[TMP32]], <14 x i64> [[TMP33]], <14 x i32> <i32 0, i32 1, i32 2, i32 3, i32 14, i32 15, i32 16, i32 17, i32 8, i32 9, i32 10, i32 11, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP35:%.*]] = shufflevector <2 x i64> [[TMP29]], <2 x i64> poison, <14 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP36:%.*]] = shufflevector <14 x i64> [[TMP34]], <14 x i64> [[TMP35]], <14 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 14, i32 15>
+; CHECK-NEXT: br i1 [[TMP3]], label %[[BB52:.*]], label %[[BB37:.*]]
+; CHECK: [[BB37]]:
+; CHECK-NEXT: [[TMP38:%.*]] = add <4 x i64> [[TMP10]], splat (i64 1)
+; CHECK-NEXT: [[TMP39:%.*]] = shufflevector <4 x i64> [[TMP10]], <4 x i64> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP40:%.*]] = add <2 x i64> [[TMP39]], splat (i64 1)
+; CHECK-NEXT: [[TMP41:%.*]] = lshr <2 x i64> [[TMP39]], splat (i64 1)
+; CHECK-NEXT: [[TMP42:%.*]] = add <2 x i64> [[TMP40]], [[TMP41]]
+; CHECK-NEXT: [[TMP43:%.*]] = shufflevector <4 x i64> [[TMP10]], <4 x i64> [[TMP11]], <10 x i32> <i32 0, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP44:%.*]] = insertelement <10 x i64> [[TMP43]], i64 [[TMP4]], i32 6
+; CHECK-NEXT: [[TMP45:%.*]] = insertelement <10 x i64> [[TMP44]], i64 [[TMP5]], i32 7
+; CHECK-NEXT: [[TMP46:%.*]] = shufflevector <4 x i64> [[TMP38]], <4 x i64> poison, <10 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP47:%.*]] = shufflevector <2 x i64> [[TMP42]], <2 x i64> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP48:%.*]] = shufflevector <10 x i64> [[TMP46]], <10 x i64> [[TMP47]], <10 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 4, i32 5, i32 6, i32 7, i32 10, i32 11>
+; CHECK-NEXT: [[TMP49:%.*]] = shufflevector <10 x i64> [[TMP48]], <10 x i64> [[TMP45]], <10 x i32> <i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 8, i32 9>
+; CHECK-NEXT: [[TMP50:%.*]] = shufflevector <10 x i64> [[TMP49]], <10 x i64> poison, <14 x i32> <i32 0, i32 1, i32 0, i32 2, i32 0, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 0, i32 0>
+; CHECK-NEXT: [[TMP51:%.*]] = ashr <14 x i64> [[TMP50]], splat (i64 2)
+; CHECK-NEXT: br label %[[BB52]]
+; CHECK: [[BB52]]:
+; CHECK-NEXT: [[TMP53:%.*]] = phi <14 x i64> [ [[TMP51]], %[[BB37]] ], [ [[TMP36]], [[TMP6:%.*]] ]
+; CHECK-NEXT: [[TMP54:%.*]] = extractelement <14 x i64> [[TMP53]], i32 0
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <14 x i64> [[TMP53]], i32 13
+; CHECK-NEXT: [[TMP56:%.*]] = or i64 [[TMP54]], [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = extractelement <14 x i64> [[TMP53]], i32 4
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <14 x i64> [[TMP53]], i32 12
+; CHECK-NEXT: [[TMP59:%.*]] = or i64 [[TMP57]], [[TMP58]]
+; CHECK-NEXT: [[TMP60:%.*]] = extractelement <14 x i64> [[TMP53]], i32 1
+; CHECK-NEXT: [[TMP61:%.*]] = extractelement <14 x i64> [[TMP53]], i32 2
+; CHECK-NEXT: [[TMP62:%.*]] = or i64 [[TMP60]], [[TMP61]]
+; CHECK-NEXT: [[TMP63:%.*]] = or i64 [[TMP59]], [[TMP56]]
+; CHECK-NEXT: [[TMP64:%.*]] = extractelement <14 x i64> [[TMP53]], i32 5
+; CHECK-NEXT: [[TMP65:%.*]] = extractelement <14 x i64> [[TMP53]], i32 8
+; CHECK-NEXT: [[TMP66:%.*]] = or i64 [[TMP64]], [[TMP65]]
+; CHECK-NEXT: [[TMP67:%.*]] = extractelement <14 x i64> [[TMP53]], i32 3
+; CHECK-NEXT: [[TMP68:%.*]] = or i64 [[TMP67]], [[TMP62]]
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <14 x i64> [[TMP53]], i32 9
+; CHECK-NEXT: [[TMP70:%.*]] = or i64 [[TMP69]], [[TMP66]]
+; CHECK-NEXT: [[TMP71:%.*]] = extractelement <14 x i64> [[TMP53]], i32 6
+; CHECK-NEXT: [[TMP72:%.*]] = or i64 [[TMP71]], [[TMP70]]
+; CHECK-NEXT: [[TMP73:%.*]] = or i64 [[TMP63]], [[TMP72]]
+; CHECK-NEXT: [[TMP74:%.*]] = extractelement <14 x i64> [[TMP53]], i32 10
+; CHECK-NEXT: [[TMP75:%.*]] = or i64 [[TMP74]], [[TMP73]]
+; CHECK-NEXT: store i64 [[TMP68]], ptr [[TMP0]], align 4
+; CHECK-NEXT: [[TMP76:%.*]] = extractelement <14 x i64> [[TMP53]], i32 11
+; CHECK-NEXT: store i64 [[TMP76]], ptr null, align 4
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <14 x i64> [[TMP53]], i32 7
+; CHECK-NEXT: store i64 [[TMP77]], ptr [[TMP0]], align 4
+; CHECK-NEXT: store i64 [[TMP75]], ptr null, align 4
+; CHECK-NEXT: ret void
+;
+ %7 = getelementptr i8, ptr %0, i32 248
+ %8 = load i64, ptr %7, align 4
+ %9 = getelementptr i8, ptr %0, i32 240
+ %10 = load i64, ptr %9, align 4
+ %11 = load i64, ptr null, align 4
+ %12 = add i64 %1, 1
+ %13 = add i64 %1, 1
+ %14 = add i64 %1, %2
+ %15 = getelementptr i8, ptr %0, i32 136
+ %16 = load i64, ptr %15, align 4
+ %17 = getelementptr i8, ptr %0, i32 128
+ %18 = load i64, ptr %17, align 4
+ %19 = add i64 %18, %1
+ %20 = sub i64 0, %18
+ %21 = sub i64 0, %16
+ %22 = sub i64 0, %11
+ %23 = add i64 %1, 1
+ %24 = sub i64 0, %1
+ %25 = sub i64 0, %1
+ %26 = sub i64 0, %10
+ %27 = sub i64 0, %8
+ %28 = sub i64 0, %19
+ %29 = add i64 %11, 1
+ %30 = ashr i64 %29, 14
+ %31 = add i64 %11, 1
+ %32 = ashr i64 %31, 14
+ br i1 %3, label %58, label %33
+
+33:
+ %34 = ashr i64 %2, 2
+ %35 = ashr i64 %1, 2
+ %36 = add i64 %1, 1
+ %37 = ashr i64 %36, 2
+ %38 = add i64 %1, 1
+ %39 = lshr i64 %1, 1
+ %40 = add i64 %38, %39
+ %41 = ashr i64 %40, 2
+ %42 = add i64 %1, 1
+ %43 = lshr i64 %1, 1
+ %44 = add i64 %42, %43
+ %45 = ashr i64 %44, 2
+ %46 = ashr i64 %5, 2
+ %47 = ashr i64 %4, 2
+ %48 = ashr i64 %1, 2
+ %49 = ashr i64 %1, 2
+ %50 = ashr i64 %1, 2
+ %51 = ashr i64 %1, 2
+ %52 = add i64 %1, 1
+ %53 = ashr i64 %52, 2
+ %54 = add i64 %1, 1
+ %55 = ashr i64 %54, 2
+ %56 = add i64 %1, 1
+ %57 = ashr i64 %56, 2
+ br label %58
+
+58:
+ %59 = phi i64 [ %51, %33 ], [ %24, %6 ]
+ %60 = phi i64 [ %50, %33 ], [ %32, %6 ]
+ %61 = phi i64 [ %53, %33 ], [ %25, %6 ]
+ %62 = phi i64 [ %55, %33 ], [ %26, %6 ]
+ %63 = phi i64 [ %57, %33 ], [ %27, %6 ]
+ %64 = phi i64 [ %49, %33 ], [ %30, %6 ]
+ %65 = phi i64 [ %48, %33 ], [ %23, %6 ]
+ %66 = phi i64 [ %47, %33 ], [ %22, %6 ]
+ %67 = phi i64 [ %46, %33 ], [ %21, %6 ]
+ %68 = phi i64 [ %45, %33 ], [ %20, %6 ]
+ %69 = phi i64 [ %41, %33 ], [ %28, %6 ]
+ %70 = phi i64 [ %34, %33 ], [ %12, %6 ]
+ %71 = phi i64 [ %35, %33 ], [ %13, %6 ]
+ %72 = phi i64 [ %37, %33 ], [ %14, %6 ]
+ %73 = or i64 %65, %64
+ %74 = or i64 %59, %60
+ %75 = or i64 %70, %71
+ %76 = or i64 %74, %73
+ %77 = or i64 %61, %66
+ %78 = or i64 %72, %75
+ %79 = or i64 %67, %77
+ %80 = or i64 %62, %79
+ %81 = or i64 %76, %80
+ %82 = or i64 %68, %81
+ store i64 %78, ptr %0, align 4
+ store i64 %69, ptr null, align 4
+ store i64 %63, ptr %0, align 4
+ store i64 %82, ptr null, align 4
+ ret void
+}
+
More information about the llvm-commits
mailing list