[llvm] [BPF] Remove skb operand of LD_ABS/LD_IND instructions (PR #157344)

[Sergei Barannikov via llvm-commits]

https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/157344

The instructions already have R6 register in the Uses list, there is no need for an additional explicit `GPR:$skb` operand.

This simplifies intrinsic selection and makes the instructions decodable without post-decoding pass inserting R6 operand.

>From 86e1fc69544e8d8a0221c27030546e2486a71e03 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sun, 7 Sep 2025 17:59:34 +0300
Subject: [PATCH] [BPF] Remove skb operand of LD_ABS/LD_IND instructions

The instructions already have R6 register in the Uses list, there is no
need for an additional explicit `GPR:$skb` operand.

This simplifies intrinsic selection and makes the instructions decodable
without post-decoding pass inserting R6 operand.
---
 llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp       | 21 -------------------
 llvm/lib/Target/BPF/BPFInstrInfo.td           | 10 ++++-----
 llvm/lib/Target/BPF/CMakeLists.txt            |  3 +--
 .../BPF/Disassembler/BPFDisassembler.cpp      | 12 -----------
 4 files changed, 5 insertions(+), 41 deletions(-)

diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
index 352017e9b9292..dadba52de4627 100644
--- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
@@ -193,27 +193,6 @@ void BPFDAGToDAGISel::Select(SDNode *Node) {
   switch (Opcode) {
   default:
     break;
-  case ISD::INTRINSIC_W_CHAIN: {
-    unsigned IntNo = Node->getConstantOperandVal(1);
-    switch (IntNo) {
-    case Intrinsic::bpf_load_byte:
-    case Intrinsic::bpf_load_half:
-    case Intrinsic::bpf_load_word: {
-      SDLoc DL(Node);
-      SDValue Chain = Node->getOperand(0);
-      SDValue N1 = Node->getOperand(1);
-      SDValue Skb = Node->getOperand(2);
-      SDValue N3 = Node->getOperand(3);
-
-      SDValue R6Reg = CurDAG->getRegister(BPF::R6, MVT::i64);
-      Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());
-      Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);
-      break;
-    }
-    }
-    break;
-  }
-
   case ISD::FrameIndex: {
     int FI = cast<FrameIndexSDNode>(Node)->getIndex();
     EVT VT = Node->getValueType(0);
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td
index b21f1a0eee3b0..de7dae2c8ca68 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.td
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.td
@@ -1189,10 +1189,9 @@ let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
     hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
 class LOAD_ABS<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
     : TYPE_LD_ST<BPF_ABS.Value, SizeOp.Value,
-                 (outs),
-                 (ins GPR:$skb, i64imm:$imm),
+                 (outs), (ins i64imm:$imm),
                  "r0 = *("#OpcodeStr#" *)skb[$imm]",
-                 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
+                 [(set R0, (OpNode R6, i64immSExt32:$imm))]> {
   bits<32> imm;
 
   let Inst{31-0} = imm;
@@ -1201,10 +1200,9 @@ class LOAD_ABS<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
 
 class LOAD_IND<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
     : TYPE_LD_ST<BPF_IND.Value, SizeOp.Value,
-                 (outs),
-                 (ins GPR:$skb, GPR:$val),
+                 (outs), (ins GPR:$val),
                  "r0 = *("#OpcodeStr#" *)skb[$val]",
-                 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
+                 [(set R0, (OpNode R6, GPR:$val))]> {
   bits<4> val;
 
   let Inst{55-52} = val;
diff --git a/llvm/lib/Target/BPF/CMakeLists.txt b/llvm/lib/Target/BPF/CMakeLists.txt
index 678cb42c35f13..eade4cacb7100 100644
--- a/llvm/lib/Target/BPF/CMakeLists.txt
+++ b/llvm/lib/Target/BPF/CMakeLists.txt
@@ -6,8 +6,7 @@ tablegen(LLVM BPFGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM BPFGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM BPFGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM BPFGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM BPFGenDisassemblerTables.inc -gen-disassembler
-              -ignore-non-decodable-operands)
+tablegen(LLVM BPFGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM BPFGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM BPFGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM BPFGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
index b5bb1c08c5644..230cf3b0ddbe4 100644
--- a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
+++ b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
@@ -205,18 +205,6 @@ DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
     Op.setImm(Make_64(Hi, Op.getImm()));
     break;
   }
-  case BPF::LD_ABS_B:
-  case BPF::LD_ABS_H:
-  case BPF::LD_ABS_W:
-  case BPF::LD_IND_B:
-  case BPF::LD_IND_H:
-  case BPF::LD_IND_W: {
-    auto Op = Instr.getOperand(0);
-    Instr.clear();
-    Instr.addOperand(MCOperand::createReg(BPF::R6));
-    Instr.addOperand(Op);
-    break;
-  }
   }
 
   return Result;