[llvm] CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (PR #157337)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 7 06:26:39 PDT 2025
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/157337
>From 9ae15f2dab49670cbde4701f6ff5ef531f09b2a0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sun, 7 Sep 2025 19:06:13 +0900
Subject: [PATCH 1/4] CodeGen: Pass MCSubtargetInfo to TargetGenInstrInfo
constructors
This will make it possible for tablegen to make subtarget
dependent decisions without adding new arguments to every
target.
---
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 4 ++--
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 ++--
llvm/lib/Target/ARC/ARCInstrInfo.cpp | 2 +-
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 6 +++---
llvm/lib/Target/AVR/AVRInstrInfo.cpp | 4 ++--
llvm/lib/Target/AVR/AVRInstrInfo.h | 2 +-
llvm/lib/Target/BPF/BPFInstrInfo.cpp | 5 +++--
llvm/lib/Target/BPF/BPFInstrInfo.h | 3 ++-
llvm/lib/Target/BPF/BPFSubtarget.cpp | 2 +-
llvm/lib/Target/CSKY/CSKYInstrInfo.cpp | 5 +++--
llvm/lib/Target/CSKY/CSKYInstrInfo.h | 2 +-
llvm/lib/Target/DirectX/DirectXInstrInfo.cpp | 4 ++++
llvm/lib/Target/DirectX/DirectXInstrInfo.h | 4 +++-
llvm/lib/Target/DirectX/DirectXSubtarget.cpp | 3 ++-
llvm/lib/Target/DirectX/DirectXSubtarget.h | 2 +-
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 7 ++++---
llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 2 +-
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 5 +++--
llvm/lib/Target/Lanai/LanaiInstrInfo.h | 4 +++-
llvm/lib/Target/Lanai/LanaiSubtarget.cpp | 4 ++--
llvm/lib/Target/Lanai/LanaiSubtarget.h | 2 +-
llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp | 4 ++--
llvm/lib/Target/LoongArch/LoongArchInstrInfo.h | 2 +-
llvm/lib/Target/M68k/M68kInstrInfo.cpp | 2 +-
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp | 7 ++++---
llvm/lib/Target/MSP430/MSP430InstrInfo.h | 2 +-
llvm/lib/Target/Mips/MipsInstrInfo.cpp | 2 +-
llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp | 6 ++++--
llvm/lib/Target/NVPTX/NVPTXInstrInfo.h | 3 ++-
llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp | 2 +-
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 2 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp | 4 +++-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.h | 3 ++-
llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp | 6 +++---
llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 4 ++--
llvm/lib/Target/Sparc/SparcInstrInfo.h | 2 +-
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 4 ++--
llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 4 ++--
llvm/lib/Target/VE/VEInstrInfo.cpp | 4 ++--
llvm/lib/Target/VE/VEInstrInfo.h | 2 +-
.../Target/WebAssembly/WebAssemblyInstrInfo.cpp | 2 +-
llvm/lib/Target/X86/X86InstrInfo.cpp | 5 +++--
llvm/lib/Target/X86/X86InstrInfo.h | 4 ++--
llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 8 ++++----
llvm/lib/Target/XCore/XCoreInstrInfo.h | 3 ++-
llvm/lib/Target/XCore/XCoreSubtarget.cpp | 4 ++--
llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 2 +-
.../Target/DirectX/RegisterCostTests.cpp | 15 +++++++++------
llvm/utils/TableGen/InstrInfoEmitter.cpp | 7 +++++--
52 files changed, 114 insertions(+), 85 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 3ce7829207cb6..8843ce3b94780 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -91,8 +91,8 @@ static cl::opt<unsigned> GatherOptSearchLimit(
"machine-combiner gather pattern optimization"));
AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
- : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP,
- AArch64::CATCHRET),
+ : AArch64GenInstrInfo(STI, AArch64::ADJCALLSTACKDOWN,
+ AArch64::ADJCALLSTACKUP, AArch64::CATCHRET),
RI(STI.getTargetTriple(), STI.getHwMode()), Subtarget(STI) {}
/// GetInstSize - Return the number of bytes of code the specified
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 8d27153fcfcde..3e256cce97afb 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -29,7 +29,7 @@ using namespace llvm;
#include "R600GenInstrInfo.inc"
R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
- : R600GenInstrInfo(-1, -1), RI(), ST(ST) {}
+ : R600GenInstrInfo(ST, -1, -1), RI(), ST(ST) {}
bool R600InstrInfo::isVector(const MachineInstr &MI) const {
return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 3745060f816e0..d500858841a41 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -62,8 +62,8 @@ static cl::opt<bool> Fix16BitCopies(
cl::ReallyHidden);
SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
- : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
- RI(ST), ST(ST) {
+ : AMDGPUGenInstrInfo(ST, AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
+ RI(ST), ST(ST) {
SchedModel.init(&ST);
}
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 8a89bdb546f3b..05bcb3596ac48 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -44,7 +44,7 @@ enum TSFlagsConstants {
void ARCInstrInfo::anchor() {}
ARCInstrInfo::ARCInstrInfo(const ARCSubtarget &ST)
- : ARCGenInstrInfo(ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI(ST) {}
+ : ARCGenInstrInfo(ST, ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI(ST) {}
static bool isZeroImm(const MachineOperand &Op) {
return Op.isImm() && Op.getImm() == 0;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index d7398f6a948ce..5c35b3327c16d 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -107,9 +107,9 @@ static const ARM_MLxEntry ARM_MLxTable[] = {
{ ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
};
-ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
- : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
- Subtarget(STI) {
+ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
+ : ARMGenInstrInfo(STI, ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+ Subtarget(STI) {
for (unsigned i = 0, e = std::size(ARM_MLxTable); i != e; ++i) {
if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
llvm_unreachable("Duplicated entries?");
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index 601068bf17933..ce9908597dcac 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -29,8 +29,8 @@
namespace llvm {
-AVRInstrInfo::AVRInstrInfo(AVRSubtarget &STI)
- : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI(),
+AVRInstrInfo::AVRInstrInfo(const AVRSubtarget &STI)
+ : AVRGenInstrInfo(STI, AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI(),
STI(STI) {}
void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.h b/llvm/lib/Target/AVR/AVRInstrInfo.h
index 1c92f173d254b..759aea2010962 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.h
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.h
@@ -65,7 +65,7 @@ enum TOF {
/// Utilities related to the AVR instruction set.
class AVRInstrInfo : public AVRGenInstrInfo {
public:
- explicit AVRInstrInfo(AVRSubtarget &STI);
+ explicit AVRInstrInfo(const AVRSubtarget &STI);
const AVRRegisterInfo &getRegisterInfo() const { return RI; }
const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
index 70bc163615f61..fb4efcfe86142 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
@@ -12,6 +12,7 @@
#include "BPFInstrInfo.h"
#include "BPF.h"
+#include "BPFSubtarget.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -25,8 +26,8 @@
using namespace llvm;
-BPFInstrInfo::BPFInstrInfo()
- : BPFGenInstrInfo(BPF::ADJCALLSTACKDOWN, BPF::ADJCALLSTACKUP) {}
+BPFInstrInfo::BPFInstrInfo(const BPFSubtarget &STI)
+ : BPFGenInstrInfo(STI, BPF::ADJCALLSTACKDOWN, BPF::ADJCALLSTACKUP) {}
void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.h b/llvm/lib/Target/BPF/BPFInstrInfo.h
index d8bbad44e314e..94e6737707376 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.h
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.h
@@ -20,12 +20,13 @@
#include "BPFGenInstrInfo.inc"
namespace llvm {
+class BPFSubtarget;
class BPFInstrInfo : public BPFGenInstrInfo {
const BPFRegisterInfo RI;
public:
- BPFInstrInfo();
+ BPFInstrInfo(const BPFSubtarget &STI);
const BPFRegisterInfo &getRegisterInfo() const { return RI; }
diff --git a/llvm/lib/Target/BPF/BPFSubtarget.cpp b/llvm/lib/Target/BPF/BPFSubtarget.cpp
index 4167547680b12..a7ecc39fad7b9 100644
--- a/llvm/lib/Target/BPF/BPFSubtarget.cpp
+++ b/llvm/lib/Target/BPF/BPFSubtarget.cpp
@@ -103,7 +103,7 @@ void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
: BPFGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
- FrameLowering(initializeSubtargetDependencies(CPU, FS)),
+ InstrInfo(initializeSubtargetDependencies(CPU, FS)), FrameLowering(*this),
TLInfo(TM, *this) {
IsLittleEndian = TT.isLittleEndian();
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
index ccb3f16394d4c..619a797be6dc7 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
@@ -24,8 +24,9 @@ using namespace llvm;
#define GET_INSTRINFO_CTOR_DTOR
#include "CSKYGenInstrInfo.inc"
-CSKYInstrInfo::CSKYInstrInfo(CSKYSubtarget &STI)
- : CSKYGenInstrInfo(CSKY::ADJCALLSTACKDOWN, CSKY::ADJCALLSTACKUP), STI(STI) {
+CSKYInstrInfo::CSKYInstrInfo(const CSKYSubtarget &STI)
+ : CSKYGenInstrInfo(STI, CSKY::ADJCALLSTACKDOWN, CSKY::ADJCALLSTACKUP),
+ STI(STI) {
v2sf = STI.hasFPUv2SingleFloat();
v2df = STI.hasFPUv2DoubleFloat();
v3sf = STI.hasFPUv3SingleFloat();
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.h b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
index 98f583e8b4051..6451c0af14fc0 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.h
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
@@ -33,7 +33,7 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {
const CSKYSubtarget &STI;
public:
- explicit CSKYInstrInfo(CSKYSubtarget &STI);
+ explicit CSKYInstrInfo(const CSKYSubtarget &STI);
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
diff --git a/llvm/lib/Target/DirectX/DirectXInstrInfo.cpp b/llvm/lib/Target/DirectX/DirectXInstrInfo.cpp
index 07b68648f16c2..bb2efa43d818c 100644
--- a/llvm/lib/Target/DirectX/DirectXInstrInfo.cpp
+++ b/llvm/lib/Target/DirectX/DirectXInstrInfo.cpp
@@ -11,10 +11,14 @@
//===----------------------------------------------------------------------===//
#include "DirectXInstrInfo.h"
+#include "DirectXSubtarget.h"
#define GET_INSTRINFO_CTOR_DTOR
#include "DirectXGenInstrInfo.inc"
using namespace llvm;
+DirectXInstrInfo::DirectXInstrInfo(const DirectXSubtarget &STI)
+ : DirectXGenInstrInfo(STI) {}
+
DirectXInstrInfo::~DirectXInstrInfo() {}
diff --git a/llvm/lib/Target/DirectX/DirectXInstrInfo.h b/llvm/lib/Target/DirectX/DirectXInstrInfo.h
index e2c7036fc74a7..57ede28030b2e 100644
--- a/llvm/lib/Target/DirectX/DirectXInstrInfo.h
+++ b/llvm/lib/Target/DirectX/DirectXInstrInfo.h
@@ -20,9 +20,11 @@
#include "DirectXGenInstrInfo.inc"
namespace llvm {
+class DirectXSubtarget;
+
struct DirectXInstrInfo : public DirectXGenInstrInfo {
const DirectXRegisterInfo RI;
- explicit DirectXInstrInfo() : DirectXGenInstrInfo() {}
+ explicit DirectXInstrInfo(const DirectXSubtarget &STI);
const DirectXRegisterInfo &getRegisterInfo() const { return RI; }
~DirectXInstrInfo() override;
};
diff --git a/llvm/lib/Target/DirectX/DirectXSubtarget.cpp b/llvm/lib/Target/DirectX/DirectXSubtarget.cpp
index 526b7d29fb13e..f8519177cc2db 100644
--- a/llvm/lib/Target/DirectX/DirectXSubtarget.cpp
+++ b/llvm/lib/Target/DirectX/DirectXSubtarget.cpp
@@ -24,6 +24,7 @@ using namespace llvm;
DirectXSubtarget::DirectXSubtarget(const Triple &TT, StringRef CPU,
StringRef FS, const DirectXTargetMachine &TM)
- : DirectXGenSubtargetInfo(TT, CPU, CPU, FS), FL(*this), TL(TM, *this) {}
+ : DirectXGenSubtargetInfo(TT, CPU, CPU, FS), InstrInfo(*this), FL(*this),
+ TL(TM, *this) {}
void DirectXSubtarget::anchor() {}
diff --git a/llvm/lib/Target/DirectX/DirectXSubtarget.h b/llvm/lib/Target/DirectX/DirectXSubtarget.h
index b2374caaf3cdf..f3d71c4c4e3bd 100644
--- a/llvm/lib/Target/DirectX/DirectXSubtarget.h
+++ b/llvm/lib/Target/DirectX/DirectXSubtarget.h
@@ -28,9 +28,9 @@ namespace llvm {
class DirectXTargetMachine;
class DirectXSubtarget : public DirectXGenSubtargetInfo {
+ DirectXInstrInfo InstrInfo;
DirectXFrameLowering FL;
DirectXTargetLowering TL;
- DirectXInstrInfo InstrInfo;
virtual void anchor(); // virtual anchor method
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 64bc5ca134c86..45d194e944fb9 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -117,9 +117,10 @@ const int Hexagon_ADDI_OFFSET_MIN = -32768;
// Pin the vtable to this file.
void HexagonInstrInfo::anchor() {}
-HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
- : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
- Subtarget(ST) {}
+HexagonInstrInfo::HexagonInstrInfo(const HexagonSubtarget &ST)
+ : HexagonGenInstrInfo(ST, Hexagon::ADJCALLSTACKDOWN,
+ Hexagon::ADJCALLSTACKUP),
+ Subtarget(ST) {}
namespace llvm {
namespace HexagonFUnits {
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index 086cb1fdd8ac4..c17e5277ae2e7 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -45,7 +45,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
virtual void anchor();
public:
- explicit HexagonInstrInfo(HexagonSubtarget &ST);
+ explicit HexagonInstrInfo(const HexagonSubtarget &ST);
/// TargetInstrInfo overrides.
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index 4ca97da16cdeb..02ed1001cd0d3 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -13,6 +13,7 @@
#include "LanaiInstrInfo.h"
#include "LanaiAluCode.h"
#include "LanaiCondCode.h"
+#include "LanaiSubtarget.h"
#include "MCTargetDesc/LanaiBaseInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
@@ -25,8 +26,8 @@ using namespace llvm;
#define GET_INSTRINFO_CTOR_DTOR
#include "LanaiGenInstrInfo.inc"
-LanaiInstrInfo::LanaiInstrInfo()
- : LanaiGenInstrInfo(Lanai::ADJCALLSTACKDOWN, Lanai::ADJCALLSTACKUP),
+LanaiInstrInfo::LanaiInstrInfo(const LanaiSubtarget &STI)
+ : LanaiGenInstrInfo(STI, Lanai::ADJCALLSTACKDOWN, Lanai::ADJCALLSTACKUP),
RegisterInfo() {}
void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
index 07b1e87dc8b2c..d98276243dc31 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
@@ -22,11 +22,13 @@
namespace llvm {
+class LanaiSubtarget;
+
class LanaiInstrInfo : public LanaiGenInstrInfo {
const LanaiRegisterInfo RegisterInfo;
public:
- LanaiInstrInfo();
+ LanaiInstrInfo(const LanaiSubtarget &STI);
// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
// such, whenever a client has an instance of instruction info, it should
diff --git a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp
index 24aa8553279f1..f99e88373edf0 100644
--- a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp
+++ b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp
@@ -40,5 +40,5 @@ LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu,
CodeModel::Model /*CodeModel*/,
CodeGenOptLevel /*OptLevel*/)
: LanaiGenSubtargetInfo(TargetTriple, Cpu, /*TuneCPU*/ Cpu, FeatureString),
- FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)),
- TLInfo(TM, *this) {}
+ InstrInfo(initializeSubtargetDependencies(Cpu, FeatureString)),
+ FrameLowering(*this), TLInfo(TM, *this) {}
diff --git a/llvm/lib/Target/Lanai/LanaiSubtarget.h b/llvm/lib/Target/Lanai/LanaiSubtarget.h
index 0a229063ab7b2..233c89e881d58 100644
--- a/llvm/lib/Target/Lanai/LanaiSubtarget.h
+++ b/llvm/lib/Target/Lanai/LanaiSubtarget.h
@@ -64,8 +64,8 @@ class LanaiSubtarget : public LanaiGenSubtargetInfo {
}
private:
- LanaiFrameLowering FrameLowering;
LanaiInstrInfo InstrInfo;
+ LanaiFrameLowering FrameLowering;
LanaiTargetLowering TLInfo;
LanaiSelectionDAGInfo TSInfo;
};
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
index 26d36f1c5058f..c89212dae72d9 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
@@ -25,8 +25,8 @@ using namespace llvm;
#define GET_INSTRINFO_CTOR_DTOR
#include "LoongArchGenInstrInfo.inc"
-LoongArchInstrInfo::LoongArchInstrInfo(LoongArchSubtarget &STI)
- : LoongArchGenInstrInfo(LoongArch::ADJCALLSTACKDOWN,
+LoongArchInstrInfo::LoongArchInstrInfo(const LoongArchSubtarget &STI)
+ : LoongArchGenInstrInfo(STI, LoongArch::ADJCALLSTACKDOWN,
LoongArch::ADJCALLSTACKUP),
STI(STI) {}
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
index 63b7112b8b40a..f25958a32bec4 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
@@ -25,7 +25,7 @@ class LoongArchSubtarget;
class LoongArchInstrInfo : public LoongArchGenInstrInfo {
public:
- explicit LoongArchInstrInfo(LoongArchSubtarget &STI);
+ explicit LoongArchInstrInfo(const LoongArchSubtarget &STI);
MCInst getNop() const override;
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 21e9319aaf0b3..c6be190bd1245 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -43,7 +43,7 @@ using namespace llvm;
void M68kInstrInfo::anchor() {}
M68kInstrInfo::M68kInstrInfo(const M68kSubtarget &STI)
- : M68kGenInstrInfo(M68k::ADJCALLSTACKDOWN, M68k::ADJCALLSTACKUP, 0,
+ : M68kGenInstrInfo(STI, M68k::ADJCALLSTACKDOWN, M68k::ADJCALLSTACKUP, 0,
M68k::RET),
Subtarget(STI), RI(STI) {}
diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
index 8bc6387e6a7ee..65b4820752c94 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
+++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -12,6 +12,7 @@
#include "MSP430InstrInfo.h"
#include "MSP430.h"
+#include "MSP430Subtarget.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/ErrorHandling.h"
@@ -24,9 +25,9 @@ using namespace llvm;
// Pin the vtable to this file.
void MSP430InstrInfo::anchor() {}
-MSP430InstrInfo::MSP430InstrInfo(MSP430Subtarget &STI)
- : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
- RI() {}
+MSP430InstrInfo::MSP430InstrInfo(const MSP430Subtarget &STI)
+ : MSP430GenInstrInfo(STI, MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
+ RI() {}
void MSP430InstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/llvm/lib/Target/MSP430/MSP430InstrInfo.h
index 58be64336f26e..316c136890bf8 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrInfo.h
+++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.h
@@ -27,7 +27,7 @@ class MSP430InstrInfo : public MSP430GenInstrInfo {
const MSP430RegisterInfo RI;
virtual void anchor();
public:
- explicit MSP430InstrInfo(MSP430Subtarget &STI);
+ explicit MSP430InstrInfo(const MSP430Subtarget &STI);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index 8a59532ba5786..bffdffa4af6a0 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -40,7 +40,7 @@ using namespace llvm;
void MipsInstrInfo::anchor() {}
MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
- : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
+ : MipsGenInstrInfo(STI, Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
Subtarget(STI), UncondBrOpc(UncondBr) {}
const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
index 34fe467c94563..6840c7ae8faf4 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
@@ -12,6 +12,7 @@
#include "NVPTXInstrInfo.h"
#include "NVPTX.h"
+#include "NVPTXSubtarget.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -24,7 +25,8 @@ using namespace llvm;
// Pin the vtable to this file.
void NVPTXInstrInfo::anchor() {}
-NVPTXInstrInfo::NVPTXInstrInfo() : RegInfo() {}
+NVPTXInstrInfo::NVPTXInstrInfo(const NVPTXSubtarget &STI)
+ : NVPTXGenInstrInfo(STI), RegInfo() {}
void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
@@ -190,4 +192,4 @@ unsigned NVPTXInstrInfo::insertBranch(MachineBasicBlock &MBB,
BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB);
BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
return 2;
-}
\ No newline at end of file
+}
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
index 4e9dc9d3b4686..23889531431ea 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
@@ -21,12 +21,13 @@
#include "NVPTXGenInstrInfo.inc"
namespace llvm {
+class NVPTXSubtarget;
class NVPTXInstrInfo : public NVPTXGenInstrInfo {
const NVPTXRegisterInfo RegInfo;
virtual void anchor();
public:
- explicit NVPTXInstrInfo();
+ explicit NVPTXInstrInfo(const NVPTXSubtarget &STI);
const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
index a84ceaba991c7..c5489670bd249 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
@@ -62,7 +62,7 @@ NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const NVPTXTargetMachine &TM)
: NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
FullSmVersion(200), SmVersion(getSmVersion()),
- TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {
+ InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {
TSInfo = std::make_unique<NVPTXSelectionDAGInfo>();
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index ffd63947e584d..db066bc4b7bdd 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -89,7 +89,7 @@ static cl::opt<bool> EnableFMARegPressureReduction(
void PPCInstrInfo::anchor() {}
PPCInstrInfo::PPCInstrInfo(const PPCSubtarget &STI)
- : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
+ : PPCGenInstrInfo(STI, PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
/* CatchRetOpcode */ -1,
STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
Subtarget(STI), RI(STI.getTargetMachine()) {}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index ee6d6cdb00096..f2e6e8959a726 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -80,8 +80,8 @@ namespace llvm::RISCV {
} // end namespace llvm::RISCV
-RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
- : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
+RISCVInstrInfo::RISCVInstrInfo(const RISCVSubtarget &STI)
+ : RISCVGenInstrInfo(STI, RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
STI(STI) {}
#define GET_INSTRINFO_HELPERS
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 785c8352d4a5e..57ec431749ebe 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -62,7 +62,7 @@ enum RISCVMachineCombinerPattern : unsigned {
class RISCVInstrInfo : public RISCVGenInstrInfo {
public:
- explicit RISCVInstrInfo(RISCVSubtarget &STI);
+ explicit RISCVInstrInfo(const RISCVSubtarget &STI);
MCInst getNop() const override;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
index f658b67a4c2a5..45e88fc94144e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
@@ -12,6 +12,7 @@
#include "SPIRVInstrInfo.h"
#include "SPIRV.h"
+#include "SPIRVSubtarget.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -22,7 +23,8 @@
using namespace llvm;
-SPIRVInstrInfo::SPIRVInstrInfo() : SPIRVGenInstrInfo() {}
+SPIRVInstrInfo::SPIRVInstrInfo(const SPIRVSubtarget &STI)
+ : SPIRVGenInstrInfo(STI) {}
bool SPIRVInstrInfo::isConstantInstr(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
index d58dddcd8da2b..0ae924f23d783 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
@@ -20,12 +20,13 @@
#include "SPIRVGenInstrInfo.inc"
namespace llvm {
+class SPIRVSubtarget;
class SPIRVInstrInfo : public SPIRVGenInstrInfo {
const SPIRVRegisterInfo RI;
public:
- SPIRVInstrInfo();
+ SPIRVInstrInfo(const SPIRVSubtarget &STI);
const SPIRVRegisterInfo &getRegisterInfo() const { return RI; }
bool isHeaderInstr(const MachineInstr &MI) const;
diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
index 690493fb426bc..5b746a1389afd 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
@@ -53,9 +53,9 @@ SPIRVSubtarget::SPIRVSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
const SPIRVTargetMachine &TM)
: SPIRVGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS),
- PointerSize(TM.getPointerSizeInBits(/* AS= */ 0)), InstrInfo(),
- FrameLowering(initSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
- TargetTriple(TT) {
+ PointerSize(TM.getPointerSizeInBits(/* AS= */ 0)),
+ InstrInfo(initSubtargetDependencies(CPU, FS)), FrameLowering(*this),
+ TLInfo(TM, *this), TargetTriple(TT) {
switch (TT.getSubArch()) {
case Triple::SPIRVSubArch_v10:
SPIRVVersion = VersionTuple(1, 0);
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index a7fbbd4044c11..86f52fefbaedd 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -37,8 +37,8 @@ static cl::opt<unsigned>
// Pin the vtable to this file.
void SparcInstrInfo::anchor() {}
-SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
- : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
+SparcInstrInfo::SparcInstrInfo(const SparcSubtarget &ST)
+ : SparcGenInstrInfo(ST, SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
Subtarget(ST) {}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h
index 1feb12ba2fdae..01d0204734943 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.h
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h
@@ -40,7 +40,7 @@ class SparcInstrInfo : public SparcGenInstrInfo {
const SparcSubtarget& Subtarget;
virtual void anchor();
public:
- explicit SparcInstrInfo(SparcSubtarget &ST);
+ explicit SparcInstrInfo(const SparcSubtarget &ST);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 783f86aecce4a..2e21f27c9032f 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -59,8 +59,8 @@ static uint64_t allOnes(unsigned int Count) {
// Pin the vtable to this file.
void SystemZInstrInfo::anchor() {}
-SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
- : SystemZGenInstrInfo(-1, -1),
+SystemZInstrInfo::SystemZInstrInfo(const SystemZSubtarget &sti)
+ : SystemZGenInstrInfo(sti, -1, -1),
RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister(),
sti.getHwMode()),
STI(sti) {}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index 8b82af61e669a..7b9ad7b87a14f 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -184,7 +184,7 @@ MachineBasicBlock *splitBlockBefore(MachineBasicBlock::iterator MI,
class SystemZInstrInfo : public SystemZGenInstrInfo {
const SystemZRegisterInfo RI;
- SystemZSubtarget &STI;
+ const SystemZSubtarget &STI;
void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
@@ -225,7 +225,7 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
unsigned CommuteOpIdx2) const override;
public:
- explicit SystemZInstrInfo(SystemZSubtarget &STI);
+ explicit SystemZInstrInfo(const SystemZSubtarget &STI);
// Override TargetInstrInfo.
Register isLoadFromStackSlot(const MachineInstr &MI,
diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp
index 98e4b452a8a5e..d5e804afd27fe 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.cpp
+++ b/llvm/lib/Target/VE/VEInstrInfo.cpp
@@ -34,8 +34,8 @@ using namespace llvm;
// Pin the vtable to this file.
void VEInstrInfo::anchor() {}
-VEInstrInfo::VEInstrInfo(VESubtarget &ST)
- : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {}
+VEInstrInfo::VEInstrInfo(const VESubtarget &ST)
+ : VEGenInstrInfo(ST, VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {}
static bool IsIntegerCC(unsigned CC) { return (CC < VECC::CC_AF); }
diff --git a/llvm/lib/Target/VE/VEInstrInfo.h b/llvm/lib/Target/VE/VEInstrInfo.h
index 49dcba5034624..408d3ab9e05f5 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.h
+++ b/llvm/lib/Target/VE/VEInstrInfo.h
@@ -53,7 +53,7 @@ class VEInstrInfo : public VEGenInstrInfo {
virtual void anchor();
public:
- explicit VEInstrInfo(VESubtarget &ST);
+ explicit VEInstrInfo(const VESubtarget &ST);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
index a934853ff9f45..feac04a17068a 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
@@ -34,7 +34,7 @@ using namespace llvm;
#include "WebAssemblyGenInstrInfo.inc"
WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
- : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
+ : WebAssemblyGenInstrInfo(STI, WebAssembly::ADJCALLSTACKDOWN,
WebAssembly::ADJCALLSTACKUP,
WebAssembly::CATCHRET),
RI(STI.getTargetTriple()) {}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 5c0deeb56c295..a68edf4d2b7ee 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -83,8 +83,9 @@ static cl::opt<unsigned> UndefRegClearance(
// Pin the vtable to this file.
void X86InstrInfo::anchor() {}
-X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
- : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
+X86InstrInfo::X86InstrInfo(const X86Subtarget &STI)
+ : X86GenInstrInfo(STI,
+ (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
: X86::ADJCALLSTACKDOWN32),
(STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
: X86::ADJCALLSTACKUP32),
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 9dc5f4b0e086e..f087b7f20ff67 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -222,7 +222,7 @@ inline static bool isMemInstrWithGOTPCREL(const MachineInstr &MI) {
}
class X86InstrInfo final : public X86GenInstrInfo {
- X86Subtarget &Subtarget;
+ const X86Subtarget &Subtarget;
const X86RegisterInfo RI;
LLVM_DECLARE_VIRTUAL_ANCHOR_FUNCTION();
@@ -238,7 +238,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
bool MakeChange) const;
public:
- explicit X86InstrInfo(X86Subtarget &STI);
+ explicit X86InstrInfo(const X86Subtarget &STI);
/// Given a machine instruction descriptor, returns the register
/// class constraint for OpNum, or NULL. Returned register class
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
index 0a86588b6bdb4..1a9133aad4dd3 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -12,6 +12,7 @@
#include "XCoreInstrInfo.h"
#include "XCore.h"
+#include "XCoreSubtarget.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -41,10 +42,9 @@ namespace XCore {
// Pin the vtable to this file.
void XCoreInstrInfo::anchor() {}
-XCoreInstrInfo::XCoreInstrInfo()
- : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
- RI() {
-}
+XCoreInstrInfo::XCoreInstrInfo(const XCoreSubtarget &ST)
+ : XCoreGenInstrInfo(ST, XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
+ RI() {}
static bool isZeroImm(const MachineOperand &op) {
return op.isImm() && op.getImm() == 0;
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h
index 5026671616fae..3fe84c3787e42 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.h
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h
@@ -20,12 +20,13 @@
#include "XCoreGenInstrInfo.inc"
namespace llvm {
+class XCoreSubtarget;
class XCoreInstrInfo : public XCoreGenInstrInfo {
const XCoreRegisterInfo RI;
virtual void anchor();
public:
- XCoreInstrInfo();
+ XCoreInstrInfo(const XCoreSubtarget &ST);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
diff --git a/llvm/lib/Target/XCore/XCoreSubtarget.cpp b/llvm/lib/Target/XCore/XCoreSubtarget.cpp
index d4b777ef447fd..2f6517ec9e7ad 100644
--- a/llvm/lib/Target/XCore/XCoreSubtarget.cpp
+++ b/llvm/lib/Target/XCore/XCoreSubtarget.cpp
@@ -26,5 +26,5 @@ void XCoreSubtarget::anchor() { }
XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
- : XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), FrameLowering(*this),
- TLInfo(TM, *this) {}
+ : XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(*this),
+ FrameLowering(*this), TLInfo(TM, *this) {}
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
index 55c0729a0c9e7..b0f924f2cd58e 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
@@ -48,7 +48,7 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI) {
}
XtensaInstrInfo::XtensaInstrInfo(const XtensaSubtarget &STI)
- : XtensaGenInstrInfo(Xtensa::ADJCALLSTACKDOWN, Xtensa::ADJCALLSTACKUP),
+ : XtensaGenInstrInfo(STI, Xtensa::ADJCALLSTACKDOWN, Xtensa::ADJCALLSTACKUP),
RI(STI), STI(STI) {}
Register XtensaInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
diff --git a/llvm/unittests/Target/DirectX/RegisterCostTests.cpp b/llvm/unittests/Target/DirectX/RegisterCostTests.cpp
index ebf740ed73e98..55a0e9f50b393 100644
--- a/llvm/unittests/Target/DirectX/RegisterCostTests.cpp
+++ b/llvm/unittests/Target/DirectX/RegisterCostTests.cpp
@@ -24,8 +24,7 @@ using namespace llvm::dxil;
namespace {
class RegisterCostTests : public testing::Test {
protected:
- DirectXInstrInfo DXInstInfo;
- DirectXRegisterInfo RI;
+ std::unique_ptr<DirectXInstrInfo> DXInstInfo;
DirectXTargetLowering *DL;
virtual void SetUp() {
@@ -37,11 +36,15 @@ class RegisterCostTests : public testing::Test {
StringRef FS = "";
DirectXTargetMachine TM(T, TT, CPU, FS, TargetOptions(), Reloc::Static,
CodeModel::Small, CodeGenOptLevel::Default, false);
+
LLVMContext Context;
Function *F =
Function::Create(FunctionType::get(Type::getVoidTy(Context), false),
Function::ExternalLinkage, 0);
- DL = new DirectXTargetLowering(TM, *TM.getSubtargetImpl(*F));
+ const DirectXSubtarget *DXSubtarget = TM.getSubtargetImpl(*F);
+ DL = new DirectXTargetLowering(TM, *DXSubtarget);
+ DXInstInfo = std::make_unique<DirectXInstrInfo>(*DXSubtarget);
+
delete F;
}
virtual void TearDown() { delete DL; }
@@ -53,12 +56,12 @@ TEST_F(RegisterCostTests, TestRepRegClassForVTSet) {
}
TEST_F(RegisterCostTests, TestTrivialCopyCostGetter) {
-
- const TargetRegisterClass *RC = DXInstInfo.getRegisterInfo().getRegClass(0);
+ const DirectXRegisterInfo &TRI = DXInstInfo->getRegisterInfo();
+ const TargetRegisterClass *RC = TRI.getRegClass(0);
unsigned Cost = RC->getCopyCost();
EXPECT_EQ(1u, Cost);
- RC = RI.getRegClass(0);
+ RC = TRI.getRegClass(0);
Cost = RC->getCopyCost();
EXPECT_EQ(1u, Cost);
}
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 9e03e28a26d8d..5cdf4fbb297f3 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -1070,7 +1070,9 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "namespace llvm {\n";
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
<< " explicit " << ClassName
- << "(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, "
+ << "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode = ~0u, "
+ "unsigned "
+ "CFDestroyOpcode = ~0u, "
"unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);\n"
<< " ~" << ClassName << "() override = default;\n";
@@ -1104,7 +1106,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "extern const MCInstrInfo::ComplexDeprecationPredicate " << TargetName
<< "InstrComplexDeprecationInfos[];\n";
OS << ClassName << "::" << ClassName
- << "(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned "
+ << "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode, unsigned "
+ "CFDestroyOpcode, unsigned "
"CatchRetOpcode, unsigned ReturnOpcode)\n"
<< " : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, "
"ReturnOpcode) {\n"
>From 986b1c9f366987b0db91d0115ec5f168050ed611 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sun, 7 Sep 2025 22:24:47 +0900
Subject: [PATCH 2/4] Apply suggestions from code review
Co-authored-by: Sergei Barannikov <barannikov88 at gmail.com>
---
llvm/lib/Target/XCore/XCoreInstrInfo.h | 2 +-
llvm/utils/TableGen/InstrInfoEmitter.cpp | 6 ++----
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h
index 3fe84c3787e42..3543392653786 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.h
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h
@@ -26,7 +26,7 @@ class XCoreInstrInfo : public XCoreGenInstrInfo {
const XCoreRegisterInfo RI;
virtual void anchor();
public:
- XCoreInstrInfo(const XCoreSubtarget &ST);
+ explicit XCoreInstrInfo(const XCoreSubtarget &ST);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 5cdf4fbb297f3..0174475e70602 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -1071,8 +1071,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
<< " explicit " << ClassName
<< "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode = ~0u, "
- "unsigned "
- "CFDestroyOpcode = ~0u, "
+ "unsigned CFDestroyOpcode = ~0u, "
"unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);\n"
<< " ~" << ClassName << "() override = default;\n";
@@ -1107,8 +1106,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
<< "InstrComplexDeprecationInfos[];\n";
OS << ClassName << "::" << ClassName
<< "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode, unsigned "
- "CFDestroyOpcode, unsigned "
- "CatchRetOpcode, unsigned ReturnOpcode)\n"
+ "CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)\n"
<< " : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, "
"ReturnOpcode) {\n"
<< " InitMCInstrInfo(" << TargetName << "Descs.Insts, " << TargetName
>From 34a68a575974fa6cdbf9e112dc974a0255231ea0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sun, 7 Sep 2025 22:26:23 +0900
Subject: [PATCH 3/4] Update llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
Co-authored-by: Sergei Barannikov <barannikov88 at gmail.com>
---
llvm/lib/Target/SPIRV/SPIRVInstrInfo.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
index 0ae924f23d783..72d2243fba62a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
@@ -26,7 +26,7 @@ class SPIRVInstrInfo : public SPIRVGenInstrInfo {
const SPIRVRegisterInfo RI;
public:
- SPIRVInstrInfo(const SPIRVSubtarget &STI);
+ explicit SPIRVInstrInfo(const SPIRVSubtarget &STI);
const SPIRVRegisterInfo &getRegisterInfo() const { return RI; }
bool isHeaderInstr(const MachineInstr &MI) const;
>From 9bb233473d1b34f7cef79c4e817ea93aba2b3eeb Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sun, 7 Sep 2025 22:26:31 +0900
Subject: [PATCH 4/4] Update llvm/lib/Target/BPF/BPFInstrInfo.h
Co-authored-by: Sergei Barannikov <barannikov88 at gmail.com>
---
llvm/lib/Target/BPF/BPFInstrInfo.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.h b/llvm/lib/Target/BPF/BPFInstrInfo.h
index 94e6737707376..2359e43e483f8 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.h
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.h
@@ -26,7 +26,7 @@ class BPFInstrInfo : public BPFGenInstrInfo {
const BPFRegisterInfo RI;
public:
- BPFInstrInfo(const BPFSubtarget &STI);
+ explicit BPFInstrInfo(const BPFSubtarget &STI);
const BPFRegisterInfo &getRegisterInfo() const { return RI; }
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