[llvm] [CSKY] Decode CARRY / GPRSP operands not encoded into instruction (NFCI) (PR #157338)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 7 06:17:23 PDT 2025
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/157338
The generated decoder can now decode these operands. All we need to do is to add `bits<0>` for these operands to instruction records.
While here, reformat adjacent lines.
>From 1e3513c74f2a90abc47cf3c82ebb41bc4980d53f Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sun, 7 Sep 2025 16:06:43 +0300
Subject: [PATCH] [CSKY] Decode CARRY / GPRSP operands not encoded into
instruction
The generated decoder can now decode these operands. All we need to do
is to add `bits<0>` for these operands to instruction records.
---
llvm/lib/Target/CSKY/CMakeLists.txt | 3 +-
llvm/lib/Target/CSKY/CSKYInstrFormats.td | 28 ++--
.../Target/CSKY/CSKYInstrFormats16Instr.td | 31 ++--
llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td | 24 +--
llvm/lib/Target/CSKY/CSKYInstrFormatsF2.td | 17 ++-
llvm/lib/Target/CSKY/CSKYInstrInfo.td | 83 +++++++----
llvm/lib/Target/CSKY/CSKYInstrInfo16Instr.td | 31 ++--
.../CSKY/Disassembler/CSKYDisassembler.cpp | 138 ++----------------
8 files changed, 155 insertions(+), 200 deletions(-)
diff --git a/llvm/lib/Target/CSKY/CMakeLists.txt b/llvm/lib/Target/CSKY/CMakeLists.txt
index 101b34ea18442..4b900bc99c271 100644
--- a/llvm/lib/Target/CSKY/CMakeLists.txt
+++ b/llvm/lib/Target/CSKY/CMakeLists.txt
@@ -7,8 +7,7 @@ tablegen(LLVM CSKYGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM CSKYGenCallingConv.inc -gen-callingconv)
tablegen(LLVM CSKYGenCompressInstEmitter.inc -gen-compress-inst-emitter)
tablegen(LLVM CSKYGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM CSKYGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM CSKYGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM CSKYGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM CSKYGenMCPseudoLowering.inc -gen-pseudo-lowering)
diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormats.td b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
index 5296d282c689b..abf5cac0013d2 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrFormats.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
@@ -168,7 +168,9 @@ class I_16_RET<bits<5> sop, bits<5> pcode, string op, list<dag> pattern>
// Instructions(3): cmpnei32, cmphsi32, cmplti32
class I_16_X<bits<5> sop, string op, Operand operand>
: CSKY32Inst<AddrModeNone, 0x3a, (outs CARRY:$ca),
- (ins GPR:$rx, operand:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
+ (ins GPR:$rx, operand:$imm16),
+ !strconcat(op, "\t$rx, $imm16"), []> {
+ bits<0> ca;
bits<16> imm16;
bits<5> rx;
let Inst{25 - 21} = sop;
@@ -263,8 +265,9 @@ class I_12_PP<bits<5> sop, bits<5> pcode, dag outs, dag ins, string op>
class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
list<dag> pattern>
: CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
- (ins CARRY:$cond, GPR:$false, GPR:$rx, ImmType:$imm5),
- !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
+ (ins CARRY:$cond, GPR:$false, GPR:$rx, ImmType:$imm5),
+ !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
+ bits<0> cond;
bits<5> rz;
bits<5> rx;
bits<5> imm5;
@@ -469,9 +472,10 @@ class I_5_XZ_UZ<bits<6> sop, bits<5> lsb, bits<5> msb, string op, int v>
// Instructions(1): btsti32
class I_5_X<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
list<dag> pattern>
- : CSKY32Inst<AddrModeNone, 0x31,
- (outs CARRY:$ca), (ins GPR:$rx, ImmType:$imm5),
- !strconcat(op, "\t$rx, $imm5"), pattern> {
+ : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca),
+ (ins GPR:$rx, ImmType:$imm5),
+ !strconcat(op, "\t$rx, $imm5"), pattern> {
+ bits<0> ca;
bits<5> imm5;
bits<5> rx;
let Inst{25 - 21} = imm5;
@@ -581,9 +585,9 @@ class R_XXZ<bits<6> sop, bits<5> pcode, dag outs, dag ins, string op,
// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
// Instructions:(4) cmpne32, cmphs32, cmplt32, tst32
class R_YX<bits<6> sop, bits<5> pcode, string op>
- : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca),
- (ins GPR:$rx, GPR:$ry),
+ : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca), (ins GPR:$rx, GPR:$ry),
!strconcat(op, "\t$rx, $ry"), []> {
+ bits<0> ca;
bits<5> ry;
bits<5> rx;
let Inst{25 - 21} = ry;
@@ -642,8 +646,9 @@ class R_X<bits<6> sop, bits<5> pcode, dag outs, dag ins, string op, list<dag> pa
// Format< OP[6] | 00000[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5] >
// Instructions:(2) mvc32, mvcv32
class R_Z_1<bits<6> sop, bits<5> pcode, string op>
- : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
- (ins CARRY:$ca), !strconcat(op, "\t$rz"), []> {
+ : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins CARRY:$ca),
+ !strconcat(op, "\t$rz"), []> {
+ bits<0> ca;
bits<5> rz;
let Inst{25 - 21} = 0;
let Inst{20 - 16} = 0;
@@ -656,7 +661,8 @@ class R_Z_1<bits<6> sop, bits<5> pcode, string op>
// Instructions:(2) clrf32, clrt32
class R_Z_2<bits<6> sop, bits<5> pcode, string op>
: CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
- (ins CARRY:$ca, GPR:$false), !strconcat(op, "\t$rz"), []> {
+ (ins CARRY:$ca, GPR:$false), !strconcat(op, "\t$rz"), []> {
+ bits<0> ca;
bits<5> rz;
let Inst{25 - 21} = rz;
let Inst{20 - 16} = 0;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormats16Instr.td b/llvm/lib/Target/CSKY/CSKYInstrFormats16Instr.td
index ea0761d97545d..5cd970d27d478 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrFormats16Instr.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormats16Instr.td
@@ -16,8 +16,9 @@ class J16<bits<5> sop, string opstr, dag ins>
}
class J16_B<bits<5> sop, string opstr>
- : CSKY16Inst<AddrModeNone, (outs), (ins CARRY:$ca, br_symbol_16bit:$offset),
- !strconcat(opstr, "\t$offset"), []> {
+ : CSKY16Inst<AddrModeNone, (outs), (ins CARRY:$ca, br_symbol_16bit:$offset),
+ !strconcat(opstr, "\t$offset"), []> {
+ bits<0> ca;
bits<10> offset;
let Inst{15} = 0;
let Inst{14 - 10} = sop;
@@ -66,6 +67,8 @@ class R16_XZ_BINOP_NOPat<bits<4> op, bits<2> sop, string opstr> : CSKY16Inst<
class R16_XZ_BINOP_C<bits<4> op, bits<2> sop, string opstr> : CSKY16Inst<
AddrModeNone, (outs sGPR:$rz, CARRY:$cout),
(ins sGPR:$rZ, sGPR:$rx, CARRY:$cin), !strconcat(opstr, "\t$rz, $rx"), []> {
+ bits<0> cout;
+ bits<0> cin;
bits<4> rz;
bits<4> rx;
let Inst{15, 14} = 0b01;
@@ -101,9 +104,10 @@ class R16_Z_UNOP<bits<4> op, bits<2> sop, string opstr> : CSKY16Inst<
let Constraints = "$rz = $rx";
}
-class R16_XY_CMP<bits<2> sop, string opstr> : CSKY16Inst<
- AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx, sGPR:$ry), !strconcat(opstr, "\t$rx, $ry"),
- []> {
+class R16_XY_CMP<bits<2> sop, string opstr>
+ : CSKY16Inst<AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx, sGPR:$ry),
+ !strconcat(opstr, "\t$rx, $ry"), []> {
+ bits<0> ca;
bits<4> ry;
bits<4> rx;
let Inst{15, 14} = 0b01;
@@ -145,9 +149,11 @@ class I16_Z_5<bits<3> sop, dag outs, dag ins,string opstr>
let Inst{4 - 0} = imm5;
}
-class I16_X_CMP<bits<3> sop, string opstr, Operand Immoperand> : CSKY16Inst<
- AddrModeNone, (outs CARRY:$ca), (ins mGPR:$rx, Immoperand:$imm5),
- !strconcat(opstr, "\t$rx, $imm5"), []> {
+class I16_X_CMP<bits<3> sop, string opstr, Operand Immoperand>
+ : CSKY16Inst<AddrModeNone, (outs CARRY:$ca),
+ (ins mGPR:$rx, Immoperand:$imm5),
+ !strconcat(opstr, "\t$rx, $imm5"), []> {
+ bits<0> ca;
bits<3> rx;
bits<5> imm5;
let Inst{15, 14} = 0b00;
@@ -158,9 +164,12 @@ class I16_X_CMP<bits<3> sop, string opstr, Operand Immoperand> : CSKY16Inst<
let isCompare = 1;
}
-class I16_SP_IMM7<bits<3> sop, string opstr> : CSKY16Inst<
- AddrModeNone, (outs GPRSP:$sp2), (ins GPRSP:$sp1, uimm7_2:$imm7),
- !strconcat(opstr, "\t$sp2, $sp1, $imm7"), []> {
+class I16_SP_IMM7<bits<3> sop, string opstr>
+ : CSKY16Inst<AddrModeNone, (outs GPRSP:$sp2),
+ (ins GPRSP:$sp1, uimm7_2:$imm7),
+ !strconcat(opstr, "\t$sp2, $sp1, $imm7"), []> {
+ bits<0> sp2;
+ bits<0> sp1;
bits<7> imm7;
let Inst{15, 14} = 0b00;
let Inst{13 - 10} = 0b0101;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td b/llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td
index 446670a4d0a97..a40874b054d8d 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td
@@ -91,15 +91,21 @@ multiclass FT_XZ<bits<6> sop, string op, PatFrag opnode> {
}
let vrz = 0, isCompare = 1 in {
-class F_CMPXY<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterOperand regtype>
- : F_XYZ_BASE<datatype, sop, (outs CARRY:$ca), (ins regtype:$vrx, regtype:$vry), !strconcat(op#op_su, "\t$vrx, $vry"),
- []>;
-
-let vry = 0 in{
-class F_CMPZX<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterOperand regtype>
- : F_XYZ_BASE<datatype, sop, (outs CARRY:$ca), (ins regtype:$vrx), !strconcat(op#op_su, "\t$vrx"),
- []>;
-}
+ class F_CMPXY<bits<5> datatype, bits<6> sop, string op, string op_su,
+ RegisterOperand regtype>
+ : F_XYZ_BASE<datatype, sop, (outs CARRY:$ca),
+ (ins regtype:$vrx, regtype:$vry),
+ !strconcat(op#op_su, "\t$vrx, $vry"), []> {
+ bits<0> ca;
+ }
+
+ let vry = 0 in
+ class F_CMPZX<bits<5> datatype, bits<6> sop, string op, string op_su,
+ RegisterOperand regtype>
+ : F_XYZ_BASE<datatype, sop, (outs CARRY:$ca), (ins regtype:$vrx),
+ !strconcat(op#op_su, "\t$vrx"), []> {
+ bits<0> ca;
+ }
}
class F_XYZ<bits<5> datatype, bits<6> sop, string op, string op_su, PatFrag opnode, RegisterOperand regtype>
diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormatsF2.td b/llvm/lib/Target/CSKY/CSKYInstrFormatsF2.td
index 641ad623f140e..bd7c554565cd1 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrFormatsF2.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormatsF2.td
@@ -91,8 +91,9 @@ multiclass F2_XZ_SET_T<bits<6> sop, string op, string suffix = ""> {
let vrz = 0, isCompare = 1 in
class F2_CXY<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
: F2_XYZ<datatype, sop, !strconcat(op, "\t$vrx, $vry"),
- (outs CARRY:$ca), (ins regtype:$vrx, regtype:$vry),
- []>;
+ (outs CARRY:$ca), (ins regtype:$vrx, regtype:$vry), []> {
+ bits<0> ca;
+}
multiclass F2_CXY_T<bits<6> sop, string op> {
def _S : F2_CXY<0b00000, FPR32Op, sop, op#".32">;
@@ -103,9 +104,10 @@ multiclass F2_CXY_T<bits<6> sop, string op> {
let vrz = 0, vry = 0, isCompare = 1 in
class F2_CX<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
- : F2_XYZ<datatype, sop, !strconcat(op, "\t$vrx"),
- (outs CARRY:$ca), (ins regtype:$vrx),
- []>;
+ : F2_XYZ<datatype, sop, !strconcat(op, "\t$vrx"), (outs CARRY:$ca),
+ (ins regtype:$vrx), []> {
+ bits<0> ca;
+}
multiclass F2_CX_T<bits<6> sop, string op> {
def _S : F2_CX<0b00000, FPR32Op, sop, op#".32">;
@@ -183,7 +185,10 @@ class F2_LDSTR_D<bits<1> sop, string op, dag outs, dag ins>
class F2_CXYZ<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
: F2_XYZ<datatype, sop, !strconcat(op, "\t$vrz, $vrx, $vry"),
(outs regtype:$vrz), (ins CARRY:$ca, regtype:$vrx, regtype:$vry),
- []>;
+ []> {
+ bits<0> ca;
+}
+
multiclass F2_CXYZ_T<bits<6> sop, string op> {
def _S : F2_CXYZ<0b00000, FPR32Op, sop, op#".32">;
let Predicates = [HasFPUv3_DF] in
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.td b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
index c6bfc2495ae29..82e271e5b5565 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
@@ -586,14 +586,23 @@ let Predicates = [iHasE2] in {
BinOpFrag<(rotl node:$LHS, (and node:$RHS, 0x1f))>, "rotl32">;
def BMASKI32 : I_5_Z<0b010100, 0x1, "bmaski32", oimm5, []>;
- def LSLC32 : I_5_XZ<0x13, 0x1, "lslc32",
- (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5), []>;
- def LSRC32 : I_5_XZ<0x13, 0x2, "lsrc32",
- (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5), []>;
- def ASRC32 : I_5_XZ<0x13, 0x4, "asrc32",
- (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5), []>;
- def XSR32 : I_5_XZ<0x13, 0x8, "xsr32",
- (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5, CARRY:$cin), []>;
+ def LSLC32 : I_5_XZ<0x13, 0x1, "lslc32", (outs GPR:$rz, CARRY:$cout),
+ (ins GPR:$rx, oimm5:$imm5), []> {
+ bits<0> cout;
+ }
+ def LSRC32 : I_5_XZ<0x13, 0x2, "lsrc32", (outs GPR:$rz, CARRY:$cout),
+ (ins GPR:$rx, oimm5:$imm5), []> {
+ bits<0> cout;
+ }
+ def ASRC32 : I_5_XZ<0x13, 0x4, "asrc32", (outs GPR:$rz, CARRY:$cout),
+ (ins GPR:$rx, oimm5:$imm5), []> {
+ bits<0> cout;
+ }
+ def XSR32 : I_5_XZ<0x13, 0x8, "xsr32", (outs GPR:$rz, CARRY:$cout),
+ (ins GPR:$rx, oimm5:$imm5, CARRY:$cin), []> {
+ bits<0> cout;
+ bits<0> cin;
+ }
def IXH32 : R_YXZ_SP_F1<0x2, 0x1,
BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 1)))>, "ixh32">;
@@ -605,9 +614,15 @@ let Predicates = [iHasE2] in {
let isCommutable = 1, isAdd = 1 in
def ADDC32 : R_YXZ<0x31, 0x0, 0x2, (outs GPR:$rz, CARRY:$cout),
- (ins GPR:$rx, GPR:$ry, CARRY:$cin), "addc32", []>;
+ (ins GPR:$rx, GPR:$ry, CARRY:$cin), "addc32", []> {
+ bits<0> cout;
+ bits<0> cin;
+ }
def SUBC32 : R_YXZ<0x31, 0x0, 0x8, (outs GPR:$rz, CARRY:$cout),
- (ins GPR:$rx, GPR:$ry, CARRY:$cin), "subc32", []>;
+ (ins GPR:$rx, GPR:$ry, CARRY:$cin), "subc32", []> {
+ bits<0> cout;
+ bits<0> cin;
+ }
def INCF32 : I_5_ZX<0x3, 0x1, "incf32", uimm5, []>;
def INCT32 : I_5_ZX<0x3, 0x2, "inct32", uimm5, []>;
@@ -621,12 +636,18 @@ let Predicates = [iHas2E3] in {
def DIVU32 : R_YXZ_SP_F1<0x20, 0x1,
BinOpFrag<(udiv node:$LHS, node:$RHS)>, "divu32">;
- def DECGT32 : I_5_XZ<0x4, 0x1, "decgt32",
- (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
- def DECLT32 : I_5_XZ<0x4, 0x2, "declt32",
- (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
- def DECNE32 : I_5_XZ<0x4, 0x4, "decne32",
- (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
+ def DECGT32 : I_5_XZ<0x4, 0x1, "decgt32", (outs GPR:$rz, CARRY:$cout),
+ (ins GPR:$rx, uimm5:$imm5), []> {
+ bits<0> cout;
+ }
+ def DECLT32 : I_5_XZ<0x4, 0x2, "declt32", (outs GPR:$rz, CARRY:$cout),
+ (ins GPR:$rx, uimm5:$imm5), []> {
+ bits<0> cout;
+ }
+ def DECNE32 : I_5_XZ<0x4, 0x4, "decne32", (outs GPR:$rz, CARRY:$cout),
+ (ins GPR:$rx, uimm5:$imm5), []> {
+ bits<0> cout;
+ }
def SEXT32 : I_5_XZ_U<0x16, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "sext32", []>;
let isCodeGenOnly = 1 in {
@@ -744,8 +765,9 @@ let Predicates = [iHas2E3] in {
def CMPHS32 : R_YX<0x1, 0x1, "cmphs32">;
def CMPLT32 : R_YX<0x1, 0x2, "cmplt32">;
- def SETC32 : CSKY32Inst<AddrModeNone, 0x31,
- (outs CARRY:$ca), (ins), "setc32", []> {
+ def SETC32 : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca), (ins), "setc32",
+ []> {
+ bits<0> ca;
let Inst{25 - 21} = 0; //rx
let Inst{20 - 16} = 0; //ry
let Inst{15 - 10} = 0x1;
@@ -753,8 +775,9 @@ let Predicates = [iHas2E3] in {
let Inst{4 - 0} = 0;
let isCompare = 1;
}
- def CLRC32 : CSKY32Inst<AddrModeNone, 0x31,
- (outs CARRY:$ca), (ins), "clrc32", []> {
+ def CLRC32 : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca), (ins), "clrc32",
+ []> {
+ bits<0> ca;
let Inst{25 - 21} = 0; //rx
let Inst{20 - 16} = 0; //ry
let Inst{15 - 10} = 0x1;
@@ -764,8 +787,10 @@ let Predicates = [iHas2E3] in {
}
def TST32 : R_YX<0x8, 0x4, "tst32">;
- def TSTNBZ32 : R_X<0x8, 0x8,
- (outs CARRY:$ca), (ins GPR:$rx), "tstnbz32", []>;
+ def TSTNBZ32 : R_X<0x8, 0x8, (outs CARRY:$ca), (ins GPR:$rx), "tstnbz32",
+ []> {
+ bits<0> ca;
+ }
}
//===----------------------------------------------------------------------===//
@@ -806,9 +831,14 @@ let isBranch = 1, isTerminator = 1 in {
[(br bb:$imm16)]>;
def BT32 : I_16_L<0x3, (outs), (ins CARRY:$ca, br_symbol:$imm16),
- "bt32\t$imm16", [(brcond CARRY:$ca, bb:$imm16)]>, Requires<[iHasE2]>;
+ "bt32\t$imm16", [(brcond CARRY:$ca, bb:$imm16)]>,
+ Requires<[iHasE2]> {
+ bits<0> ca;
+ }
def BF32 : I_16_L<0x2, (outs), (ins CARRY:$ca, br_symbol:$imm16),
- "bf32\t$imm16", []>, Requires<[iHasE2]>;
+ "bf32\t$imm16", []>, Requires<[iHasE2]> {
+ bits<0> ca;
+ }
}
let Predicates = [iHas2E3] in {
@@ -1030,7 +1060,10 @@ def SE32 : I_5_XZ_PRIVI<0b010110, 0x1, "se32">;
def WSC32 : I_5_XZ_PRIVI<0b001111, 0x1, "wsc32">;
def CPOP32 : I_CPOP<(outs), (ins uimm5:$cpid, uimm20:$usdef), "cpop32 <$cpid, ${usdef}>">;
-def CPRC32 : I_CP<0b0100, (outs CARRY:$ca), (ins uimm5:$cpid, uimm12:$usdef), "cprc32 <$cpid, ${usdef}>">;
+def CPRC32 : I_CP<0b0100, (outs CARRY:$ca), (ins uimm5:$cpid, uimm12:$usdef),
+ "cprc32 <$cpid, ${usdef}>"> {
+ bits<0> ca;
+}
def CPRCR32 : I_CP_Z<0b0010, (outs GPR:$rz), (ins uimm5:$cpid, uimm12:$usdef), "cprcr32 $rz, <$cpid, ${usdef}>">;
def CPRGR32 : I_CP_Z<0b0000, (outs GPR:$rz), (ins uimm5:$cpid, uimm12:$usdef), "cprgr32 $rz, <$cpid, ${usdef}>">;
def CPWCR32 : I_CP_Z<0b0011, (outs), (ins GPR:$rz, uimm5:$cpid, uimm12:$usdef), "cpwcr32 $rz, <$cpid, ${usdef}>">;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo16Instr.td b/llvm/lib/Target/CSKY/CSKYInstrInfo16Instr.td
index 3e248019d73f9..51645215f32a8 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo16Instr.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo16Instr.td
@@ -102,7 +102,9 @@ def : Pat<(add GPR:$rs1, (oimm8_neg:$im)),
let isAdd = 1 in
def ADDI16ZSP : I16_Z_8<0b011, (ins GPRSP:$sp, uimm8_2:$imm8),
- "addi16\t$rz, $sp, $imm8">;
+ "addi16\t$rz, $sp, $imm8"> {
+ bits<0> sp;
+}
let isAdd = 1 in
def ADDI16SPSP : I16_SP_IMM7<0b000,"addi16">;
@@ -142,10 +144,14 @@ def ST16H : I16_XZ_LDST<AddrMode16H, 0b101, "st16.h",
def ST16W : I16_XZ_LDST<AddrMode16W, 0b110, "st16.w",
(outs), (ins mGPR:$rz, mGPR:$rx, uimm5_2:$imm)>;
-def LD16WSP : I16_ZSP_LDST<AddrMode16W, 0b011, "ld16.w",
- (outs mGPR:$rz), (ins GPRSP:$sp, uimm8_2:$addr)>;
-def ST16WSP : I16_ZSP_LDST<AddrMode16W, 0b111, "st16.w",
- (outs), (ins mGPR:$rz, GPRSP:$sp, uimm8_2:$addr)>;
+def LD16WSP : I16_ZSP_LDST<AddrMode16W, 0b011, "ld16.w", (outs mGPR:$rz),
+ (ins GPRSP:$sp, uimm8_2:$addr)> {
+ bits<0> sp;
+}
+def ST16WSP : I16_ZSP_LDST<AddrMode16W, 0b111, "st16.w", (outs),
+ (ins mGPR:$rz, GPRSP:$sp, uimm8_2:$addr)> {
+ bits<0> sp;
+}
//===----------------------------------------------------------------------===//
// Compare instructions.
@@ -187,8 +193,9 @@ def MOV16 : CSKY16Inst<AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rx),
}
// MVC16 is not in "cskyv2 instructions reference manul"
-def MVCV16 : CSKY16Inst<AddrModeNone,
- (outs sGPR:$rz), (ins CARRY:$ca), "mvcv16\t$rz", []> {
+def MVCV16 : CSKY16Inst<AddrModeNone, (outs sGPR:$rz), (ins CARRY:$ca),
+ "mvcv16\t$rz", []> {
+ bits<0> ca;
bits<4> rz;
let Inst{15,14} = 0b01;
let Inst{13 - 10} = 0b1001;
@@ -317,11 +324,14 @@ let Constraints = "$rZ = $rz" in {
}
let Predicates = [HasBTST16] in
- def BTSTI16 : I16_Z_5<0b110, (outs CARRY:$ca), (ins mGPR:$rz, uimm5:$imm5),
- "btsti16">;
+def BTSTI16 : I16_Z_5<0b110, (outs CARRY:$ca), (ins mGPR:$rz, uimm5:$imm5),
+ "btsti16"> {
+ bits<0> ca;
+}
def TST16 : CSKY16Inst<AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx, sGPR:$ry),
- "tst16\t$rx, $ry", []> {
+ "tst16\t$rx, $ry", []> {
+ bits<0> ca;
bits<4> ry;
bits<4> rx;
let Inst{15,14} = 0b01;
@@ -334,6 +344,7 @@ def TST16 : CSKY16Inst<AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx, sGPR:$ry),
def TSTNBZ16 : CSKY16Inst<AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx),
"tstnbz16\t$rx", []> {
+ bits<0> ca;
bits<4> rx;
let Inst{15,14} = 0b01;
let Inst{13 - 10} = 0b1010;
diff --git a/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp b/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
index 749127f4ddc8a..887e281279535 100644
--- a/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
+++ b/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
@@ -36,8 +36,6 @@ class CSKYDisassembler : public MCDisassembler {
std::unique_ptr<MCInstrInfo const> const MCII;
mutable StringRef symbolName;
- DecodeStatus handleCROperand(MCInst &Instr) const;
-
public:
CSKYDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
MCInstrInfo const *MCII);
@@ -198,15 +196,9 @@ static DecodeStatus DecodemGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
return MCDisassembler::Success;
}
-// TODO
-LLVM_ATTRIBUTE_UNUSED
-static DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst, uint64_t RegNo,
- uint64_t Address,
+static DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst,
const MCDisassembler *Decoder) {
- if (RegNo != 14)
- return MCDisassembler::Fail;
-
- Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
+ Inst.addOperand(MCOperand::createReg(CSKY::R14));
return MCDisassembler::Success;
}
@@ -224,6 +216,12 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint64_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeCARRYRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(CSKY::C));
+ return MCDisassembler::Success;
+}
+
template <unsigned N, unsigned S>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
int64_t Address,
@@ -378,121 +376,6 @@ static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
#include "CSKYGenDisassemblerTables.inc"
-DecodeStatus CSKYDisassembler::handleCROperand(MCInst &MI) const {
-
- // FIXME: To query instruction info from td file or a table inc file
- switch (MI.getOpcode()) {
- default:
- return MCDisassembler::Success;
- case CSKY::LD16WSP:
- case CSKY::ST16WSP:
- case CSKY::ADDI16ZSP:
- MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::R14));
- return MCDisassembler::Success;
- case CSKY::ADDI16SPSP:
- case CSKY::SUBI16SPSP:
- MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14));
- MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14));
- return MCDisassembler::Success;
- case CSKY::FCMPHS_S:
- case CSKY::FCMPHS_D:
- case CSKY::FCMPLT_S:
- case CSKY::FCMPLT_D:
- case CSKY::FCMPNE_S:
- case CSKY::FCMPNE_D:
- case CSKY::FCMPUO_S:
- case CSKY::FCMPUO_D:
- case CSKY::FCMPZHS_S:
- case CSKY::FCMPZHS_D:
- case CSKY::FCMPZLS_S:
- case CSKY::FCMPZLS_D:
- case CSKY::FCMPZNE_S:
- case CSKY::FCMPZNE_D:
- case CSKY::FCMPZUO_S:
- case CSKY::FCMPZUO_D:
- case CSKY::f2FCMPHS_S:
- case CSKY::f2FCMPHS_D:
- case CSKY::f2FCMPLT_S:
- case CSKY::f2FCMPLT_D:
- case CSKY::f2FCMPNE_S:
- case CSKY::f2FCMPNE_D:
- case CSKY::f2FCMPUO_S:
- case CSKY::f2FCMPUO_D:
- case CSKY::f2FCMPHSZ_S:
- case CSKY::f2FCMPHSZ_D:
- case CSKY::f2FCMPHZ_S:
- case CSKY::f2FCMPHZ_D:
- case CSKY::f2FCMPLSZ_S:
- case CSKY::f2FCMPLSZ_D:
- case CSKY::f2FCMPLTZ_S:
- case CSKY::f2FCMPLTZ_D:
- case CSKY::f2FCMPNEZ_S:
- case CSKY::f2FCMPNEZ_D:
- case CSKY::f2FCMPUOZ_S:
- case CSKY::f2FCMPUOZ_D:
-
- case CSKY::BT32:
- case CSKY::BF32:
- case CSKY::BT16:
- case CSKY::BF16:
- case CSKY::CMPNEI32:
- case CSKY::CMPNEI16:
- case CSKY::CMPNE32:
- case CSKY::CMPNE16:
- case CSKY::CMPHSI32:
- case CSKY::CMPHSI16:
- case CSKY::CMPHS32:
- case CSKY::CMPHS16:
- case CSKY::CMPLTI32:
- case CSKY::CMPLTI16:
- case CSKY::CMPLT32:
- case CSKY::CMPLT16:
- case CSKY::BTSTI32:
- case CSKY::BTSTI16:
- case CSKY::TSTNBZ32:
- case CSKY::TSTNBZ16:
- case CSKY::TST32:
- case CSKY::TST16:
- MI.insert(MI.begin(), MCOperand::createReg(CSKY::C));
- return MCDisassembler::Success;
- case CSKY::LSLC32:
- case CSKY::LSRC32:
- case CSKY::ASRC32:
- MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
- return MCDisassembler::Success;
- case CSKY::MOVF32:
- case CSKY::MOVT32:
- case CSKY::MVC32:
- case CSKY::MVCV32:
- case CSKY::MVCV16:
- case CSKY::INCT32:
- case CSKY::INCF32:
- case CSKY::DECT32:
- case CSKY::DECF32:
- case CSKY::DECGT32:
- case CSKY::DECLT32:
- case CSKY::DECNE32:
- case CSKY::CLRF32:
- case CSKY::CLRT32:
- case CSKY::f2FSEL_S:
- case CSKY::f2FSEL_D:
- MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
- return MCDisassembler::Success;
- case CSKY::ADDC32:
- case CSKY::ADDC16:
- case CSKY::SUBC32:
- case CSKY::SUBC16:
- case CSKY::XSR32:
- MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
- MI.insert(MI.end(), MCOperand::createReg(CSKY::C));
- return MCDisassembler::Success;
- case CSKY::INS32:
- MI.getOperand(3).setImm(MI.getOperand(3).getImm() +
- MI.getOperand(4).getImm());
- return MCDisassembler::Success;
- }
-}
-
static bool decodeFPUV3Instruction(MCInst &MI, uint32_t insn, uint64_t Address,
const MCDisassembler *DisAsm,
const MCSubtargetInfo &STI) {
@@ -548,7 +431,10 @@ DecodeStatus CSKYDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Size = 2;
}
- handleCROperand(MI);
+ if (MI.getOpcode() == CSKY::INS32) {
+ MI.getOperand(3).setImm(MI.getOperand(3).getImm() +
+ MI.getOperand(4).getImm());
+ }
return Result;
}
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