[llvm] d4450bb - [AArch64][GlobalISel] Move special selection for aarch64_crypto_sha1h.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 7 05:45:07 PDT 2025
Author: David Green
Date: 2025-09-07T13:45:00+01:00
New Revision: d4450bb8ece5f4d14c23a86556340c54d55b02b5
URL: https://github.com/llvm/llvm-project/commit/d4450bb8ece5f4d14c23a86556340c54d55b02b5
DIFF: https://github.com/llvm/llvm-project/commit/d4450bb8ece5f4d14c23a86556340c54d55b02b5.diff
LOG: [AArch64][GlobalISel] Move special selection for aarch64_crypto_sha1h.
This appears to just need to select FPR registers.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
llvm/test/CodeGen/AArch64/arm64-crypto.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 0bceb322726d1..5748556d07285 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -6608,45 +6608,6 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
switch (IntrinID) {
default:
break;
- case Intrinsic::aarch64_crypto_sha1h: {
- Register DstReg = I.getOperand(0).getReg();
- Register SrcReg = I.getOperand(2).getReg();
-
- // FIXME: Should this be an assert?
- if (MRI.getType(DstReg).getSizeInBits() != 32 ||
- MRI.getType(SrcReg).getSizeInBits() != 32)
- return false;
-
- // The operation has to happen on FPRs. Set up some new FPR registers for
- // the source and destination if they are on GPRs.
- if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {
- SrcReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
- MIB.buildCopy({SrcReg}, {I.getOperand(2)});
-
- // Make sure the copy ends up getting constrained properly.
- RBI.constrainGenericRegister(I.getOperand(2).getReg(),
- AArch64::GPR32RegClass, MRI);
- }
-
- if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID)
- DstReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
-
- // Actually insert the instruction.
- auto SHA1Inst = MIB.buildInstr(AArch64::SHA1Hrr, {DstReg}, {SrcReg});
- constrainSelectedInstRegOperands(*SHA1Inst, TII, TRI, RBI);
-
- // Did we create a new register for the destination?
- if (DstReg != I.getOperand(0).getReg()) {
- // Yep. Copy the result of the instruction back into the original
- // destination.
- MIB.buildCopy({I.getOperand(0)}, {DstReg});
- RBI.constrainGenericRegister(I.getOperand(0).getReg(),
- AArch64::GPR32RegClass, MRI);
- }
-
- I.eraseFromParent();
- return true;
- }
case Intrinsic::ptrauth_resign: {
Register DstReg = I.getOperand(0).getReg();
Register ValReg = I.getOperand(2).getReg();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index cf391c446a955..eecb502e18515 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -482,6 +482,7 @@ static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
case Intrinsic::aarch64_neon_sqrdmulh:
case Intrinsic::aarch64_neon_sqadd:
case Intrinsic::aarch64_neon_sqsub:
+ case Intrinsic::aarch64_crypto_sha1h:
return true;
case Intrinsic::aarch64_neon_saddlv: {
const LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
diff --git a/llvm/test/CodeGen/AArch64/arm64-crypto.ll b/llvm/test/CodeGen/AArch64/arm64-crypto.ll
index 1def7588e7bde..dc5263352aab5 100644
--- a/llvm/test/CodeGen/AArch64/arm64-crypto.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-crypto.ll
@@ -1,5 +1,11 @@
-; RUN: llc -mtriple=arm64-eabi -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s
-; RUN: llc -mtriple=arm64-eabi -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mattr=crypto -aarch64-neon-syntax=apple -o - %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=arm64-eabi -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=arm64-eabi -mattr=crypto -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 -o - %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for test_sha1c
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sha1c_in_a_row
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sha1p
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sha1m
declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
@@ -8,28 +14,36 @@ declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
define <16 x i8> @test_aese(<16 x i8> %data, <16 x i8> %key) {
; CHECK-LABEL: test_aese:
-; CHECK: aese.16b v0, v1
+; CHECK: // %bb.0:
+; CHECK-NEXT: aese.16b v0, v1
+; CHECK-NEXT: ret
%res = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
ret <16 x i8> %res
}
define <16 x i8> @test_aesd(<16 x i8> %data, <16 x i8> %key) {
; CHECK-LABEL: test_aesd:
-; CHECK: aesd.16b v0, v1
+; CHECK: // %bb.0:
+; CHECK-NEXT: aesd.16b v0, v1
+; CHECK-NEXT: ret
%res = call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
ret <16 x i8> %res
}
define <16 x i8> @test_aesmc(<16 x i8> %data) {
; CHECK-LABEL: test_aesmc:
-; CHECK: aesmc.16b v0, v0
+; CHECK: // %bb.0:
+; CHECK-NEXT: aesmc.16b v0, v0
+; CHECK-NEXT: ret
%res = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data)
ret <16 x i8> %res
}
define <16 x i8> @test_aesimc(<16 x i8> %data) {
; CHECK-LABEL: test_aesimc:
-; CHECK: aesimc.16b v0, v0
+; CHECK: // %bb.0:
+; CHECK-NEXT: aesimc.16b v0, v0
+; CHECK-NEXT: ret
%res = call <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
ret <16 x i8> %res
}
@@ -43,8 +57,10 @@ declare <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12
define <4 x i32> @test_sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
; CHECK-LABEL: test_sha1c:
-; CHECK: fmov [[HASH_E:s[0-9]+]], w0
-; CHECK: sha1c.4s q0, [[HASH_E]], v1
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w0
+; CHECK-NEXT: sha1c.4s q0, s2, v1
+; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
ret <4 x i32> %res
}
@@ -52,10 +68,12 @@ define <4 x i32> @test_sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
; <rdar://problem/14742333> Incomplete removal of unnecessary FMOV instructions in intrinsic SHA1
define <4 x i32> @test_sha1c_in_a_row(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
; CHECK-LABEL: test_sha1c_in_a_row:
-; CHECK: fmov [[HASH_E:s[0-9]+]], w0
-; CHECK: sha1c.4s q[[SHA1RES:[0-9]+]], [[HASH_E]], v1
-; CHECK-NOT: fmov
-; CHECK: sha1c.4s q0, s[[SHA1RES]], v1
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w0
+; CHECK-NEXT: mov.16b v3, v0
+; CHECK-NEXT: sha1c.4s q3, s2, v1
+; CHECK-NEXT: sha1c.4s q0, s3, v1
+; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
%extract = extractelement <4 x i32> %res, i32 0
%res2 = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %extract, <4 x i32> %wk)
@@ -64,40 +82,49 @@ define <4 x i32> @test_sha1c_in_a_row(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i3
define <4 x i32> @test_sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
; CHECK-LABEL: test_sha1p:
-; CHECK: fmov [[HASH_E:s[0-9]+]], w0
-; CHECK: sha1p.4s q0, [[HASH_E]], v1
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w0
+; CHECK-NEXT: sha1p.4s q0, s2, v1
+; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.aarch64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
ret <4 x i32> %res
}
define <4 x i32> @test_sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
; CHECK-LABEL: test_sha1m:
-; CHECK: fmov [[HASH_E:s[0-9]+]], w0
-; CHECK: sha1m.4s q0, [[HASH_E]], v1
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w0
+; CHECK-NEXT: sha1m.4s q0, s2, v1
+; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.aarch64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
ret <4 x i32> %res
}
-; FALLBACK-NOT: remark{{.*}}test_sha1h
define i32 @test_sha1h(i32 %hash_e) {
; CHECK-LABEL: test_sha1h:
-; CHECK: fmov [[HASH_E:s[0-9]+]], w0
-; CHECK: sha1h [[RES:s[0-9]+]], [[HASH_E]]
-; CHECK: fmov w0, [[RES]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: sha1h s0, s0
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: ret
%res = call i32 @llvm.aarch64.crypto.sha1h(i32 %hash_e)
ret i32 %res
}
define <4 x i32> @test_sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11) {
; CHECK-LABEL: test_sha1su0:
-; CHECK: sha1su0.4s v0, v1, v2
+; CHECK: // %bb.0:
+; CHECK-NEXT: sha1su0.4s v0, v1, v2
+; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.aarch64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
ret <4 x i32> %res
}
define <4 x i32> @test_sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15) {
; CHECK-LABEL: test_sha1su1:
-; CHECK: sha1su1.4s v0, v1
+; CHECK: // %bb.0:
+; CHECK-NEXT: sha1su1.4s v0, v1
+; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
ret <4 x i32> %res
}
@@ -109,14 +136,18 @@ declare <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_
define <4 x i32> @test_sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
; CHECK-LABEL: test_sha256h:
-; CHECK: sha256h.4s q0, q1, v2
+; CHECK: // %bb.0:
+; CHECK-NEXT: sha256h.4s q0, q1, v2
+; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.aarch64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
ret <4 x i32> %res
}
define <4 x i32> @test_sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) {
; CHECK-LABEL: test_sha256h2:
-; CHECK: sha256h2.4s q0, q1, v2
+; CHECK: // %bb.0:
+; CHECK-NEXT: sha256h2.4s q0, q1, v2
+; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.aarch64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
ret <4 x i32> %res
@@ -124,14 +155,21 @@ define <4 x i32> @test_sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x
define <4 x i32> @test_sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7) {
; CHECK-LABEL: test_sha256su0:
-; CHECK: sha256su0.4s v0, v1
+; CHECK: // %bb.0:
+; CHECK-NEXT: sha256su0.4s v0, v1
+; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.aarch64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
ret <4 x i32> %res
}
define <4 x i32> @test_sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
; CHECK-LABEL: test_sha256su1:
-; CHECK: sha256su1.4s v0, v1, v2
+; CHECK: // %bb.0:
+; CHECK-NEXT: sha256su1.4s v0, v1, v2
+; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
ret <4 x i32> %res
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
+; CHECK-SD: {{.*}}
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