[llvm] [GlobalISel] Add computeNumSignBits for SHL (PR #152067)
Yi-Chi Lee via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 6 08:51:36 PDT 2025
https://github.com/yichi170 updated https://github.com/llvm/llvm-project/pull/152067
>From a7dcbc9edc37396c4108580055778486a2947beb Mon Sep 17 00:00:00 2001
From: Yi-Chi Lee <yichi170 at gmail.com>
Date: Mon, 4 Aug 2025 14:01:20 -0500
Subject: [PATCH 1/3] [GlobalISel] Add computeNumSignBits for SHL
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 33 ++++++
.../AArch64/GlobalISel/knownbits-shl.mir | 110 ++++++++++++++++++
2 files changed, 143 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 974fc40de6222..b27aa475e13d4 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -1892,6 +1892,38 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
FirstAnswer = std::min<uint64_t>(FirstAnswer + *C, TyBits);
break;
}
+ case TargetOpcode::G_SHL: {
+ Register Src1 = MI.getOperand(1).getReg();
+ Register Src2 = MI.getOperand(2).getReg();
+ if (std::optional<ConstantRange> ShAmtRange =
+ getValidShiftAmountRange(Src2, DemandedElts, Depth + 1)) {
+ uint64_t MaxShAmt = ShAmtRange->getUnsignedMax().getZExtValue();
+ uint64_t MinShAmt = ShAmtRange->getUnsignedMin().getZExtValue();
+
+ MachineInstr &ExtMI = *MRI.getVRegDef(Src1);
+ unsigned ExtOpc = ExtMI.getOpcode();
+
+ if (ExtOpc == TargetOpcode::G_SEXT || ExtOpc == TargetOpcode::G_ZEXT ||
+ ExtOpc == TargetOpcode::G_ANYEXT) {
+ LLT ExtTy = MRI.getType(Src1);
+ Register Extendee = ExtMI.getOperand(1).getReg();
+ LLT ExtendeeTy = MRI.getType(Extendee);
+ uint64_t SizeDiff =
+ ExtTy.getScalarSizeInBits() - ExtendeeTy.getScalarSizeInBits();
+
+ if (SizeDiff <= MinShAmt) {
+ unsigned Tmp =
+ SizeDiff + computeNumSignBits(Extendee, DemandedElts, Depth + 1);
+ if (MaxShAmt < Tmp)
+ return Tmp - MaxShAmt;
+ }
+ }
+ unsigned Tmp = computeNumSignBits(Src1, DemandedElts, Depth + 1);
+ if (MaxShAmt < Tmp)
+ return Tmp - MaxShAmt;
+ }
+ break;
+ }
case TargetOpcode::G_TRUNC: {
Register Src = MI.getOperand(1).getReg();
LLT SrcTy = MRI.getType(Src);
@@ -2051,6 +2083,7 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
// Okay, we know that the sign bit in Mask is set. Use CLO to determine
// the number of identical bits in the top of the input value.
Mask <<= Mask.getBitWidth() - TyBits;
+ LLVM_DEBUG(dbgs() << "Mask.countl_one(): " << Mask.countl_one() << "\n");
return std::max(FirstAnswer, Mask.countl_one());
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
new file mode 100644
index 0000000000000..9e9c1413259fa
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
@@ -0,0 +1,110 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -o - 2>&1 | FileCheck %s
+
+---
+name: Cst
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @Cst
+ ; CHECK-NEXT: %0:_ KnownBits:11100000 SignBits:3
+ ; CHECK-NEXT: %1:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %2:_ KnownBits:10000000 SignBits:1
+ %0:_(s8) = G_CONSTANT i8 224
+ %1:_(s8) = G_CONSTANT i8 2
+ %2:_(s8) = G_SHL %0, %1
+...
+---
+name: CstBig
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstBig
+ ; CHECK-NEXT: %0:_ KnownBits:11111001 SignBits:5
+ ; CHECK-NEXT: %1:_ KnownBits:00000110 SignBits:5
+ ; CHECK-NEXT: %2:_ KnownBits:01000000 SignBits:1
+ %0:_(s8) = G_CONSTANT i8 249
+ %1:_(s8) = G_CONSTANT i8 6
+ %2:_(s8) = G_SHL %0, %1
+...
+---
+name: ScalarVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = COPY $b1
+ %2:_(s8) = G_SHL %0, %1
+...
+---
+name: ScalarCst
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarCst
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
+ ; CHECK-NEXT: %2:_ KnownBits:?????000 SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = G_CONSTANT i8 3
+ %2:_(s8) = G_SHL %0, %1
+...
+---
+name: VectorVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = G_SHL %0, %1
+...
+---
+name: VectorCst
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:?????????????000 SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(s16) = G_CONSTANT i16 3
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %3:_(<4 x s16>) = G_SHL %0, %2
+...
+---
+name: VectorCst36
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst36
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000110 SignBits:13
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %4:_ KnownBits:000000????????00 SignBits:7
+ %0:_(s16) = G_CONSTANT i16 3
+ %1:_(s16) = G_CONSTANT i16 6
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %4:_(<4 x s16>) = G_SHL %2, %3
+...
+
+---
+name: VectorCst3unknown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst3unknown
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %2:_(s16) = COPY $h0
+ %1:_(s16) = G_CONSTANT i16 3
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %2, %2, %1
+ %4:_(<4 x s16>) = G_SHL %0, %3
+...
>From 16f468872a85ec79acd8502541f1d06bbfa55383 Mon Sep 17 00:00:00 2001
From: yichi170 <yichi170 at gmail.com>
Date: Tue, 5 Aug 2025 21:44:38 -0500
Subject: [PATCH 2/3] Update test and comment
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 7 +-
.../AArch64/GlobalISel/knownbits-shl.mir | 72 +++++++++++++++++++
2 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index b27aa475e13d4..0cf44e02254de 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -1903,6 +1903,11 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
MachineInstr &ExtMI = *MRI.getVRegDef(Src1);
unsigned ExtOpc = ExtMI.getOpcode();
+ // Try to look through ZERO/SIGN/ANY_EXTEND. If all extended bits are
+ // shifted out, then we can compute the number of sign bits for the
+ // operand being extended. A future improvement could be to pass along the
+ // "shifted left by" information in the recursive calls to
+ // ComputeKnownSignBits. Allowing us to handle this more generically.
if (ExtOpc == TargetOpcode::G_SEXT || ExtOpc == TargetOpcode::G_ZEXT ||
ExtOpc == TargetOpcode::G_ANYEXT) {
LLT ExtTy = MRI.getType(Src1);
@@ -1918,6 +1923,7 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
return Tmp - MaxShAmt;
}
}
+ // shl destroys sign bits, ensure it doesn't shift out all sign bits.
unsigned Tmp = computeNumSignBits(Src1, DemandedElts, Depth + 1);
if (MaxShAmt < Tmp)
return Tmp - MaxShAmt;
@@ -2083,7 +2089,6 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
// Okay, we know that the sign bit in Mask is set. Use CLO to determine
// the number of identical bits in the top of the input value.
Mask <<= Mask.getBitWidth() - TyBits;
- LLVM_DEBUG(dbgs() << "Mask.countl_one(): " << Mask.countl_one() << "\n");
return std::max(FirstAnswer, Mask.countl_one());
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
index 9e9c1413259fa..a98fca9620945 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
@@ -26,6 +26,38 @@ body: |
%2:_(s8) = G_SHL %0, %1
...
---
+name: CstSext
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstSext
+ ; CHECK-NEXT: %0:_ KnownBits:10000001 SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
+ ; CHECK-NEXT: %2:_ KnownBits:11111000 SignBits:5
+ ; CHECK-NEXT: %3:_ KnownBits:00000011 SignBits:6
+ ; CHECK-NEXT: %4:_ KnownBits:11000000 SignBits:2
+ %0:_(s8) = G_CONSTANT i8 129
+ %1:_(s8) = G_CONSTANT i8 4
+ %2:_(s8) = G_ASHR %0, %1
+ %3:_(s8) = G_CONSTANT i8 3
+ %4:_(s8) = G_SHL %2, %3
+...
+---
+name: CstSextBig
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstSextBig
+ ; CHECK-NEXT: %0:_ KnownBits:10000001 SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
+ ; CHECK-NEXT: %2:_ KnownBits:11111000 SignBits:5
+ ; CHECK-NEXT: %3:_ KnownBits:00000110 SignBits:5
+ ; CHECK-NEXT: %4:_ KnownBits:00000000 SignBits:8
+ %0:_(s8) = G_CONSTANT i8 129
+ %1:_(s8) = G_CONSTANT i8 4
+ %2:_(s8) = G_ASHR %0, %1
+ %3:_(s8) = G_CONSTANT i8 6
+ %4:_(s8) = G_SHL %2, %3
+...
+---
name: ScalarVar
body: |
bb.1:
@@ -108,3 +140,43 @@ body: |
%3:_(<4 x s16>) = G_BUILD_VECTOR %1, %2, %2, %1
%4:_(<4 x s16>) = G_SHL %0, %3
...
+---
+name: VectorSext
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorSext
+ ; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3
+ ; CHECK-NEXT: %1:_ KnownBits:1111111111101110 SignBits:11
+ ; CHECK-NEXT: %2:_ KnownBits:1111111111101110 SignBits:11
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000000110 SignBits:13
+ ; CHECK-NEXT: %5:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %6:_ KnownBits:1111??11?????000 SignBits:5
+ %0:_(s8) = G_CONSTANT i8 238
+ %1:_(s16) = G_SEXT %0(s8)
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %3:_(s16) = G_CONSTANT i16 3
+ %4:_(s16) = G_CONSTANT i16 6
+ %5:_(<4 x s16>) = G_BUILD_VECTOR %3, %4, %4, %3
+ %6:_(<4 x s16>) = G_SHL %2, %5
+...
+---
+name: VectorSextBig
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorSextBig
+ ; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3
+ ; CHECK-NEXT: %1:_ KnownBits:1111111111101110 SignBits:11
+ ; CHECK-NEXT: %2:_ KnownBits:1111111111101110 SignBits:11
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000001000 SignBits:12
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000001001 SignBits:12
+ ; CHECK-NEXT: %5:_ KnownBits:000000000000100? SignBits:12
+ ; CHECK-NEXT: %6:_ KnownBits:11??11?000000000 SignBits:2
+ %0:_(s8) = G_CONSTANT i8 238
+ %1:_(s16) = G_SEXT %0(s8)
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %3:_(s16) = G_CONSTANT i16 8
+ %4:_(s16) = G_CONSTANT i16 9
+ %5:_(<4 x s16>) = G_BUILD_VECTOR %3, %4, %4, %3
+ %6:_(<4 x s16>) = G_SHL %2, %5
+...
>From 1cd9f89df1f8868dda1558ab526496b5f3868124 Mon Sep 17 00:00:00 2001
From: yichi170 <yichi170 at gmail.com>
Date: Sat, 6 Sep 2025 10:51:08 -0500
Subject: [PATCH 3/3] Update testcases
---
.../AArch64/GlobalISel/knownbits-shl.mir | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
index a98fca9620945..61d1c4375bd6e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
@@ -180,3 +180,63 @@ body: |
%5:_(<4 x s16>) = G_BUILD_VECTOR %3, %4, %4, %3
%6:_(<4 x s16>) = G_SHL %2, %5
...
+---
+name: SHLless
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @SHLless
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:?????????????000 SignBits:6
+ %0:_(s8) = COPY $b0
+ %1:_(s16) = G_SEXT %0(s8)
+ %2:_(s16) = G_CONSTANT i16 3
+ %3:_(s16) = G_SHL %1, %2
+...
+---
+name: SHLeq
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @SHLeq
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000001000 SignBits:12
+ ; CHECK-NEXT: %3:_ KnownBits:????????00000000 SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s16) = G_SEXT %0(s8)
+ %2:_(s16) = G_CONSTANT i16 8
+ %3:_(s16) = G_SHL %1, %2
+...
+---
+name: SHLmore
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @SHLmore
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000001101 SignBits:12
+ ; CHECK-NEXT: %3:_ KnownBits:???0000000000000 SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s16) = G_SEXT %0(s8)
+ %2:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_SHL %1, %2
+...
+---
+name: SignBitsThroughZext
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @SignBitsThroughZext
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:4
+ ; CHECK-NEXT: %3:_ KnownBits:00000000???????? SignBits:8
+ ; CHECK-NEXT: %4:_ KnownBits:0000000000001000 SignBits:12
+ ; CHECK-NEXT: %5:_ KnownBits:????????00000000 SignBits:4
+ %0:_(s8) = COPY $b0
+ %1:_(s16) = G_CONSTANT i16 3
+ %2:_(s8) = G_ASHR %0, %1
+ %3:_(s16) = G_ZEXT %2
+ %4:_(s16) = G_CONSTANT i16 8
+ %5:_(s16) = G_SHL %3, %4
+...
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