[llvm] [RISCV] Use C.ADD when OR is not compressible due to register restriction (PR #156044)

[Alex Bradbury via llvm-commits]

asb wrote:

> Note there is a small correctness risk with this change - if we forgot to drop the disioint flag somewhere this could cause miscompiles, and I don't think we have another use of the flag this late in the backend.

Just as a litmus test, I applied a modified version of this patch that unconditionally selects `add` when possible (i.e. without gating it just on the case where the extra compressibility is taken advantage of). For an rva22u64 build of the LLVM test suite including SPEC 2017 it results in 1907 conversions of or=>add and all tests still pass. 

Obviously this isn't a proof of the absence of any lurking issues, but at least we know that the obvious litmus test is fine.

https://github.com/llvm/llvm-project/pull/156044