[llvm] 667f919 - [SelectionDAG][ARM] Propagate fast math flags in visitBRCOND (#156647)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 6 05:44:29 PDT 2025
Author: paperchalice
Date: 2025-09-06T20:44:25+08:00
New Revision: 667f9192141f407fa22cad897b3564c0d120fedf
URL: https://github.com/llvm/llvm-project/commit/667f9192141f407fa22cad897b3564c0d120fedf
DIFF: https://github.com/llvm/llvm-project/commit/667f9192141f407fa22cad897b3564c0d120fedf.diff
LOG: [SelectionDAG][ARM] Propagate fast math flags in visitBRCOND (#156647)
Factor out from #151275.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/ARM/fpcmp-opt.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6310f7270ceaf..1ef2b35952833 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19364,13 +19364,13 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
// MachineBasicBlock CFG, which is awkward.
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
- // on the target.
+ // on the target, also copy fast math flags.
if (N1.getOpcode() == ISD::SETCC &&
TLI.isOperationLegalOrCustom(ISD::BR_CC,
N1.getOperand(0).getValueType())) {
- return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
- Chain, N1.getOperand(2),
- N1.getOperand(0), N1.getOperand(1), N2);
+ return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, Chain,
+ N1.getOperand(2), N1.getOperand(0), N1.getOperand(1), N2,
+ N1->getFlags());
}
if (N1.hasOneUse()) {
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 219e039f6c2c3..d4d3c70095279 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5570,7 +5570,7 @@ static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
llvm_unreachable("Unknown VFP cmp argument!");
}
-/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
+/// OptimizeVFPBrcond - With nnan, it's legal to optimize some
/// f32 and even f64 comparisons to integer ones.
SDValue
ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
@@ -5712,9 +5712,12 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, Cmp);
}
- if (getTargetMachine().Options.UnsafeFPMath &&
- (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
- CC == ISD::SETNE || CC == ISD::SETUNE)) {
+ SDNodeFlags Flags = Op->getFlags();
+ if ((getTargetMachine().Options.UnsafeFPMath || Flags.hasNoNaNs()) &&
+ (DAG.getDenormalMode(MVT::f32) == DenormalMode::getIEEE() &&
+ DAG.getDenormalMode(MVT::f64) == DenormalMode::getIEEE()) &&
+ (CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETNE ||
+ CC == ISD::SETUNE)) {
if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
return Result;
}
diff --git a/llvm/test/CodeGen/ARM/fpcmp-opt.ll b/llvm/test/CodeGen/ARM/fpcmp-opt.ll
index 447e470b2363a..a40fd4244af17 100644
--- a/llvm/test/CodeGen/ARM/fpcmp-opt.ll
+++ b/llvm/test/CodeGen/ARM/fpcmp-opt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math %s -o - \
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 %s -o - \
; RUN: | FileCheck %s
; rdar://7461510
@@ -42,7 +42,7 @@ entry:
; CHECK-NOT: vmrs
; CHECK: bne
%0 = load double, ptr %a
- %1 = fcmp oeq double %0, 0.000000e+00
+ %1 = fcmp nnan oeq double %0, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb1:
@@ -65,7 +65,7 @@ entry:
; CHECK-NOT: vmrs
; CHECK: bne
%0 = load float, ptr %a
- %1 = fcmp oeq float %0, 0.000000e+00
+ %1 = fcmp nnan oeq float %0, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb1:
More information about the llvm-commits
mailing list