[llvm] [AArch64] Fix vectorToScalarBitmask BE (#156312) (PR #156314)

[Giuseppe Cesarano via llvm-commits]

GiuseppeCesarano wrote:

> I see what you mean, but often they can be intertwined and if the codegen changes the lane masks should be changed to accommodate.

I see your point. I think both versions have their own issues. The current version relies on the correspondence between bits and lanes:

```
LE:
lane0 = bit0
lane1 = bit1
...

BE:
lane0 = bit(N-1)
lane1 = bit(N-2)
...
```

This correspondence holds today, but it is not explicitly checked.

I’ve seen other issues caused by this endianness differences, and in those cases the problem was fixed in the surrounding logic and not in the bit–lane mapping itself. For that reason I think this correspondence is unlikely to change, or at least such patch would require special care if it ever did.

If you have a suggestion for how to assert or verify this mapping, I’ll be happy to add it. Otherwise, I’m fine with the patch being merged as is.


https://github.com/llvm/llvm-project/pull/156314