[llvm] [TargetInstrInfo][AArch64] Don't assume register came from operand 0 in canCombine (PR #157210)

[Craig Topper via llvm-commits]

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/157210

>From 9579c500d3fe1f42751490f00fad17696b929f62 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 5 Sep 2025 17:16:52 -0700
Subject: [PATCH 1/2] [TargetInstrInfo][AArch64] Don't assume register came
 from operand 0 in canCombine

We already have the register number from the user operand. Use it
instead of assuming it must be operand 0 of the producing instruction.

Fixes #157118
---
 llvm/lib/CodeGen/TargetInstrInfo.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 7ba65f0418a6b..0d7b128fc736e 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -996,7 +996,7 @@ static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO,
       (MI->getOpcode() != CombineOpc && CombineOpc != 0))
     return false;
   // Must only used by the user we combine with.
-  if (!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
+  if (!MRI.hasOneNonDBGUse(MO.getReg()))
     return false;
 
   return true;

>From 34612950a757f2d7c175973843fb8ba1f9c7be3e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 5 Sep 2025 17:55:56 -0700
Subject: [PATCH 2/2] fixup! commit test case

---
 llvm/test/CodeGen/AArch64/pr157118.ll | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/pr157118.ll

diff --git a/llvm/test/CodeGen/AArch64/pr157118.ll b/llvm/test/CodeGen/AArch64/pr157118.ll
new file mode 100644
index 0000000000000..cdef46fe8f227
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr157118.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+
+define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) {
+; CHECK-LABEL: test_vaba_u8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    //APP
+; CHECK-NEXT:    //NO_APP
+; CHECK-NEXT:    uaba v0.8b, v1.8b, v2.8b
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call <8 x i8> asm sideeffect "", "=w,0"(<8 x i8> %a)
+  %vabd.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %b, <8 x i8> %c)
+  %add.i = add <8 x i8> %vabd.i, %0
+  ret <8 x i8> %add.i
+}