[llvm] [RISCV] Check for legal type before calling getSimpleValueType() in matchSplatAsGather. (PR #157188)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/157188

This just reorders existing so we do the legal type check first.

In this particular test case we're also protected by the i1 check that I also moved earlier.

Fixes #157177.

>From e4245d4ca13c6e365465a5a501004086952e342b Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 5 Sep 2025 14:58:26 -0700
Subject: [PATCH] [RISCV] Check for legal type before calling
 getSimpleValueType() in matchSplatAsGather.

This just reorders existing so we do the legal type check first.

In this particular test case we're also protected by the i1 check
that I also moved earlier.

Fixes #157177.
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp |  6 ++++--
 llvm/test/CodeGen/RISCV/rvv/pr157177.ll     | 20 ++++++++++++++++++++
 2 files changed, 24 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/pr157177.ll

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 44434ff51288f..a27bd418a6b01 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3744,9 +3744,11 @@ static SDValue matchSplatAsGather(SDValue SplatVal, MVT VT, const SDLoc &DL,
   // different
   // FIXME: Support i1 vectors, maybe by promoting to i8?
   MVT EltTy = VT.getVectorElementType();
+  if (EltTy == MVT::i1 ||
+      !DAG.getTargetLoweringInfo().isTypeLegal(Src.getValueType()))
+    return SDValue();
   MVT SrcVT = Src.getSimpleValueType();
-  if (EltTy == MVT::i1 || EltTy != SrcVT.getVectorElementType() ||
-      !DAG.getTargetLoweringInfo().isTypeLegal(SrcVT))
+  if (EltTy != SrcVT.getVectorElementType())
     return SDValue();
   SDValue Idx = SplatVal.getOperand(1);
   // The index must be a legal type.
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr157177.ll b/llvm/test/CodeGen/RISCV/rvv/pr157177.ll
new file mode 100644
index 0000000000000..adf857f833a47
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/pr157177.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
+
+define <vscale x 8 x i1> @main(<120 x i1> %0) #0 {
+; CHECK-LABEL: main:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li a0, 128
+; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+entry:
+  %1 = extractelement <120 x i1> %0, i64 0
+  %2 = insertelement <vscale x 8 x i1> zeroinitializer, i1 %1, i64 0
+  %3 = shufflevector <vscale x 8 x i1> %2, <vscale x 8 x i1> zeroinitializer, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x i1> %3
+}