[llvm] [RISCV] Add SRAI to recursive part of isSignExtendedW. (PR #157164)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/157164

SRAI can only increase the number of sign bits. If the input has at least 33 sign bits, the result will to.

I don't have a test case for this currently. It was just an observation I made while thinking about the shifts and extracts.

>From 824d120b43cdcc9e91d4fd7f555536312f633b86 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 5 Sep 2025 12:14:47 -0700
Subject: [PATCH] [RISCV] Add SRAI to recursive part of isSignExtendedW.

SRAI can only increase the number of sign bits. If the input has
at least 33 sign bits, the result will to.

I don't have a test case for this currently. It was just an
observation I made while thinking about the shifts and extracts.
---
 llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 3b19c3456ad67..e86c49dabfd64 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -519,9 +519,11 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
     case RISCV::ANDI:
     case RISCV::ORI:
     case RISCV::XORI:
+    case RISCV::SRAI:
       // |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
       // DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
       // Logical operations use a sign extended 12-bit immediate.
+      // Arithmetic shift right can only increase the number of sign bits.
       if (!AddRegToWorkList(MI->getOperand(1).getReg()))
         return false;