[llvm] [AMDGPU] Add documentation files for GFX12. (PR #157151)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 5 10:53:22 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jun Wang (jwanggit86)
<details>
<summary>Changes</summary>
This patch adds documentation files for GFX12.
---
Patch is 526.24 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/157151.diff
130 Files Affected:
- (added) llvm/docs/AMDGPU/AMDGPUAsmGFX12.rst (+2002)
- (added) llvm/docs/AMDGPU/gfx12_addr.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_attr.rst (+28)
- (added) llvm/docs/AMDGPU/gfx12_clause.rst (+7)
- (added) llvm/docs/AMDGPU/gfx12_data0_56f215.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_data0_6802ce.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_data0_e016a1.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_data0_fd235e.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_data1_6802ce.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_data1_731030.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_data1_e016a1.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_data1_fd235e.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_delay.rst (+74)
- (added) llvm/docs/AMDGPU/gfx12_hwreg.rst (+76)
- (added) llvm/docs/AMDGPU/gfx12_imm16.rst (+7)
- (added) llvm/docs/AMDGPU/gfx12_ioffset.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_label.rst (+29)
- (added) llvm/docs/AMDGPU/gfx12_literal_1f74c7.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_literal_81e671.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_rsrc_5fe6d8.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_rsrc_c9f929.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_saddr_cdc95c.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_saddr_d42b64.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_samp.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_sbase_453b95.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sbase_47adb7.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdata_0974a4.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdata_354189.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdata_4585b8.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdata_5c7b50.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdata_6c003b.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdata_836716.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdata_d725ab.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdata_dd9dd8.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdst_006c40.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdst_20064d.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_sdst_354189.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdst_836716.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdst_ced58d.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sdst_e701cc.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_sendmsg.rst (+48)
- (added) llvm/docs/AMDGPU/gfx12_sendmsg_rtn.rst (+30)
- (added) llvm/docs/AMDGPU/gfx12_simm16_15ccdd.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_simm16_218bea.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_simm16_39b593.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_simm16_3d2a4f.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_simm16_730a13.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_simm16_7ed651.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_simm16_81e671.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_simm16_c98889.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_simm16_cc1716.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_simm16_ee8b30.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_soffset_8ec073.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_soffset_c5b88c.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_soffset_ec005a.rst (+20)
- (added) llvm/docs/AMDGPU/gfx12_src0_5727cf.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src0_5cae62.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src0_6802ce.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src0_85aab6.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src0_c4593f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src0_e016a1.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src0_fd235e.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src1_5727cf.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src1_5cae62.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src1_6802ce.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src1_731030.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src1_977794.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src1_c4593f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src1_e016a1.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src1_fd235e.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src2_2797bc.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src2_5727cf.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src2_5cae62.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src2_6802ce.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src2_7b936a.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src2_96fbd3.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src2_c4593f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_src2_e016a1.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_srcx0.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_srcy0.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_ssrc0_007f9c.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_ssrc0_1a9ca5.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_ssrc0_245536.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_ssrc0_2797bc.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_ssrc0_bbb4c6.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_ssrc0_c4593f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_ssrc1_bbb4c6.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_ssrc1_c4593f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_tgt.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vaddr_a972b9.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_vaddr_c12f43.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_vaddr_c8b8d4.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_vaddr_d82160.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_vaddr_f2b449.rst (+15)
- (added) llvm/docs/AMDGPU/gfx12_vcc.rst (+16)
- (added) llvm/docs/AMDGPU/gfx12_vdata_2eda77.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdata_48e42f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdata_69a144.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdata_89680f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdata_aac3e8.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdata_bdb32f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdst_006c40.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdst_227281.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdst_2eda77.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdst_47d3bc.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdst_48e42f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdst_69a144.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdst_7de8e7.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdst_836716.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdst_89680f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdst_bdb32f.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdstx.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vdsty.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_version.rst (+7)
- (added) llvm/docs/AMDGPU/gfx12_vsrc0.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrc1_6802ce.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrc1_fd235e.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrc2.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrc3.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrc_56f215.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrc_6802ce.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrc_89fd7b.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrc_e016a1.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrc_fd235e.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrcx1.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_vsrcy1.rst (+17)
- (added) llvm/docs/AMDGPU/gfx12_waitcnt.rst (+55)
- (modified) llvm/docs/AMDGPUModifierSyntax.rst (+109)
- (modified) llvm/docs/AMDGPUOperandSyntax.rst (+11)
- (modified) llvm/docs/AMDGPUUsage.rst (+1)
``````````diff
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX12.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX12.rst
new file mode 100644
index 0000000000000..d16914d09c106
--- /dev/null
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX12.rst
@@ -0,0 +1,2002 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+====================================================================================
+Syntax of GFX12 Instructions
+====================================================================================
+
+.. contents::
+ :local:
+
+Introduction
+============
+
+This document describes the syntax of GFX12 instructions.
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Overview
+========
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+SMEM
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_atc_probe :ref:`sdata<amdgpu_synid_gfx12_sdata_d725ab>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_atc_probe_buffer :ref:`sdata<amdgpu_synid_gfx12_sdata_d725ab>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_load_b128 :ref:`sdata<amdgpu_synid_gfx12_sdata_4585b8>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_load_b256 :ref:`sdata<amdgpu_synid_gfx12_sdata_0974a4>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_load_b32 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_load_b512 :ref:`sdata<amdgpu_synid_gfx12_sdata_6c003b>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_load_b64 :ref:`sdata<amdgpu_synid_gfx12_sdata_354189>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_load_b96 :ref:`sdata<amdgpu_synid_gfx12_sdata_dd9dd8>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_load_i16 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_load_i8 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_load_u16 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_load_u8 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_nop :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_buffer_prefetch_data :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`, :ref:`ioffset<amdgpu_synid_gfx12_ioffset>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`, :ref:`sdata<amdgpu_synid_gfx12_sdata_5c7b50>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_dcache_inv :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_load_b128 :ref:`sdata<amdgpu_synid_gfx12_sdata_4585b8>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_load_b256 :ref:`sdata<amdgpu_synid_gfx12_sdata_0974a4>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_load_b32 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_load_b512 :ref:`sdata<amdgpu_synid_gfx12_sdata_6c003b>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_load_b64 :ref:`sdata<amdgpu_synid_gfx12_sdata_354189>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_load_b96 :ref:`sdata<amdgpu_synid_gfx12_sdata_dd9dd8>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_load_i16 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_load_i8 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_load_u16 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_load_u8 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`, :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_prefetch_data :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`ioffset<amdgpu_synid_gfx12_ioffset>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`, :ref:`sdata<amdgpu_synid_gfx12_sdata_5c7b50>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_prefetch_data_pc_rel :ref:`ioffset<amdgpu_synid_gfx12_ioffset>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`, :ref:`sdata<amdgpu_synid_gfx12_sdata_5c7b50>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_prefetch_inst :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`, :ref:`ioffset<amdgpu_synid_gfx12_ioffset>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`, :ref:`sdata<amdgpu_synid_gfx12_sdata_5c7b50>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+ s_prefetch_inst_pc_rel :ref:`ioffset<amdgpu_synid_gfx12_ioffset>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`, :ref:`sdata<amdgpu_synid_gfx12_sdata_5c7b50>` :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+
+SOP1
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs_i32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_alloc_vgpr :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_and_not0_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_and_not0_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_and_not0_wrexec_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_and_not0_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_and_not1_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_and_not1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_and_not1_wrexec_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_and_not1_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_and_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_and_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_barrier_init :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+ s_barrier_join :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+ s_barrier_signal :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+ s_barrier_signal_isfirst :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+ s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_bitset0_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_bitset0_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_bitset1_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_bitset1_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_brev_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_brev_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_ceil_f16 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_ceil_f32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_cls_i32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_cls_i32_i64 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_clz_i32_u32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_clz_i32_u64 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_cmov_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_cmov_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_ctz_i32_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_ctz_i32_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_cvt_f16_f32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_cvt_f32_f16 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_cvt_f32_i32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_cvt_f32_u32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_cvt_hi_f32_f16 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_cvt_i32_f32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_cvt_u32_f32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_floor_f16 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_floor_f32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_get_barrier_state :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+ s_get_lock_state :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+ s_getpc_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`
+ s_mov_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_mov_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_mov_fed_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_mov_from_global_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_007f9c>`
+ s_mov_from_global_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_2797bc>`
+ s_mov_regrd_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_mov_to_global_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_mov_to_global_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_movreld_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_movreld_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_movrels_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_007f9c>`
+ s_movrels_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_2797bc>`
+ s_movrelsd_2_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_007f9c>`
+ s_nand_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_nor_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+ s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`, :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+ s_no...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/157151
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