[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[via llvm-commits]

================
@@ -4069,6 +4069,74 @@ SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
 }
 
----------------
LU-JOHN wrote:

Instead of calling getShiftForReduction in each shift combine function, consider adding a new performExtractVectorElementCombine function that transforms:

`(extract_vector_element (and {y0, y1},  (build_vector 0x1f, 0x1f)), index)`

to:

`(and (extract_vector_element {y0, y1}, index), 0x1f)`

Perhaps this could be generalized to other bitwise operations, other constants, and other vector lengths.

https://github.com/llvm/llvm-project/pull/140694