[llvm] eb623e6 - [RISCV][GISel] Lower G_ABDS and G_ABDU (#155888)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 5 06:16:39 PDT 2025
Author: Shaoce SUN
Date: 2025-09-05T21:16:35+08:00
New Revision: eb623e650b64a4994a6d47f402b049157f26a4d4
URL: https://github.com/llvm/llvm-project/commit/eb623e650b64a4994a6d47f402b049157f26a4d4
DIFF: https://github.com/llvm/llvm-project/commit/eb623e650b64a4994a6d47f402b049157f26a4d4.diff
LOG: [RISCV][GISel] Lower G_ABDS and G_ABDU (#155888)
Implementation follows the `ISD::ABDS` handling in
`RISCVTargetLowering`.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir
Modified:
llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
index aef7891af8f93..3be4f82d11bbf 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -522,6 +522,8 @@ class LegalizerHelper {
LLVM_ABI LegalizeResult lowerAbsToAddXor(MachineInstr &MI);
LLVM_ABI LegalizeResult lowerAbsToMaxNeg(MachineInstr &MI);
LLVM_ABI LegalizeResult lowerAbsToCNeg(MachineInstr &MI);
+ LLVM_ABI LegalizeResult lowerAbsDiffToSelect(MachineInstr &MI);
+ LLVM_ABI LegalizeResult lowerAbsDiffToMinMax(MachineInstr &MI);
LLVM_ABI LegalizeResult lowerFAbs(MachineInstr &MI);
LLVM_ABI LegalizeResult lowerVectorReduction(MachineInstr &MI);
LLVM_ABI LegalizeResult lowerMemcpyInline(MachineInstr &MI);
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 40e6b1bf81bd0..a38d305a8bb52 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -4742,6 +4742,16 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerShlSat(MI);
case G_ABS:
return lowerAbsToAddXor(MI);
+ case G_ABDS:
+ case G_ABDU: {
+ bool IsSigned = MI.getOpcode() == G_ABDS;
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+ if ((IsSigned && LI.isLegal({G_SMIN, Ty}) && LI.isLegal({G_SMAX, Ty})) ||
+ (!IsSigned && LI.isLegal({G_UMIN, Ty}) && LI.isLegal({G_UMAX, Ty}))) {
+ return lowerAbsDiffToMinMax(MI);
+ }
+ return lowerAbsDiffToSelect(MI);
+ }
case G_FABS:
return lowerFAbs(MI);
case G_SELECT:
@@ -9925,6 +9935,54 @@ LegalizerHelper::lowerAbsToCNeg(MachineInstr &MI) {
return Legalized;
}
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerAbsDiffToSelect(MachineInstr &MI) {
+ assert((MI.getOpcode() == TargetOpcode::G_ABDS ||
+ MI.getOpcode() == TargetOpcode::G_ABDU) &&
+ "Expected G_ABDS or G_ABDU instruction");
+
+ auto [DstReg, LHS, RHS] = MI.getFirst3Regs();
+ LLT Ty = MRI.getType(LHS);
+
+ // abds(lhs, rhs) -> select(sgt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
+ // abdu(lhs, rhs) -> select(ugt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
+ Register LHSSub = MIRBuilder.buildSub(Ty, LHS, RHS).getReg(0);
+ Register RHSSub = MIRBuilder.buildSub(Ty, RHS, LHS).getReg(0);
+ CmpInst::Predicate Pred = (MI.getOpcode() == TargetOpcode::G_ABDS)
+ ? CmpInst::ICMP_SGT
+ : CmpInst::ICMP_UGT;
+ auto ICmp = MIRBuilder.buildICmp(Pred, LLT::scalar(1), LHS, RHS);
+ MIRBuilder.buildSelect(DstReg, ICmp, LHSSub, RHSSub);
+
+ MI.eraseFromParent();
+ return Legalized;
+}
+
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerAbsDiffToMinMax(MachineInstr &MI) {
+ assert((MI.getOpcode() == TargetOpcode::G_ABDS ||
+ MI.getOpcode() == TargetOpcode::G_ABDU) &&
+ "Expected G_ABDS or G_ABDU instruction");
+
+ auto [DstReg, LHS, RHS] = MI.getFirst3Regs();
+ LLT Ty = MRI.getType(LHS);
+
+ // abds(lhs, rhs) -→ sub(smax(lhs, rhs), smin(lhs, rhs))
+ // abdu(lhs, rhs) -→ sub(umax(lhs, rhs), umin(lhs, rhs))
+ Register MaxReg, MinReg;
+ if (MI.getOpcode() == TargetOpcode::G_ABDS) {
+ MaxReg = MIRBuilder.buildSMax(Ty, LHS, RHS).getReg(0);
+ MinReg = MIRBuilder.buildSMin(Ty, LHS, RHS).getReg(0);
+ } else {
+ MaxReg = MIRBuilder.buildUMax(Ty, LHS, RHS).getReg(0);
+ MinReg = MIRBuilder.buildUMin(Ty, LHS, RHS).getReg(0);
+ }
+ MIRBuilder.buildSub(DstReg, MaxReg, MinReg);
+
+ MI.eraseFromParent();
+ return Legalized;
+}
+
LegalizerHelper::LegalizeResult LegalizerHelper::lowerFAbs(MachineInstr &MI) {
Register SrcReg = MI.getOperand(1).getReg();
Register DstReg = MI.getOperand(0).getReg();
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index d908e5f482e2b..ab5c9e17b9a37 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -488,6 +488,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
.lower();
+ getActionDefinitionsBuilder({G_ABDS, G_ABDU}).lower();
+
getActionDefinitionsBuilder({G_UMAX, G_UMIN, G_SMAX, G_SMIN})
.legalFor(ST.hasStdExtZbb(), {sXLen})
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index 8edc7e4f8b57c..562adbd2ce3a7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -73,12 +73,13 @@
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_ABDS (opcode 65): 1 type index, 0 imm indices
-# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT:.. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT:.. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT:G_ABDU (opcode 66): 1 type index, 0 imm indices
-# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT:.. opcode 66 is aliased to 65
+# DEBUG-NEXT:.. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT:.. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_IMPLICIT_DEF (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-
diff -rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-
diff -rv32.mir
new file mode 100644
index 0000000000000..7a9b25218a352
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-
diff -rv32.mir
@@ -0,0 +1,264 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB
+
+---
+name: abds_i8
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: abds_i8
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
+ ; CHECK-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
+ ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %3:_(s32) = G_ASSERT_SEXT %1, 8
+ %4:_(s32) = G_ASSERT_SEXT %2, 8
+ %5:_(s8) = G_TRUNC %3(s32)
+ %6:_(s8) = G_TRUNC %4(s32)
+ %7:_(s8) = G_ABDS %5, %6
+ %8:_(s32) = G_ANYEXT %7(s8)
+ $x10 = COPY %8(s32)
+ PseudoRET implicit $x10
+...
+---
+name: abds_i16
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: abds_i16
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
+ ; CHECK-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 16
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
+ ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %3:_(s32) = G_ASSERT_SEXT %1, 16
+ %4:_(s32) = G_ASSERT_SEXT %2, 16
+ %5:_(s16) = G_TRUNC %3(s32)
+ %6:_(s16) = G_TRUNC %4(s32)
+ %7:_(s16) = G_ABDS %5, %6
+ %8:_(s32) = G_ANYEXT %7(s16)
+ $x10 = COPY %8(s32)
+ PseudoRET implicit $x10
+...
+---
+name: abds_i32
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; RV32I-LABEL: name: abds_i32
+ ; RV32I: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+ ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
+ ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
+ ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32ZBB-LABEL: name: abds_i32
+ ; RV32ZBB: liveins: $x10, $x11
+ ; RV32ZBB-NEXT: {{ $}}
+ ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[COPY1]]
+ ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]]
+ ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]
+ ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
+ ; RV32ZBB-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %3:_(s32) = G_ABDS %1, %2
+ $x10 = COPY %3(s32)
+ PseudoRET implicit $x10
+...
+---
+name: abds_i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: abds_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
+ ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[COPY]]
+ ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]]
+ ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[ICMP1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP2]], [[ICMP3]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB]], [[SUB3]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB2]], [[SUB5]]
+ ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %3:_(s32) = COPY $x10
+ %4:_(s32) = COPY $x11
+ %5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
+ %6:_(s64) = G_ABDS %2, %5
+ %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
+ $x10 = COPY %7(s32)
+ $x11 = COPY %8(s32)
+ PseudoRET implicit $x10, implicit $x11
+...
+---
+name: abdu_i8
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: abdu_i8
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
+ ; CHECK-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
+ ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %3:_(s32) = G_ASSERT_ZEXT %1, 8
+ %4:_(s32) = G_ASSERT_ZEXT %2, 8
+ %5:_(s8) = G_TRUNC %3(s32)
+ %6:_(s8) = G_TRUNC %4(s32)
+ %7:_(s8) = G_ABDU %5, %6
+ %8:_(s32) = G_ANYEXT %7(s8)
+ $x10 = COPY %8(s32)
+ PseudoRET implicit $x10
+...
+---
+name: abdu_i16
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: abdu_i16
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
+ ; CHECK-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
+ ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %3:_(s32) = G_ASSERT_ZEXT %1, 16
+ %4:_(s32) = G_ASSERT_ZEXT %2, 16
+ %5:_(s16) = G_TRUNC %3(s32)
+ %6:_(s16) = G_TRUNC %4(s32)
+ %7:_(s16) = G_ABDU %5, %6
+ %8:_(s32) = G_ANYEXT %7(s16)
+ $x10 = COPY %8(s32)
+ PseudoRET implicit $x10
+...
+---
+name: abdu_i32
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; RV32I-LABEL: name: abdu_i32
+ ; RV32I: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+ ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
+ ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
+ ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32ZBB-LABEL: name: abdu_i32
+ ; RV32ZBB: liveins: $x10, $x11
+ ; RV32ZBB-NEXT: {{ $}}
+ ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]
+ ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]
+ ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]]
+ ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
+ ; RV32ZBB-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %3:_(s32) = G_ABDU %1, %2
+ $x10 = COPY %3(s32)
+ PseudoRET implicit $x10
+...
+---
+name: abdu_i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: abdu_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
+ ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[COPY]]
+ ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]]
+ ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[ICMP1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP2]], [[ICMP3]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB]], [[SUB3]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB2]], [[SUB5]]
+ ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %3:_(s32) = COPY $x10
+ %4:_(s32) = COPY $x11
+ %5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
+ %6:_(s64) = G_ABDU %2, %5
+ %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
+ $x10 = COPY %7(s32)
+ $x11 = COPY %8(s32)
+ PseudoRET implicit $x10, implicit $x11
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-
diff -rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-
diff -rv64.mir
new file mode 100644
index 0000000000000..170671684f18f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-
diff -rv64.mir
@@ -0,0 +1,266 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefixes=CHECK,RV64I
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB
+
+---
+name: abds_i8
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: abds_i8
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 8
+ ; CHECK-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY1]], 8
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s64), [[ASSERT_SEXT1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = COPY $x11
+ %3:_(s64) = G_ASSERT_SEXT %1, 8
+ %4:_(s64) = G_ASSERT_SEXT %2, 8
+ %5:_(s8) = G_TRUNC %3(s64)
+ %6:_(s8) = G_TRUNC %4(s64)
+ %7:_(s8) = G_ABDS %5, %6
+ %8:_(s64) = G_ANYEXT %7(s8)
+ $x10 = COPY %8(s64)
+ PseudoRET implicit $x10
+...
+---
+name: abds_i16
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: abds_i16
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16
+ ; CHECK-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY1]], 16
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s64), [[ASSERT_SEXT1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = COPY $x11
+ %3:_(s64) = G_ASSERT_SEXT %1, 16
+ %4:_(s64) = G_ASSERT_SEXT %2, 16
+ %5:_(s16) = G_TRUNC %3(s64)
+ %6:_(s16) = G_TRUNC %4(s64)
+ %7:_(s16) = G_ABDS %5, %6
+ %8:_(s64) = G_ANYEXT %7(s16)
+ $x10 = COPY %8(s64)
+ PseudoRET implicit $x10
+...
+---
+name: abds_i32
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: abds_i32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
+ ; CHECK-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY1]], 32
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG]](s64)
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG1]](s64)
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s64), [[ASSERT_SEXT1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = COPY $x11
+ %3:_(s64) = G_ASSERT_SEXT %1, 32
+ %4:_(s64) = G_ASSERT_SEXT %2, 32
+ %5:_(s32) = G_TRUNC %3(s64)
+ %6:_(s32) = G_TRUNC %4(s64)
+ %7:_(s32) = G_ABDS %5, %6
+ %8:_(s64) = G_ANYEXT %7(s32)
+ $x10 = COPY %8(s64)
+ PseudoRET implicit $x10
+...
+---
+name: abds_i64
+body: |
+ bb.0.entry:
+
+ ; RV64I-LABEL: name: abds_i64
+ ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]]
+ ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[COPY1]], [[COPY]]
+ ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
+ ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SUB]], [[SUB1]]
+ ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV64ZBB-LABEL: name: abds_i64
+ ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[COPY]], [[COPY1]]
+ ; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[COPY]], [[COPY1]]
+ ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SMAX]], [[SMIN]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64)
+ ; RV64ZBB-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = COPY $x11
+ %3:_(s64) = G_ABDS %1, %2
+ $x10 = COPY %3(s64)
+ PseudoRET implicit $x10
+...
+---
+name: abdu_i8
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; CHECK-LABEL: name: abdu_i8
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8
+ ; CHECK-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY1]], 8
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s64), [[ASSERT_ZEXT1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = COPY $x11
+ %3:_(s64) = G_ASSERT_ZEXT %1, 8
+ %4:_(s64) = G_ASSERT_ZEXT %2, 8
+ %5:_(s8) = G_TRUNC %3(s64)
+ %6:_(s8) = G_TRUNC %4(s64)
+ %7:_(s8) = G_ABDU %5, %6
+ %8:_(s64) = G_ANYEXT %7(s8)
+ $x10 = COPY %8(s64)
+ PseudoRET implicit $x10
+...
+---
+name: abdu_i16
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: abdu_i16
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16
+ ; CHECK-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY1]], 16
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s64), [[ASSERT_ZEXT1]]
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB1]](s64)
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = COPY $x11
+ %3:_(s64) = G_ASSERT_ZEXT %1, 16
+ %4:_(s64) = G_ASSERT_ZEXT %2, 16
+ %5:_(s16) = G_TRUNC %3(s64)
+ %6:_(s16) = G_TRUNC %4(s64)
+ %7:_(s16) = G_ABDU %5, %6
+ %8:_(s64) = G_ANYEXT %7(s16)
+ $x10 = COPY %8(s64)
+ PseudoRET implicit $x10
+...
+---
+name: abdu_i32
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: abdu_i32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32
+ ; CHECK-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY1]], 32
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG]](s64)
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG1]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ASSERT_ZEXT]], 32
+ ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ASSERT_ZEXT1]], 32
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[SEXT_INREG2]](s64), [[SEXT_INREG3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = COPY $x11
+ %3:_(s64) = G_ASSERT_ZEXT %1, 32
+ %4:_(s64) = G_ASSERT_ZEXT %2, 32
+ %5:_(s32) = G_TRUNC %3(s64)
+ %6:_(s32) = G_TRUNC %4(s64)
+ %7:_(s32) = G_ABDU %5, %6
+ %8:_(s64) = G_ANYEXT %7(s32)
+ $x10 = COPY %8(s64)
+ PseudoRET implicit $x10
+...
+---
+name: abdu_i64
+body: |
+ bb.0.entry:
+
+ ; RV64I-LABEL: name: abdu_i64
+ ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]]
+ ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[COPY1]], [[COPY]]
+ ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
+ ; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[SUB]], [[SUB1]]
+ ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV64ZBB-LABEL: name: abdu_i64
+ ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[COPY]], [[COPY1]]
+ ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[COPY]], [[COPY1]]
+ ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[UMAX]], [[UMIN]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64)
+ ; RV64ZBB-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = COPY $x11
+ %3:_(s64) = G_ABDU %1, %2
+ $x10 = COPY %3(s64)
+ PseudoRET implicit $x10
+...
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