[llvm] 52dd4b9 - [AArch64] Correctly disassemble TSB instruction (#156362)

[via llvm-commits]

Author: Sergei Barannikov
Date: 2025-09-05T14:35:55+03:00
New Revision: 52dd4b9b7e4de5c098053db4fb0952249112c796

URL: https://github.com/llvm/llvm-project/commit/52dd4b9b7e4de5c098053db4fb0952249112c796
DIFF: https://github.com/llvm/llvm-project/commit/52dd4b9b7e4de5c098053db4fb0952249112c796.diff

LOG: [AArch64] Correctly disassemble TSB instruction (#156362)

TSB instruction has one operand, but the generated disassembler is
unable to decode it since the operand is not encoded into the
instruction. AArch64InstPrinter has a special case for this -- if the
instruction being printed is TSB, it prints the only possible operand
value, regardless of whether the operand is present or not.

With the changes proposed by #156358, the operand can now be decoded
automatically and the workaround is no longer required.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SystemOperands.td
    llvm/lib/Target/AArch64/CMakeLists.txt
    llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 1b0e90b0e0dc3..65b752ed40c90 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -362,7 +362,7 @@ def lookupTSBByName : SearchIndex {
   let Key = ["Name"];
 }
 
-def : TSB<"csync", 0>;
+def : TSB<"csync", 2>;
 
 //===----------------------------------------------------------------------===//
 // PRFM (prefetch) instruction options.

diff  --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt
index 833ce48ea1d7a..79b56ea9cf850 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -8,8 +8,7 @@ tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
 tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
 tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler
-              -ignore-non-decodable-operands
-              -ignore-fully-defined-operands)
+              -ignore-non-decodable-operands)
 tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
 tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner

diff  --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 54b58e948daf2..2552ee3009338 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -365,13 +365,6 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
     return;
   }
 
-  // Instruction TSB is specified as a one operand instruction, but 'csync' is
-  // not encoded, so for printing it is treated as a special case here:
-  if (Opcode == AArch64::TSB) {
-    O << "\ttsb\tcsync";
-    return;
-  }
-
   if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
     printInstruction(MI, Address, STI, O);