[clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)

[Kinoshita Kotaro via llvm-commits]

kinoshita-fj wrote:

Thank you for your comments. I agree that we should not revert it.
However, is this lowering beneficial for anything other than the use of pairwise load/store for 128-bit SVE?
As I commented before, my understanding is that the practical benefit of this lowering itself is small.
So, if the benefit is limited, considering the effect on other CPUs, wouldn't option 1 be better?

https://github.com/llvm/llvm-project/pull/127837