[llvm] 633233c - [RISCV] Use MRI from MachineFunction in isVLKnownLE. NFC
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 4 23:45:06 PDT 2025
Author: Luke Lau
Date: 2025-09-05T14:44:56+08:00
New Revision: 633233c04cfa2a342cceaa0b4833fb35d61c3900
URL: https://github.com/llvm/llvm-project/commit/633233c04cfa2a342cceaa0b4833fb35d61c3900
DIFF: https://github.com/llvm/llvm-project/commit/633233c04cfa2a342cceaa0b4833fb35d61c3900.diff
LOG: [RISCV] Use MRI from MachineFunction in isVLKnownLE. NFC
TIL that MachineFunction actually stores a reference to
MachineRegisterInfo, so use that instead of plumbing it through. This
helps avoid the need to plumb MRI through static functions in #151285
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 872f2cff67e58..ee6d6cdb00096 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4796,12 +4796,12 @@ unsigned RISCV::getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW) {
return Scaled;
}
-static std::optional<int64_t> getEffectiveImm(const MachineOperand &MO,
- const MachineRegisterInfo *MRI) {
+static std::optional<int64_t> getEffectiveImm(const MachineOperand &MO) {
assert(MO.isImm() || MO.getReg().isVirtual());
if (MO.isImm())
return MO.getImm();
- const MachineInstr *Def = MRI->getVRegDef(MO.getReg());
+ const MachineInstr *Def =
+ MO.getParent()->getMF()->getRegInfo().getVRegDef(MO.getReg());
int64_t Imm;
if (isLoadImm(Def, Imm))
return Imm;
@@ -4809,9 +4809,9 @@ static std::optional<int64_t> getEffectiveImm(const MachineOperand &MO,
}
/// Given two VL operands, do we know that LHS <= RHS? Must be used in SSA form.
-bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS,
- const MachineRegisterInfo *MRI) {
- assert(MRI->isSSA());
+bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
+ assert((LHS.isImm() || LHS.getParent()->getMF()->getRegInfo().isSSA()) &&
+ (RHS.isImm() || RHS.getParent()->getMF()->getRegInfo().isSSA()));
if (LHS.isReg() && RHS.isReg() && LHS.getReg().isVirtual() &&
LHS.getReg() == RHS.getReg())
return true;
@@ -4821,8 +4821,8 @@ bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS,
return true;
if (LHS.isImm() && LHS.getImm() == RISCV::VLMaxSentinel)
return false;
- std::optional<int64_t> LHSImm = getEffectiveImm(LHS, MRI),
- RHSImm = getEffectiveImm(RHS, MRI);
+ std::optional<int64_t> LHSImm = getEffectiveImm(LHS),
+ RHSImm = getEffectiveImm(RHS);
if (!LHSImm || !RHSImm)
return false;
return LHSImm <= RHSImm;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 0defb184fba6d..785c8352d4a5e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -365,8 +365,7 @@ unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW);
static constexpr int64_t VLMaxSentinel = -1LL;
/// Given two VL operands, do we know that LHS <= RHS?
-bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS,
- const MachineRegisterInfo *MRI);
+bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS);
// Mask assignments for floating-point
static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index dca86d75f5c49..4d4f1db215220 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1379,7 +1379,7 @@ RISCVVLOptimizer::getMinimumVLForUser(const MachineOperand &UserOp) const {
assert(UserOp.getOperandNo() == UserMI.getNumExplicitDefs() &&
RISCVII::isFirstDefTiedToFirstUse(UserMI.getDesc()));
auto DemandedVL = DemandedVLs.lookup(&UserMI);
- if (!DemandedVL || !RISCV::isVLKnownLE(*DemandedVL, VLOp, MRI)) {
+ if (!DemandedVL || !RISCV::isVLKnownLE(*DemandedVL, VLOp)) {
LLVM_DEBUG(dbgs() << " Abort because user is passthru in "
"instruction with demanded tail\n");
return std::nullopt;
@@ -1397,7 +1397,7 @@ RISCVVLOptimizer::getMinimumVLForUser(const MachineOperand &UserOp) const {
// requires.
if (auto DemandedVL = DemandedVLs.lookup(&UserMI)) {
assert(isCandidate(UserMI));
- if (RISCV::isVLKnownLE(*DemandedVL, VLOp, MRI))
+ if (RISCV::isVLKnownLE(*DemandedVL, VLOp))
return DemandedVL;
}
@@ -1505,10 +1505,10 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
// Use the largest VL among all the users. If we cannot determine this
// statically, then we cannot optimize the VL.
- if (!CommonVL || RISCV::isVLKnownLE(*CommonVL, *VLOp, MRI)) {
+ if (!CommonVL || RISCV::isVLKnownLE(*CommonVL, *VLOp)) {
CommonVL = *VLOp;
LLVM_DEBUG(dbgs() << " User VL is: " << VLOp << "\n");
- } else if (!RISCV::isVLKnownLE(*VLOp, *CommonVL, MRI)) {
+ } else if (!RISCV::isVLKnownLE(*VLOp, *CommonVL)) {
LLVM_DEBUG(dbgs() << " Abort because cannot determine a common VL\n");
return std::nullopt;
}
@@ -1570,7 +1570,7 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI) const {
CommonVL = VLMI->getOperand(RISCVII::getVLOpNum(VLMI->getDesc()));
}
- if (!RISCV::isVLKnownLE(*CommonVL, VLOp, MRI)) {
+ if (!RISCV::isVLKnownLE(*CommonVL, VLOp)) {
LLVM_DEBUG(dbgs() << " Abort due to CommonVL not <= VLOp.\n");
return false;
}
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 6ea010ebb73d7..62651185137c9 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -177,7 +177,7 @@ bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const {
MachineOperand &SrcVL =
Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
- if (VL.isIdenticalTo(SrcVL) || !RISCV::isVLKnownLE(VL, SrcVL, MRI))
+ if (VL.isIdenticalTo(SrcVL) || !RISCV::isVLKnownLE(VL, SrcVL))
continue;
if (!ensureDominates(VL, *Src))
@@ -440,7 +440,7 @@ bool RISCVVectorPeephole::convertSameMaskVMergeToVMv(MachineInstr &MI) {
const MachineOperand &MIVL = MI.getOperand(RISCVII::getVLOpNum(MI.getDesc()));
const MachineOperand &TrueVL =
True->getOperand(RISCVII::getVLOpNum(True->getDesc()));
- if (!RISCV::isVLKnownLE(MIVL, TrueVL, MRI))
+ if (!RISCV::isVLKnownLE(MIVL, TrueVL))
return false;
// True's passthru needs to be equivalent to False
@@ -611,7 +611,7 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
MachineOperand &SrcPolicy =
Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc()));
- if (RISCV::isVLKnownLE(MIVL, SrcVL, MRI))
+ if (RISCV::isVLKnownLE(MIVL, SrcVL))
SrcPolicy.setImm(SrcPolicy.getImm() | RISCVVType::TAIL_AGNOSTIC);
}
@@ -663,7 +663,7 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
// so we don't need to handle a smaller source VL here. However, the
// user's VL may be larger
MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
- if (!RISCV::isVLKnownLE(SrcVL, MI.getOperand(3), MRI))
+ if (!RISCV::isVLKnownLE(SrcVL, MI.getOperand(3)))
return false;
// If the new passthru doesn't dominate Src, try to move Src so it does.
@@ -684,7 +684,7 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
// If MI was tail agnostic and the VL didn't increase, preserve it.
int64_t Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED;
if ((MI.getOperand(5).getImm() & RISCVVType::TAIL_AGNOSTIC) &&
- RISCV::isVLKnownLE(MI.getOperand(3), SrcVL, MRI))
+ RISCV::isVLKnownLE(MI.getOperand(3), SrcVL))
Policy |= RISCVVType::TAIL_AGNOSTIC;
Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc())).setImm(Policy);
}
@@ -775,9 +775,9 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
True.getOperand(RISCVII::getVLOpNum(True.getDesc()));
MachineOperand MinVL = MachineOperand::CreateImm(0);
- if (RISCV::isVLKnownLE(TrueVL, VMergeVL, MRI))
+ if (RISCV::isVLKnownLE(TrueVL, VMergeVL))
MinVL = TrueVL;
- else if (RISCV::isVLKnownLE(VMergeVL, TrueVL, MRI))
+ else if (RISCV::isVLKnownLE(VMergeVL, TrueVL))
MinVL = VMergeVL;
else
return false;
@@ -797,7 +797,7 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
// to the tail. In that case we always need to use tail undisturbed to
// preserve them.
uint64_t Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED;
- if (!PassthruReg && RISCV::isVLKnownLE(VMergeVL, MinVL, MRI))
+ if (!PassthruReg && RISCV::isVLKnownLE(VMergeVL, MinVL))
Policy |= RISCVVType::TAIL_AGNOSTIC;
assert(RISCVII::hasVecPolicyOp(True.getDesc().TSFlags) &&
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