[llvm] [AVR] Refactor ADIW/SBIW/MOVW instruction descriptions (NFCI) (PR #156876)

[Ben Shi via llvm-commits]

================
@@ -91,6 +98,22 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeDREGSRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
+  assert(isUInt<4>(RegNo));
+  Inst.addOperand(MCOperand::createReg(GPRPairDecoderTable[RegNo]));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeIWREGSRegisterClass(MCInst &Inst, unsigned RegNo,
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder) {
+  assert(isUInt<2>(RegNo));
+  Inst.addOperand(MCOperand::createReg(GPRPairDecoderTable[12 + RegNo]));
----------------
benshi001 wrote:

It would be better to add a comment line, something like
```
Only AVR::R25R24, AVR::R27R26, AVR::R29R28, AVR::R31R30 are legal.
```

https://github.com/llvm/llvm-project/pull/156876