[llvm] [DAG][ARM] canCreateUndefOrPoisonForTargetNode - ARMISD VORRIMM\VBICIMM nodes can't create poison/undef (PR #156831)

via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 4 20:22:22 PDT 2025


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@@ -106,6 +106,19 @@ TEST_F(ARMSelectionDAGTest, computeKnownBits_VORRIMM) {
   KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
   EXPECT_EQ(Known.One, APInt(32, 0xAA));
   EXPECT_EQ(Known.Zero, APInt(32, 0x0));
+
+  // LHS(per-lane)     = 00000000 00000000 00000000 00000000  (0x00000000)
+  // Encoded(per-lane) = 00000000 00000000 00000000 10101010  (0x000000AA)
+  //  =>
+  // Known.One  = 00000000 00000000 00000000 10101010  (0x000000AA)
+  // Known.Zero = 11111111 11111111 11111111 01010101  (0x00000000)
+  SDValue Zero = DAG->getConstant(0, DL, MVT::i32);
+  SDValue ZeroVec = DAG->getSplatBuildVector(VT, DL, Zero);
+  Op = DAG->getNode(ARMISD::VORRIMM, DL, VT, ZeroVec, EncSD);
+  auto FrVORRIMM = DAG->getFreeze(Op);
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woruyu wrote:

Yes — it does “fail” in the specific case where the LHS is a Register $noreg.

Concretely, when I build Fr = DAG->getFreeze(Op) and Op is VORRIMM(LHS, Imm) with LHS coming from t1: v4i32 = Register $noreg, the FREEZE node is not eliminated:
1. !canCreateUndefOrPoisonForTargetNode is true
2. all_of(Op->ops(), [&](SDValue V) {DAG.isGuaranteedNotToBeUndefOrPoison} is false for t1: v4i32 = Register $noreg

https://github.com/llvm/llvm-project/pull/156831


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