[llvm] 927eba2 - [NFC][TableGen] Adopt `CodeGenInstruction::getName()` (#156968)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 4 16:49:29 PDT 2025
Author: Rahul Joshi
Date: 2025-09-04T16:49:26-07:00
New Revision: 927eba24561455e444b249b24437b8abae7051ce
URL: https://github.com/llvm/llvm-project/commit/927eba24561455e444b249b24437b8abae7051ce
DIFF: https://github.com/llvm/llvm-project/commit/927eba24561455e444b249b24437b8abae7051ce.diff
LOG: [NFC][TableGen] Adopt `CodeGenInstruction::getName()` (#156968)
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Added:
Modified:
llvm/utils/TableGen/AsmMatcherEmitter.cpp
llvm/utils/TableGen/AsmWriterEmitter.cpp
llvm/utils/TableGen/Common/AsmWriterInst.cpp
llvm/utils/TableGen/Common/CodeGenSchedule.cpp
llvm/utils/TableGen/Common/DAGISelMatcher.cpp
llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
llvm/utils/TableGen/CompressInstEmitter.cpp
llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
llvm/utils/TableGen/GlobalISelEmitter.cpp
llvm/utils/TableGen/InstrInfoEmitter.cpp
llvm/utils/TableGen/PseudoLoweringEmitter.cpp
llvm/utils/TableGen/X86FoldTablesEmitter.cpp
llvm/utils/TableGen/X86InstrMappingEmitter.cpp
llvm/utils/TableGen/X86MnemonicTables.cpp
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index bfd158614ae39..a373d2e2014b1 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -1545,7 +1545,7 @@ void AsmMatcherInfo::buildInfo() {
// If the tblgen -match-prefix option is specified (for tblgen hackers),
// filter the set of instructions we consider.
- if (!StringRef(CGI->TheDef->getName()).starts_with(MatchPrefix))
+ if (!StringRef(CGI->getName()).starts_with(MatchPrefix))
continue;
// Ignore "codegen only" instructions.
@@ -1578,8 +1578,7 @@ void AsmMatcherInfo::buildInfo() {
// If the tblgen -match-prefix option is specified (for tblgen hackers),
// filter the set of instruction aliases we consider, based on the target
// instruction.
- if (!StringRef(Alias->ResultInst->TheDef->getName())
- .starts_with(MatchPrefix))
+ if (!StringRef(Alias->ResultInst->getName()).starts_with(MatchPrefix))
continue;
StringRef V = Alias->TheDef->getValueAsString("AsmVariantName");
@@ -3562,7 +3561,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
char(MI->Mnemonic.size()) + MI->Mnemonic.lower();
OS << " { " << *StringTable.GetStringOffset(LenMnemonic) << " /* "
<< MI->Mnemonic << " */, " << Target.getInstNamespace()
- << "::" << MI->getResultInst()->TheDef->getName() << ", "
+ << "::" << MI->getResultInst()->getName() << ", "
<< MI->ConversionFnKind << ", ";
// Write the required features mask.
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index cbe645778fa3f..9f32333f82100 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -129,11 +129,10 @@ static void EmitInstructions(std::vector<AsmWriterInst> &Insts, raw_ostream &O,
}
}
- O << " case " << FirstInst.CGI->Namespace
- << "::" << FirstInst.CGI->TheDef->getName() << ":\n";
+ O << " case " << FirstInst.CGI->Namespace << "::" << FirstInst.CGI->getName()
+ << ":\n";
for (const AsmWriterInst &AWI : SimilarInsts)
- O << " case " << AWI.CGI->Namespace << "::" << AWI.CGI->TheDef->getName()
- << ":\n";
+ O << " case " << AWI.CGI->Namespace << "::" << AWI.CGI->getName() << ":\n";
for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
if (i != DifferingOperand) {
// If the operand is the same for all instructions, just print it.
@@ -145,12 +144,12 @@ static void EmitInstructions(std::vector<AsmWriterInst> &Insts, raw_ostream &O,
O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint;
OpsToPrint.emplace_back(FirstInst.CGI->Namespace.str() +
- "::" + FirstInst.CGI->TheDef->getName().str(),
+ "::" + FirstInst.CGI->getName().str(),
FirstInst.Operands[i]);
for (const AsmWriterInst &AWI : SimilarInsts) {
OpsToPrint.emplace_back(AWI.CGI->Namespace.str() +
- "::" + AWI.CGI->TheDef->getName().str(),
+ "::" + AWI.CGI->getName().str(),
AWI.Operands[i]);
}
std::reverse(OpsToPrint.begin(), OpsToPrint.end());
@@ -188,11 +187,11 @@ void AsmWriterEmitter::FindUniqueOperandCommands(
if (I != UniqueOperandCommands.end()) {
size_t idx = I - UniqueOperandCommands.begin();
InstrsForCase[idx] += ", ";
- InstrsForCase[idx] += Inst.CGI->TheDef->getName();
+ InstrsForCase[idx] += Inst.CGI->getName();
InstIdxs[idx].push_back(i);
} else {
UniqueOperandCommands.push_back(std::move(Command));
- InstrsForCase.push_back(Inst.CGI->TheDef->getName().str());
+ InstrsForCase.push_back(Inst.CGI->getName().str());
InstIdxs.emplace_back();
InstIdxs.back().push_back(i);
@@ -451,7 +450,7 @@ void AsmWriterEmitter::EmitGetMnemonic(
<< "[] = {\n";
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
O << " " << ((OpcodeInfo[i] >> Shift) & Mask) << "U,\t// "
- << NumberedInstructions[i]->TheDef->getName() << "\n";
+ << NumberedInstructions[i]->getName() << '\n';
}
O << " };\n\n";
// Emit string to combine the individual table lookups.
@@ -1317,7 +1316,7 @@ AsmWriterEmitter::AsmWriterEmitter(const RecordKeeper &R)
NumberedInstructions = Target.getInstructions();
for (const auto &[Idx, I] : enumerate(NumberedInstructions)) {
- if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
+ if (!I->AsmString.empty() && I->getName() != "PHI")
Instructions.emplace_back(*I, Idx, Variant);
}
}
diff --git a/llvm/utils/TableGen/Common/AsmWriterInst.cpp b/llvm/utils/TableGen/Common/AsmWriterInst.cpp
index 3629247751d2f..97430a1eec8a1 100644
--- a/llvm/utils/TableGen/Common/AsmWriterInst.cpp
+++ b/llvm/utils/TableGen/Common/AsmWriterInst.cpp
@@ -94,7 +94,7 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
PrintFatalError(
CGI.TheDef->getLoc(),
"Non-supported escaped character found in instruction '" +
- CGI.TheDef->getName() + "'!");
+ CGI.getName() + "'!");
}
LastEmitted = DollarPos + 2;
continue;
@@ -135,7 +135,7 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
PrintFatalError(
CGI.TheDef->getLoc(),
"Reached end of string before terminating curly brace in '" +
- CGI.TheDef->getName() + "'");
+ CGI.getName() + "'");
// Look for a modifier string.
if (AsmString[VarEnd] == ':') {
@@ -144,7 +144,7 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
PrintFatalError(
CGI.TheDef->getLoc(),
"Reached end of string before terminating curly brace in '" +
- CGI.TheDef->getName() + "'");
+ CGI.getName() + "'");
std::string::size_type ModifierStart = VarEnd;
while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
@@ -152,20 +152,20 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
Modifier = AsmString.substr(ModifierStart, VarEnd - ModifierStart);
if (Modifier.empty())
PrintFatalError(CGI.TheDef->getLoc(),
- "Bad operand modifier name in '" +
- CGI.TheDef->getName() + "'");
+ "Bad operand modifier name in '" + CGI.getName() +
+ "'");
}
if (AsmString[VarEnd] != '}')
PrintFatalError(
CGI.TheDef->getLoc(),
"Variable name beginning with '{' did not end with '}' in '" +
- CGI.TheDef->getName() + "'");
+ CGI.getName() + "'");
++VarEnd;
}
if (VarName.empty() && Modifier.empty())
PrintFatalError(CGI.TheDef->getLoc(),
- "Stray '$' in '" + CGI.TheDef->getName() +
+ "Stray '$' in '" + CGI.getName() +
"' asm string, maybe you want $$?");
if (VarName.empty()) {
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index b07ea9e9d5caf..a47ab7667d891 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -134,7 +134,7 @@ struct InstRegexOp : public SetTheory::Operator {
// The generic opcodes are unsorted, handle them manually.
for (auto *Inst : Generics) {
- StringRef InstName = Inst->TheDef->getName();
+ StringRef InstName = Inst->getName();
if (InstName.starts_with(Prefix) &&
(!Regexpr || Regexpr->match(InstName.substr(Prefix.size())))) {
Elts.insert(Inst->TheDef);
@@ -147,11 +147,10 @@ struct InstRegexOp : public SetTheory::Operator {
// sorted by name. Find the sub-ranges that start with our prefix.
struct Comp {
bool operator()(const CodeGenInstruction *LHS, StringRef RHS) {
- return LHS->TheDef->getName() < RHS;
+ return LHS->getName() < RHS;
}
bool operator()(StringRef LHS, const CodeGenInstruction *RHS) {
- return LHS < RHS->TheDef->getName() &&
- !RHS->TheDef->getName().starts_with(LHS);
+ return LHS < RHS->getName() && !RHS->getName().starts_with(LHS);
}
};
auto Range1 =
@@ -162,7 +161,7 @@ struct InstRegexOp : public SetTheory::Operator {
// For these ranges we know that instruction names start with the prefix.
// Check if there's a regex that needs to be checked.
const auto HandleNonGeneric = [&](const CodeGenInstruction *Inst) {
- StringRef InstName = Inst->TheDef->getName();
+ StringRef InstName = Inst->getName();
if (!Regexpr || Regexpr->match(InstName.substr(Prefix.size()))) {
Elts.insert(Inst->TheDef);
NumMatches++;
@@ -862,12 +861,12 @@ void CodeGenSchedModels::collectSchedClasses() {
dbgs()
<< "\n+++ ITINERARIES and/or MACHINE MODELS (collectSchedClasses) +++\n");
for (const CodeGenInstruction *Inst : Target.getInstructions()) {
- StringRef InstName = Inst->TheDef->getName();
+ StringRef InstName = Inst->getName();
unsigned SCIdx = getSchedClassIdx(*Inst);
if (!SCIdx) {
LLVM_DEBUG({
if (!Inst->hasNoSchedulingInfo)
- dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
+ dbgs() << "No machine model for " << Inst->getName() << '\n';
});
continue;
}
@@ -916,7 +915,7 @@ void CodeGenSchedModels::collectSchedClasses() {
if (!llvm::is_contained(ProcIndices, 0)) {
for (const CodeGenProcModel &PM : ProcModels) {
if (!llvm::is_contained(ProcIndices, PM.Index))
- dbgs() << "No machine model for " << Inst->TheDef->getName()
+ dbgs() << "No machine model for " << Inst->getName()
<< " on processor " << PM.ModelName << '\n';
}
}
@@ -1932,7 +1931,7 @@ void CodeGenSchedModels::checkCompleteness() {
if (Inst->TheDef->isValueUnset("SchedRW")) {
PrintError(Inst->TheDef->getLoc(),
"No schedule information for instruction '" +
- Inst->TheDef->getName() + "' in SchedMachineModel '" +
+ Inst->getName() + "' in SchedMachineModel '" +
ProcModel.ModelDef->getName() + "'");
Complete = false;
}
@@ -1953,7 +1952,7 @@ void CodeGenSchedModels::checkCompleteness() {
if (I == InstRWs.end()) {
PrintError(Inst->TheDef->getLoc(), "'" + ProcModel.ModelName +
"' lacks information for '" +
- Inst->TheDef->getName() + "'");
+ Inst->getName() + "'");
Complete = false;
}
}
diff --git a/llvm/utils/TableGen/Common/DAGISelMatcher.cpp b/llvm/utils/TableGen/Common/DAGISelMatcher.cpp
index 3543bb5a55c64..255974624e8f0 100644
--- a/llvm/utils/TableGen/Common/DAGISelMatcher.cpp
+++ b/llvm/utils/TableGen/Common/DAGISelMatcher.cpp
@@ -284,7 +284,7 @@ void EmitNodeXFormMatcher::printImpl(raw_ostream &OS, indent Indent) const {
void EmitNodeMatcherCommon::printImpl(raw_ostream &OS, indent Indent) const {
OS << Indent;
OS << (isa<MorphNodeToMatcher>(this) ? "MorphNodeTo: " : "EmitNode: ")
- << CGI.Namespace << "::" << CGI.TheDef->getName() << ": <todo flags> ";
+ << CGI.Namespace << "::" << CGI.getName() << ": <todo flags> ";
for (MVT::SimpleValueType VT : VTs)
OS << ' ' << getEnumName(VT);
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 42c1cc91a3c1e..623fef973f989 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -1455,9 +1455,8 @@ RecordAndValue
InstructionOpcodeMatcher::getInstValue(const CodeGenInstruction *I) const {
const auto VI = OpcodeValues.find(I);
if (VI != OpcodeValues.end())
- return {MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName()),
- VI->second};
- return MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName());
+ return {MatchTable::NamedValue(2, I->Namespace, I->getName()), VI->second};
+ return MatchTable::NamedValue(2, I->Namespace, I->getName());
}
void InstructionOpcodeMatcher::initOpcodeValuesMap(
@@ -1474,9 +1473,8 @@ RecordAndValue InstructionOpcodeMatcher::getValue() const {
const CodeGenInstruction *I = Insts[0];
const auto VI = OpcodeValues.find(I);
if (VI != OpcodeValues.end())
- return {MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName()),
- VI->second};
- return MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName());
+ return {MatchTable::NamedValue(2, I->Namespace, I->getName()), VI->second};
+ return MatchTable::NamedValue(2, I->Namespace, I->getName());
}
void InstructionOpcodeMatcher::emitPredicateOpcodes(MatchTable &Table,
@@ -1503,17 +1501,17 @@ bool InstructionOpcodeMatcher::isHigherPriorityThan(
// using instruction frequency information to improve compile time.
if (const InstructionOpcodeMatcher *BO =
dyn_cast<InstructionOpcodeMatcher>(&B))
- return Insts[0]->TheDef->getName() < BO->Insts[0]->TheDef->getName();
+ return Insts[0]->getName() < BO->Insts[0]->getName();
return false;
}
bool InstructionOpcodeMatcher::isConstantInstruction() const {
- return Insts.size() == 1 && Insts[0]->TheDef->getName() == "G_CONSTANT";
+ return Insts.size() == 1 && Insts[0]->getName() == "G_CONSTANT";
}
StringRef InstructionOpcodeMatcher::getOpcode() const {
- return Insts[0]->TheDef->getName();
+ return Insts[0]->getName();
}
bool InstructionOpcodeMatcher::isVariadicNumOperands() const {
@@ -2245,7 +2243,7 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table,
<< MatchTable::Comment("RecycleInsnID")
<< MatchTable::ULEB128Value(RecycleInsnID)
<< MatchTable::Comment("Opcode")
- << MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName())
+ << MatchTable::NamedValue(2, I->Namespace, I->getName())
<< MatchTable::LineBreak;
if (!I->ImplicitDefs.empty() || !I->ImplicitUses.empty()) {
@@ -2292,7 +2290,7 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table,
}
Table << MatchTable::Comment("Opcode")
- << MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName())
+ << MatchTable::NamedValue(2, I->Namespace, I->getName())
<< MatchTable::LineBreak;
for (const auto &Renderer : OperandRenderers)
diff --git a/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp b/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
index 07db6baef84a0..c503c9a47b4ff 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
@@ -168,8 +168,7 @@ void Pattern::printImpl(raw_ostream &OS, bool PrintName,
void AnyOpcodePattern::print(raw_ostream &OS, bool PrintName) const {
printImpl(OS, PrintName, [&OS, this]() {
OS << "["
- << join(map_range(Insts,
- [](const auto *I) { return I->TheDef->getName(); }),
+ << join(map_range(Insts, [](const auto *I) { return I->getName(); }),
", ")
<< "]";
});
@@ -366,7 +365,7 @@ void MIFlagsInfo::addCopyFlag(StringRef InstName) { CopyF.insert(InstName); }
//===- CodeGenInstructionPattern ------------------------------------------===//
bool CodeGenInstructionPattern::is(StringRef OpcodeName) const {
- return I.TheDef->getName() == OpcodeName;
+ return I.getName() == OpcodeName;
}
bool CodeGenInstructionPattern::isVariadic() const {
@@ -416,9 +415,7 @@ MIFlagsInfo &CodeGenInstructionPattern::getOrCreateMIFlagsInfo() {
return *FI;
}
-StringRef CodeGenInstructionPattern::getInstName() const {
- return I.TheDef->getName();
-}
+StringRef CodeGenInstructionPattern::getInstName() const { return I.getName(); }
void CodeGenInstructionPattern::printExtras(raw_ostream &OS) const {
if (isIntrinsic())
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index 89c175bd40df8..ccf83859924bc 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -237,7 +237,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
// Source instructions can have at most 1 tied operand.
if (IsSourceInst && (OpNo - DAGOpNo > 1))
PrintFatalError(Rec->getLoc(),
- "Input operands for Inst '" + Inst.TheDef->getName() +
+ "Input operands for Inst '" + Inst.getName() +
"' and input Dag operand count mismatch");
continue;
@@ -249,7 +249,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
OpndRec = cast<DefInit>(Opnd.MIOperandInfo->getArg(SubOp))->getDef();
if (DAGOpNo >= Dag->getNumArgs())
- PrintFatalError(Rec->getLoc(), "Inst '" + Inst.TheDef->getName() +
+ PrintFatalError(Rec->getLoc(), "Inst '" + Inst.getName() +
"' and Dag operand count mismatch");
if (const auto *DI = dyn_cast<DefInit>(Dag->getArg(DAGOpNo))) {
@@ -328,7 +328,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
// We shouldn't have extra Dag operands.
if (DAGOpNo != Dag->getNumArgs())
- PrintFatalError(Rec->getLoc(), "Inst '" + Inst.TheDef->getName() +
+ PrintFatalError(Rec->getLoc(), "Inst '" + Inst.getName() +
"' and Dag operand count mismatch");
}
@@ -590,8 +590,8 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
llvm::stable_sort(CompressPatterns, [EType](const CompressPat &LHS,
const CompressPat &RHS) {
if (EType == EmitterType::Compress || EType == EmitterType::CheckCompress)
- return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName());
- return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName());
+ return LHS.Source.getName() < RHS.Source.getName();
+ return LHS.Dest.getName() < RHS.Dest.getName();
});
// A list of MCOperandPredicates for all operands in use, and the reverse map.
@@ -678,7 +678,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
CompressOrCheck ? CompressPat.DestOperandMap
: CompressPat.SourceOperandMap;
- CurOp = Source.TheDef->getName();
+ CurOp = Source.getName();
// Check current and previous opcode to decide to continue or end a case.
if (CurOp != PrevOp) {
if (!PrevOp.empty()) {
@@ -768,7 +768,7 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
CodeStream.indent(6) << "// " << Dest.AsmString << "\n";
if (CompressOrUncompress)
CodeStream.indent(6) << "OutInst.setOpcode(" << TargetName
- << "::" << Dest.TheDef->getName() << ");\n";
+ << "::" << Dest.getName() << ");\n";
OpNo = 0;
for (const auto &DestOperand : Dest.Operands) {
CodeStream.indent(6) << "// Operand: " << DestOperand.Name << "\n";
diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
index f62b26587cf4b..83dc34896e6f6 100644
--- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
@@ -1662,8 +1662,7 @@ bool CombineRuleBuilder::emitMatchPattern(CodeExpansions &CE,
const bool IsUsingCustomCXXAction = hasOnlyCXXApplyPatterns();
for (const CodeGenInstruction *CGI : AOP.insts()) {
- auto &M = addRuleMatcher(Alts, "wip_match_opcode '" +
- CGI->TheDef->getName() + "'");
+ auto &M = addRuleMatcher(Alts, "wip_match_opcode '" + CGI->getName() + "'");
InstructionMatcher &IM = M.addInstructionMatcher(AOP.getName());
declareInstExpansion(CE, IM, AOP.getName());
@@ -2201,7 +2200,7 @@ bool CombineRuleBuilder::emitBuiltinApplyPattern(
bool isLiteralImm(const InstructionPattern &P, unsigned OpIdx) {
if (const auto *CGP = dyn_cast<CodeGenInstructionPattern>(&P)) {
- StringRef InstName = CGP->getInst().TheDef->getName();
+ StringRef InstName = CGP->getInst().getName();
return (InstName == "G_CONSTANT" || InstName == "G_FCONSTANT") &&
OpIdx == 1;
}
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 6772043c21056..fcfcb36a124a8 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -859,9 +859,9 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
} else {
assert(SrcGIOrNull &&
"Expected to have already found an equivalent Instruction");
- if (SrcGIOrNull->TheDef->getName() == "G_CONSTANT" ||
- SrcGIOrNull->TheDef->getName() == "G_FCONSTANT" ||
- SrcGIOrNull->TheDef->getName() == "G_FRAME_INDEX") {
+ if (SrcGIOrNull->getName() == "G_CONSTANT" ||
+ SrcGIOrNull->getName() == "G_FCONSTANT" ||
+ SrcGIOrNull->getName() == "G_FRAME_INDEX") {
// imm/fpimm still have operands but we don't need to do anything with it
// here since we don't support ImmLeaf predicates yet. However, we still
// need to note the hidden operand to get GIM_CheckNumOperands correct.
@@ -874,9 +874,9 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
// source.
unsigned NumChildren = Src.getNumChildren();
- bool IsFCmp = SrcGIOrNull->TheDef->getName() == "G_FCMP";
+ bool IsFCmp = SrcGIOrNull->getName() == "G_FCMP";
- if (IsFCmp || SrcGIOrNull->TheDef->getName() == "G_ICMP") {
+ if (IsFCmp || SrcGIOrNull->getName() == "G_ICMP") {
const TreePatternNode &SrcChild = Src.getChild(NumChildren - 1);
if (SrcChild.isLeaf()) {
const DefInit *DI = dyn_cast<DefInit>(SrcChild.getLeafValue());
@@ -899,11 +899,10 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
// Match the used operands (i.e. the children of the operator).
bool IsIntrinsic =
- SrcGIOrNull->TheDef->getName() == "G_INTRINSIC" ||
- SrcGIOrNull->TheDef->getName() == "G_INTRINSIC_W_SIDE_EFFECTS" ||
- SrcGIOrNull->TheDef->getName() == "G_INTRINSIC_CONVERGENT" ||
- SrcGIOrNull->TheDef->getName() ==
- "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS";
+ SrcGIOrNull->getName() == "G_INTRINSIC" ||
+ SrcGIOrNull->getName() == "G_INTRINSIC_W_SIDE_EFFECTS" ||
+ SrcGIOrNull->getName() == "G_INTRINSIC_CONVERGENT" ||
+ SrcGIOrNull->getName() == "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS";
const CodeGenIntrinsic *II = Src.getIntrinsicInfo(CGP);
if (IsIntrinsic && !II)
return failedImport("Expected IntInit containing intrinsic ID)");
@@ -1521,7 +1520,7 @@ GlobalISelEmitter::createInstructionRenderer(action_iterator InsertPt,
// COPY_TO_REGCLASS is just a copy with a ConstrainOperandToRegClassAction
// attached. Similarly for EXTRACT_SUBREG except that's a subregister copy.
- StringRef Name = DstI->TheDef->getName();
+ StringRef Name = DstI->getName();
if (Name == "COPY_TO_REGCLASS" || Name == "EXTRACT_SUBREG")
DstI = &Target.getInstruction(RK.getDef("COPY"));
@@ -1603,7 +1602,7 @@ Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderers(
const CodeGenInstruction *DstI = DstMIBuilder.getCGI();
CodeGenInstruction *OrigDstI = &Target.getInstruction(Dst.getOperator());
- StringRef Name = OrigDstI->TheDef->getName();
+ StringRef Name = OrigDstI->getName();
unsigned ExpectedDstINumUses = Dst.getNumChildren();
// EXTRACT_SUBREG needs to use a subregister COPY.
@@ -1784,7 +1783,7 @@ Error GlobalISelEmitter::constrainOperands(action_iterator InsertPt,
const TreePatternNode &Dst) const {
const Record *DstOp = Dst.getOperator();
const CodeGenInstruction &DstI = Target.getInstruction(DstOp);
- StringRef DstIName = DstI.TheDef->getName();
+ StringRef DstIName = DstI.getName();
if (DstIName == "COPY_TO_REGCLASS") {
// COPY_TO_REGCLASS does not provide operand constraints itself but the
@@ -1934,7 +1933,7 @@ GlobalISelEmitter::inferRegClassFromInstructionPattern(const TreePatternNode &N,
// Handle any special-case instructions which we can safely infer register
// classes from.
- StringRef InstName = Inst.TheDef->getName();
+ StringRef InstName = Inst.getName();
if (InstName == "REG_SEQUENCE") {
// (outs $super_dst), (ins $dst_regclass, variable_ops)
// Destination register class is explicitly specified by the first operand.
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 07a7cc4869b4a..0fc421682c897 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -453,7 +453,7 @@ void InstrInfoEmitter::emitOperandTypeMappings(
OS << "LLVM_READONLY\n";
OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
auto getInstrName = [&](int I) -> StringRef {
- return NumberedInstructions[I]->TheDef->getName();
+ return NumberedInstructions[I]->getName();
};
// TODO: Factor out duplicate operand lists to compress the tables.
std::vector<size_t> OperandOffsets;
@@ -572,8 +572,7 @@ void InstrInfoEmitter::emitLogicalOperandSizeMappings(
auto I =
LogicalOpSizeMap.try_emplace(LogicalOpList, LogicalOpSizeMap.size())
.first;
- InstMap[I->second].push_back(
- (Namespace + "::" + Inst->TheDef->getName()).str());
+ InstMap[I->second].push_back((Namespace + "::" + Inst->getName()).str());
}
OS << "#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP\n";
@@ -777,7 +776,7 @@ void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
}
if (!NumPredicates)
OS << "_None";
- OS << ", // " << Inst->TheDef->getName() << '\n';
+ OS << ", // " << Inst->getName() << '\n';
}
OS << " };\n\n"
<< " assert(Opcode < " << NumberedInstructions.size() << ");\n"
@@ -958,7 +957,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
unsigned Num = NumberedInstructions.size();
for (const CodeGenInstruction *Inst : reverse(NumberedInstructions)) {
// Keep a list of the instruction names.
- InstrNames.add(Inst->TheDef->getName());
+ InstrNames.add(Inst->getName());
// Emit the record into the table.
emitRecord(*Inst, --Num, InstrInfo, EmittedLists, OperandInfoMap, OS);
}
@@ -994,7 +993,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
// Newline every eight entries.
if (Num % 8 == 0)
OS << "\n ";
- OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
+ OS << InstrNames.get(Inst->getName()) << "U, ";
++Num;
}
OS << "\n};\n\n";
@@ -1280,13 +1279,13 @@ void InstrInfoEmitter::emitRecord(
Value |= uint64_t(Bit->getValue()) << i;
else
PrintFatalError(Inst.TheDef->getLoc(),
- "Invalid TSFlags bit in " + Inst.TheDef->getName());
+ "Invalid TSFlags bit in " + Inst.getName());
}
OS << ", 0x";
OS.write_hex(Value);
OS << "ULL";
- OS << " }, // " << Inst.TheDef->getName() << '\n';
+ OS << " }, // " << Inst.getName() << '\n';
}
// emitEnums - Print out enum values for all of the instructions.
@@ -1313,7 +1312,7 @@ void InstrInfoEmitter::emitEnums(
OS << " enum {\n";
for (const CodeGenInstruction *Inst : NumberedInstructions) {
- OS << " " << left_justify(Inst->TheDef->getName(), MaxNameSize) << " = "
+ OS << " " << left_justify(Inst->getName(), MaxNameSize) << " = "
<< Target.getInstrIntValue(Inst->TheDef) << ", // "
<< SrcMgr.getFormattedLocationNoOffset(Inst->TheDef->getLoc().front())
<< '\n';
diff --git a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
index a860e681f461f..3cefdca1f1a14 100644
--- a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
+++ b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
@@ -229,11 +229,10 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
for (auto &Expansion : Expansions) {
CodeGenInstruction &Source = Expansion.Source;
CodeGenInstruction &Dest = Expansion.Dest;
- o << " case " << Source.Namespace << "::" << Source.TheDef->getName()
- << ": {\n"
+ o << " case " << Source.Namespace << "::" << Source.getName() << ": {\n"
<< " MCOperand MCOp;\n"
- << " Inst.setOpcode(" << Dest.Namespace
- << "::" << Dest.TheDef->getName() << ");\n";
+ << " Inst.setOpcode(" << Dest.Namespace << "::" << Dest.getName()
+ << ");\n";
// Copy the operands from the source instruction.
// FIXME: Instruction operands with defaults values (predicates and cc_out
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index d63570a88a4cb..762fae608bd19 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -52,13 +52,13 @@ const std::set<StringRef> NoFoldSet = {
static bool isExplicitAlign(const CodeGenInstruction *Inst) {
return any_of(ExplicitAlign, [Inst](const char *InstStr) {
- return Inst->TheDef->getName().contains(InstStr);
+ return Inst->getName().contains(InstStr);
});
}
static bool isExplicitUnalign(const CodeGenInstruction *Inst) {
return any_of(ExplicitUnalign, [Inst](const char *InstStr) {
- return Inst->TheDef->getName().contains(InstStr);
+ return Inst->getName().contains(InstStr);
});
}
@@ -96,8 +96,8 @@ class X86FoldTablesEmitter {
void print(raw_ostream &OS) const {
OS.indent(2);
- OS << "{X86::" << RegInst->TheDef->getName() << ", ";
- OS << "X86::" << MemInst->TheDef->getName() << ", ";
+ OS << "{X86::" << RegInst->getName() << ", ";
+ OS << "X86::" << MemInst->getName() << ", ";
std::string Attrs;
if (FoldLoad)
@@ -673,7 +673,7 @@ void X86FoldTablesEmitter::run(raw_ostream &OS) {
const Record *AsmWriter = Target.getAsmWriter();
unsigned Variant = AsmWriter->getValueAsInt("Variant");
auto FixUp = [&](const CodeGenInstruction *RegInst) {
- StringRef RegInstName = RegInst->TheDef->getName();
+ StringRef RegInstName = RegInst->getName();
if (RegInstName.ends_with("_REV") || RegInstName.ends_with("_alt"))
if (auto *RegAltRec = Records.getDef(RegInstName.drop_back(4)))
RegInst = &Target.getInstruction(RegAltRec);
@@ -702,7 +702,7 @@ void X86FoldTablesEmitter::run(raw_ostream &OS) {
}
// Broadcast tables
- StringRef MemInstName = MemInst->TheDef->getName();
+ StringRef MemInstName = MemInst->getName();
if (!MemInstName.contains("mb") && !MemInstName.contains("mib"))
continue;
RegInstsIt = RegInstsForBroadcast.find(Opc);
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index 2e8351c951980..9f7e679edeeaa 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -98,8 +98,8 @@ void X86InstrMappingEmitter::printTable(ArrayRef<Entry> Table, StringRef Name,
// Print all entries added to the table
for (const auto &Pair : Table)
- OS << " { X86::" << Pair.first->TheDef->getName()
- << ", X86::" << Pair.second->TheDef->getName() << " },\n";
+ OS << " { X86::" << Pair.first->getName()
+ << ", X86::" << Pair.second->getName() << " },\n";
OS << "};\n\n";
@@ -260,7 +260,7 @@ void X86InstrMappingEmitter::emitCompressEVEXTable(
<< " default: return true;\n";
for (const auto &[Key, Val] : PredicateInsts) {
for (const auto &Inst : Val)
- OS << " case X86::" << Inst->TheDef->getName() << ":\n";
+ OS << " case X86::" << Inst->getName() << ":\n";
OS << " return " << Key << ";\n";
}
OS << " }\n";
diff --git a/llvm/utils/TableGen/X86MnemonicTables.cpp b/llvm/utils/TableGen/X86MnemonicTables.cpp
index f469fcabf7c3a..85bd4df0d4362 100644
--- a/llvm/utils/TableGen/X86MnemonicTables.cpp
+++ b/llvm/utils/TableGen/X86MnemonicTables.cpp
@@ -70,11 +70,11 @@ void X86MnemonicTablesEmitter::run(raw_ostream &OS) {
auto Mnemonics = MnemonicToCGInstrMap[Mnemonic];
if (Mnemonics.size() == 1) {
const CodeGenInstruction *CGI = *Mnemonics.begin();
- OS << "\treturn Opcode == " << CGI->TheDef->getName() << ";\n}\n\n";
+ OS << "\treturn Opcode == " << CGI->getName() << ";\n}\n\n";
} else {
OS << "\tswitch (Opcode) {\n";
for (const CodeGenInstruction *CGI : Mnemonics) {
- OS << "\tcase " << CGI->TheDef->getName() << ":\n";
+ OS << "\tcase " << CGI->getName() << ":\n";
}
OS << "\t\treturn true;\n\t}\n\treturn false;\n}\n\n";
}
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