[llvm] [RISCV] Reorganize select lowering to pull binop expansion early (PR #156974)

[Philip Reames via llvm-commits]

preames wrote:

> It isn't quite NFC because it undoes the arithmetic lowering for the select c, simm12, 0 cases for a processor with both conditional move forwarding and zicond.

@topperc It's not really clear what I should do for the configuration mentioned above.  Do you actually have such a processor?  If so, how do you want the codegen to look for this case?

https://github.com/llvm/llvm-project/pull/156974