[llvm] [RISCV][VLOPT] Support segmented store instructions (PR #155467)

[Min-Yih Hsu via llvm-commits]

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mshockwave wrote:

> I'm not sure why this test isn't getting optimized on RV64

The VL candidate in that case is the `%evl` function argument, for RV32 we can just use it. But for RV64 we have to sign-extend that with add.uw, and it just so happens that the add.uw did not dominate the vnsrl instructions whose VLs are subject to be reduced.

https://github.com/llvm/llvm-project/pull/155467