[llvm] [NFC][MC][ARM] Reorder decoder functions 5/N (PR #156920)

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``````````diff
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 1d19bc89c..6f572d775 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -572,10 +572,9 @@ static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
   return MCDisassembler::Success;
 }
 
-static const MCPhysReg QQPRDecoderTable[] = {
-     ARM::Q0_Q1,  ARM::Q1_Q2,  ARM::Q2_Q3,  ARM::Q3_Q4,
-     ARM::Q4_Q5,  ARM::Q5_Q6,  ARM::Q6_Q7
-};
+static const MCPhysReg QQPRDecoderTable[] = {ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3,
+                                             ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6,
+                                             ARM::Q6_Q7};
 
 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                              uint64_t Address,
@@ -589,9 +588,8 @@ static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
 }
 
 static const MCPhysReg QQQQPRDecoderTable[] = {
-     ARM::Q0_Q1_Q2_Q3,  ARM::Q1_Q2_Q3_Q4,  ARM::Q2_Q3_Q4_Q5,
-     ARM::Q3_Q4_Q5_Q6,  ARM::Q4_Q5_Q6_Q7
-};
+    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6,
+    ARM::Q4_Q5_Q6_Q7};
 
 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t Address,
@@ -1424,7 +1422,8 @@ static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
   // return failure here.  The '01' imod value is unprintable, so there's
   // nothing useful we could do even if we returned UNPREDICTABLE.
 
-  if (imod == 1) return MCDisassembler::Fail;
+  if (imod == 1)
+    return MCDisassembler::Fail;
 
   if (imod && M) {
     Inst.setOpcode(ARM::CPS3p);
@@ -1435,11 +1434,13 @@ static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
     Inst.setOpcode(ARM::CPS2p);
     Inst.addOperand(MCOperand::createImm(imod));
     Inst.addOperand(MCOperand::createImm(iflags));
-    if (mode) S = MCDisassembler::SoftFail;
+    if (mode)
+      S = MCDisassembler::SoftFail;
   } else if (!imod && M) {
     Inst.setOpcode(ARM::CPS1p);
     Inst.addOperand(MCOperand::createImm(mode));
-    if (iflags) S = MCDisassembler::SoftFail;
+    if (iflags)
+      S = MCDisassembler::SoftFail;
   } else {
     // imod == '00' && M == '0' --> UNPREDICTABLE
     Inst.setOpcode(ARM::CPS1p);
@@ -2488,9 +2489,12 @@ static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
                                             const MCDisassembler *Decoder) {
   unsigned type = fieldFromInstruction(Insn, 8, 4);
   unsigned align = fieldFromInstruction(Insn, 4, 2);
-  if (type == 6 && (align & 2)) return MCDisassembler::Fail;
-  if (type == 7 && (align & 2)) return MCDisassembler::Fail;
-  if (type == 10 && align == 3) return MCDisassembler::Fail;
+  if (type == 6 && (align & 2))
+    return MCDisassembler::Fail;
+  if (type == 7 && (align & 2))
+    return MCDisassembler::Fail;
+  if (type == 10 && align == 3)
+    return MCDisassembler::Fail;
 
   unsigned load = fieldFromInstruction(Insn, 21, 1);
   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
@@ -2501,12 +2505,15 @@ static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
                                             uint64_t Address,
                                             const MCDisassembler *Decoder) {
   unsigned size = fieldFromInstruction(Insn, 6, 2);
-  if (size == 3) return MCDisassembler::Fail;
+  if (size == 3)
+    return MCDisassembler::Fail;
 
   unsigned type = fieldFromInstruction(Insn, 8, 4);
   unsigned align = fieldFromInstruction(Insn, 4, 2);
-  if (type == 8 && align == 3) return MCDisassembler::Fail;
-  if (type == 9 && align == 3) return MCDisassembler::Fail;
+  if (type == 8 && align == 3)
+    return MCDisassembler::Fail;
+  if (type == 9 && align == 3)
+    return MCDisassembler::Fail;
 
   unsigned load = fieldFromInstruction(Insn, 21, 1);
   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
@@ -2517,10 +2524,12 @@ static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
                                             uint64_t Address,
                                             const MCDisassembler *Decoder) {
   unsigned size = fieldFromInstruction(Insn, 6, 2);
-  if (size == 3) return MCDisassembler::Fail;
+  if (size == 3)
+    return MCDisassembler::Fail;
 
   unsigned align = fieldFromInstruction(Insn, 4, 2);
-  if (align & 2) return MCDisassembler::Fail;
+  if (align & 2)
+    return MCDisassembler::Fail;
 
   unsigned load = fieldFromInstruction(Insn, 21, 1);
   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
@@ -2531,7 +2540,8 @@ static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
                                             uint64_t Address,
                                             const MCDisassembler *Decoder) {
   unsigned size = fieldFromInstruction(Insn, 6, 2);
-  if (size == 3) return MCDisassembler::Fail;
+  if (size == 3)
+    return MCDisassembler::Fail;
 
   unsigned load = fieldFromInstruction(Insn, 21, 1);
   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
@@ -3059,21 +3069,21 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
 
   if (Rt == 15) {
     switch (Inst.getOpcode()) {
-      case ARM::t2LDRBpci:
-      case ARM::t2LDRHpci:
-        Inst.setOpcode(ARM::t2PLDpci);
-        break;
-      case ARM::t2LDRSBpci:
-        Inst.setOpcode(ARM::t2PLIpci);
-        break;
-      case ARM::t2LDRSHpci:
-        return MCDisassembler::Fail;
-      default:
-        break;
+    case ARM::t2LDRBpci:
+    case ARM::t2LDRHpci:
+      Inst.setOpcode(ARM::t2PLDpci);
+      break;
+    case ARM::t2LDRSBpci:
+      Inst.setOpcode(ARM::t2PLIpci);
+      break;
+    case ARM::t2LDRSHpci:
+      return MCDisassembler::Fail;
+    default:
+      break;
     }
   }
 
-  switch(Inst.getOpcode()) {
+  switch (Inst.getOpcode()) {
   case ARM::t2PLDpci:
     break;
   case ARM::t2PLIpci:

``````````

</details>


https://github.com/llvm/llvm-project/pull/156920